Camera device

Abstract

A camera device according to one embodiment of the present disclosure includes a photoelectric conversion layer, a first pixel electrode, a second pixel electrode, a shielding electrode, and a first shielding via. The photoelectric conversion layer converts incident light into electric charges. The first pixel electrode collects electric charges generated by the photoelectric conversion layer. The second pixel electrode collects electric charges generated by the photoelectric conversion layer. The second pixel electrode is adjacent to the first pixel electrode in a first direction. The shielding electrode is electrically separated from the first pixel electrode and the second pixel electrode. The first shielding via extends from the shielding electrode. In a plan view, the first shielding via is located between the first pixel electrode and the second pixel electrode.

Description

Technical Field

[0001] The present disclosure relates to an imaging device. Background Art

[0002] A stacked-type imaging device is known. In the stacked-type imaging device, a stacked structure including a semiconductor substrate and a photoelectric conversion layer is formed.

[0003] An example of a stacked-type imaging device is described in Patent Documents 1 and 2. In the imaging devices of Patent Documents 1 and 2, a photoelectric conversion layer is disposed between a counter electrode and a pixel electrode.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2013 / 001809

[0007] Patent Document 2: Japanese Patent Application Publication No. 2016-127264 Summary of the invention

[0008] Problems to be Solved by the Invention

[0009] Technology that can obtain higher resolution images is needed.

[0010] Means for solving problems

[0011] An imaging device according to one embodiment of the present disclosure includes:

[0012] Photoelectric conversion layer, converting incident light into electric charge;

[0013] a first pixel electrode for collecting charges generated by the photoelectric conversion layer;

[0014] a second pixel electrode, collecting charges generated by the photoelectric conversion layer and adjacent to the first pixel electrode in the first direction;

[0015] a shielding electrode electrically separated from the first pixel electrode and the second pixel electrode; and

[0016] The first shielding via extends from the shielding electrode and is located between the first pixel electrode and the second pixel electrode in a plan view.

[0017] Effects of the Invention

[0018] The present disclosure provides a technology for obtaining a high-resolution image. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a diagram showing a cross-sectional structure of an imaging device according to an embodiment.

[0020] Figure 2 It is a diagram showing a cross-sectional structure of an imaging device according to an embodiment.

[0021] Figure 3 It is a diagram showing a planar structure of an imaging device according to an embodiment.

[0022] Figure 4A It is a diagram showing a cross-sectional structure of an imaging device according to an embodiment.

[0023] Figure 4B yes Figure 4A Partially enlarged view.

[0024] Figure 4C It means Figure 4B The examples are diagrams of the insulating portion involved in different examples.

[0025] Figure 4D It is a schematic diagram showing a method for manufacturing an insulating layer and a photoelectric conversion layer.

[0026] Figure 4E It is a schematic diagram showing a method for manufacturing an insulating layer and a photoelectric conversion layer.

[0027] Figure 5A It is a diagram showing a cross-sectional structure of an imaging device according to an embodiment.

[0028] Figure 5B yes Figure 5A Partially enlarged view.

[0029] Figure 6 It is a diagram showing a protruding portion of a photoelectric conversion layer.

[0030] Figure 7 It is a diagram showing a cross-sectional structure of an imaging device according to an embodiment.

[0031] Figure 8 It is a diagram showing a planar structure of an imaging device according to an embodiment.

[0032] Fig.9A It is a diagram showing a planar structure of an imaging device according to an embodiment.

[0033] Fig. 9B yes Fig.9A Partially enlarged view.

[0034] Fig. 9C is with Fig. 9B The examples are enlarged views of the parts involved in the different examples.

[0035] Fig.9D yes Fig.9A Partially enlarged view.

[0036] Fig.9E yes Fig.9A Partially enlarged view.

[0037] Fig.10 is a block diagram of the camera system. DETAILED DESCRIPTION

[0038] (Overview of one embodiment of the present disclosure)

[0039] A first aspect of the present disclosure provides an imaging device including:

[0040] Photoelectric conversion layer, converting incident light into electric charge;

[0041] a first pixel electrode for collecting charges generated by the photoelectric conversion layer;

[0042] a second pixel electrode, collecting charges generated by the photoelectric conversion layer and adjacent to the first pixel electrode in the first direction;

[0043] a shielding electrode electrically separated from the first pixel electrode and the second pixel electrode; and

[0044] The first shielding via extends from the shielding electrode and is located between the first pixel electrode and the second pixel electrode in a plan view.

[0045] The first method is suitable for obtaining a high-resolution image.

[0046] In a second aspect of the present disclosure, for example, the imaging device according to the first aspect may further include:

[0047] a third pixel electrode that collects charges generated by the photoelectric conversion layer and is adjacent to the first pixel electrode in a second direction different from the first direction; and

[0048] The second shielding via extends from the shielding electrode and is located between the first pixel electrode and the third pixel electrode in the plan view.

[0049] The second method is suitable for obtaining a high-resolution image.

[0050] In a third aspect of the present disclosure, for example, the imaging device according to the first aspect may further include:

[0051] a third pixel electrode that collects charges generated by the photoelectric conversion layer and is adjacent to the first pixel electrode in a second direction different from the first direction;

[0052] a fourth pixel electrode that collects charges generated by the photoelectric conversion layer and is adjacent to the second pixel electrode in the second direction and adjacent to the third pixel electrode in the first direction; and

[0053] The third shielding via extends from the shielding electrode and is located between the first pixel electrode and the fourth pixel electrode in the plan view.

[0054] The third method is suitable for obtaining a high-resolution image.

[0055] In a fourth aspect of the present disclosure, for example, the imaging device according to the second aspect may further include:

[0056] a fourth pixel electrode that collects charges generated by the photoelectric conversion layer and is adjacent to the second pixel electrode in the second direction and adjacent to the third pixel electrode in the first direction; and

[0057] The third shielding via extends from the shielding electrode and is located between the first pixel electrode and the fourth pixel electrode in the plan view.

[0058] The fourth method is suitable for obtaining a high-resolution image.

[0059] In a fifth aspect of the present disclosure, for example, the imaging device according to any one of the first to fourth aspects may further include:

[0060] a first pixel via hole extending from the first pixel electrode; and

[0061] The second pixel via hole extends from the second pixel electrode.

[0062] The first pixel via hole of the fifth aspect can electrically connect the first pixel electrode to another element. The second pixel via hole can electrically connect the second pixel electrode to another element.

[0063] In a sixth aspect of the present disclosure, for example, in the imaging device according to the fifth aspect,

[0064] In the plan view, the first shielding via hole may also be located between the first pixel via hole and the second pixel via hole.

[0065] The sixth method is suitable for obtaining high-resolution images.

[0066] In a seventh aspect of the present disclosure, for example, the imaging device according to any one of the first to sixth aspects may further include:

[0067] 1st wiring layer,

[0068] The first shield via may extend from the shield electrode to the first wiring layer.

[0069] The seventh method is suitable for obtaining high-resolution images.

[0070] In an eighth aspect of the present disclosure, for example, the imaging device according to any one of the first to seventh aspects may further include:

[0071] The insulating portion is located between the shielding electrode and the photoelectric conversion layer.

[0072] The eighth aspect is suitable for obtaining a high-resolution image by the shielding electrode while suppressing a decrease in the sensitivity of the imaging device due to the shielding electrode.

[0073] In a ninth aspect of the present disclosure, for example, in the imaging device according to the eighth aspect,

[0074] In the plan view, the insulating portion may include a portion that does not overlap with the shield electrode.

[0075] The ninth method is suitable for obtaining high-resolution images.

[0076] An imaging device according to a tenth aspect of the present disclosure includes:

[0077] Photoelectric conversion layer, converting incident light into electric charge;

[0078] a first pixel electrode for collecting charges generated by the photoelectric conversion layer;

[0079] a shielding electrode electrically separated from the first pixel electrode; and

[0080] an insulating portion, located between the shielding electrode and the photoelectric conversion layer,

[0081] The insulating portion includes a portion that does not overlap with the shielding electrode in a plan view.

[0082] The tenth aspect is suitable for obtaining a high-resolution image by the shielding electrode while suppressing a decrease in the sensitivity of the imaging device due to the shielding electrode.

[0083] In an eleventh aspect of the present disclosure, for example, in the imaging device according to the ninth aspect or the tenth aspect,

[0084] The insulating portion may be separated from the first pixel electrode in the plan view.

[0085] The eleventh aspect is suitable for obtaining a high-resolution image by capturing signal charges through the first pixel electrode.

[0086] In a twelfth aspect of the present disclosure, for example, in the imaging device according to any one of the eighth to eleventh aspects,

[0087] The insulating portion may also have a film shape,

[0088] The thickness of the film shape may be 10 nm or more.

[0089] The twelfth aspect is suitable for suppressing a decrease in the sensitivity of the imaging device due to the shield electrode.

[0090] In a thirteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twelfth aspects,

[0091] The surface of the first pixel electrode and the surface of the shielding electrode may be on the same plane.

[0092] The imaging device according to the thirteenth aspect is easy to manufacture.

[0093] In a fourteenth aspect of the present disclosure, for example, the imaging device according to any one of the first to thirteenth aspects may be a color image sensor.

[0094] In a color image sensor, the technology of the first aspect can contribute to suppressing color mixing.

[0095] A fifteenth aspect of the present disclosure provides an imaging device including:

[0096] Photoelectric conversion layer, converting incident light into electric charge;

[0097] a first pixel electrode for collecting charges generated by the photoelectric conversion layer;

[0098] a shielding electrode electrically separated from the first pixel electrode; and

[0099] The insulating portion is located between the shielding electrode and the photoelectric conversion layer.

[0100] In this specification, the term "via" is sometimes used. In this specification, a via hole and a conductor inside it are collectively referred to as a "via".

[0101] In this specification, the terms "shielding via" and "pixel via" are sometimes used. In the exemplary embodiments shown below, the shielding via extends from the shielding electrode. The pixel via extends from the pixel electrode. The distinction between the terms shielding via and pixel via is for convenience of description and is not intended to limit the characteristics of the via.

[0102] In this specification, ordinal numbers such as 1st, 2nd, 3rd, etc. may be used. When an ordinal number is added to a certain element, it is not necessary that there are elements of the same type with a smaller order. The number of the ordinal number can be changed as needed.

[0103] The embodiments described below all represent general or specific examples. The numerical values, shapes, materials, constituent elements, configurations and connection methods of constituent elements, steps, the order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various methods described in this specification can be combined with each other as long as no contradiction occurs. In addition, among the structural elements in the following embodiments, the structural elements that are not recorded in the independent claims representing the highest concept are described as arbitrary structural elements. In the following description, constituent elements having substantially the same function are represented by common reference marks, and repeated descriptions are sometimes omitted or simplified.

[0104] The general or specific manner may also be implemented by a component, device, apparatus, system, integrated circuit, method or computer program. In addition, the general or specific manner may also be implemented by any combination of components, devices, apparatus, systems, integrated circuits, methods and computer programs. The additional effects and advantages of the disclosed embodiments are clear from the description and drawings. The effects and / or advantages are provided separately by various embodiments or features disclosed in the description and drawings, and not all are required to obtain more than one of them.

[0105] Various elements shown in the drawings are merely schematically shown for the purpose of understanding the present disclosure, and dimensional ratios, appearances, and the like may differ from actual objects.

[0106] The imaging device according to one embodiment of the present disclosure has a photoelectric conversion layer for converting light into an electrical signal, i.e., performing photoelectric conversion, on the upper layer, and a signal processing circuit including a silicon-based CMOS (Complementary Metal Oxide Semiconductor) circuit for taking out the electrical signal obtained in the photoelectric conversion unit to the outside on the lower layer. In this way, in the imaging device according to one embodiment of the present disclosure, the photoelectric conversion unit and the signal processing circuit are stacked, so they can be designed independently.

[0107] [Implementation Method]

[0108] exist Figure 1 and Figure 2 , a cross-sectional view of an imaging device 100 according to an embodiment is shown.

[0109] The imaging device 100 includes a semiconductor substrate 1 and a pixel unit 30 . The pixel unit 30 is provided on the semiconductor substrate 1 .

[0110] The pixel portion 30 includes a plurality of pixel electrodes 3, an opposing electrode 5, and a photoelectric conversion layer 4. The photoelectric conversion layer 4 is disposed between the pixel electrode 3 and the opposing electrode 5. The photoelectric conversion layer 4 has a film shape.

[0111] The pixel portion 30 includes a detection circuit 12 . A part of the detection circuit 12 is provided in the semiconductor substrate 1 . The detection circuit 12 detects the potential of the pixel electrode 3 .

[0112] The pixel portion 30 includes an insulating layer 2 . The insulating layer 2 is disposed between the photoelectric conversion layer 4 and the semiconductor substrate 1 .

[0113] In the pixel portion 30, the detection circuit 12 is configured so as to straddle the interface between the semiconductor substrate 1 and the insulating layer 2. Specifically, the detection circuit 12 corresponding to each of the plurality of pixels 20 is configured.

[0114] In the following, for the convenience of explanation, the terms such as X-axis, Y-axis and Z-axis are sometimes used. These axes are mutually orthogonal. In addition, for the convenience of explanation, the positive side in the Z-axis direction is sometimes referred to as the top. The main surface on the positive side in the Z-axis direction is sometimes referred to as the upper surface. In this example, the upper surface is the surface on the side close to the incident side of the light. The lower surface is the surface on the side far from the incident side of the light. In this example, the up and down direction is the direction perpendicular to the surface of the semiconductor substrate 1.

[0115] A pixel electrode 3 is formed on the upper surface of the insulating layer 2. A pixel via 13 is connected to the pixel electrode 3. The pixel via 13 extends from the pixel electrode 3 to the first wiring layer 14. The first wiring layer 14 is the layer closest to the pixel electrode 3 among the plurality of wiring layers. The pixel via 13 electrically connects the pixel electrode 3, the wiring layer, and the detection circuit 12 corresponding to the pixel electrode 3.

[0116] Each of the plurality of pixels 20 includes a photoelectric conversion section 11. The photoelectric conversion section 11 includes a pixel electrode 3, an opposing electrode 5, and a photoelectric conversion layer 4. As described above, the photoelectric conversion layer 4 is disposed between the pixel electrode 3 and the opposing electrode 5.

[0117] The photoelectric conversion layer 4 converts incident light into electric charges.

[0118] The pixel electrode 3 collects the charges generated by the photoelectric conversion layer 4 .

[0119] An example of the material of the pixel electrode 3 is a metal compound such as titanium nitride (TiN). Other examples of the material of the pixel electrode 3 are metals such as copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al). The material of the pixel electrode 3 may also be a compound or alloy formed by selecting at least two of these metals. The pixel electrode 3 may also include a stacked structure formed by selecting at least two of these metals. The stacked structure is, for example, a TiN / Ti structure. The TiN / Ti structure is a stacked structure formed by bonding a layer of titanium nitride to a layer of titanium.

[0120] In a specific example, the film thickness of each of the plurality of pixel electrodes 3 is uniform. The upper surface of each of the plurality of pixel electrodes 3 is flat.

[0121] like Figure 1 As shown in the cross-sectional view of , a plurality of pixel electrodes 3 are located between the photoelectric conversion layer 4 and the semiconductor substrate 1 .

[0122] like Figure 3 As shown in the plan view of FIG. 2 , the plurality of pixel electrodes 3 are arranged in a two-dimensional direction extending in the X-axis direction and the Y-axis direction. The plurality of pixel electrodes 3 are arranged on the upper surface of the insulating layer 2 .

[0123] In a specific example, the plurality of pixel electrodes 3 are arranged in a matrix. Here, the expression that the plurality of elements are arranged in a matrix means that the center of each element is located at an intersection of the grid. The plurality of pixel electrodes 3 are spaced at a certain distance from each other.

[0124] The pixel electrodes 3 are arranged in accordance with the arrangement of the pixels 20. In one example, the plurality of pixels 20 are arranged in a matrix. The plurality of pixel electrodes 3 are arranged in accordance with the arrangement of the plurality of pixels 20 in a matrix.

[0125] Refer again Figure 1 As described above, in the imaging device 100, the detection circuits 12 are configured to correspond to the respective pixels 20. The detection circuits 12 detect signal charges collected by the corresponding pixel electrodes 3 and output signal voltages corresponding to the charges.

[0126] The detection circuit 12 includes, for example, a MOS (Metal Oxide Semiconductor) circuit, a TFT (Thin Film Transistor) circuit, etc. The detection circuit 12 includes, for example, an amplifier transistor whose gate is electrically connected to the pixel electrode 3, and the amplifier transistor outputs a signal voltage corresponding to the amount of signal charge. The detection circuit 12 may also be shielded by a light shielding layer provided inside the insulating layer 2, etc. The light shielding layer is omitted in the illustration.

[0127] The pixel via 13 electrically connects the pixel electrode 3 of each pixel 20 , the wiring layer, and the detection circuit 12 corresponding to the pixel electrode 3 .

[0128] Examples of the material of the pixel via hole 13 include conductive materials such as copper (Cu), tungsten (W), and cobalt (Co). The pixel via hole 13 is buried in the insulating layer 2 .

[0129] The insulating layer 2 is formed on the semiconductor substrate 1. The insulating layer 2 includes a plurality of constituent layers 2a, 2b, 2c, 2d, and 2e.

[0130] The semiconductor substrate 1 is made of, for example, silicon (Si), etc. The plurality of constituent layers 2a, 2b, 2c, 2d, and 2e are made of, for example, silicon dioxide (SiO2), silicon oxycarbide film (SiOC), etc.

[0131] A wiring layer is embedded in each of the constituent layers 2a, 2b, 2c, 2d, and 2e. The wiring layer has wiring. The wiring layers are connected to each other by vias. Therefore, although an insulator of the insulating layer 2 is provided between the wiring layers, the wiring layers are electrically connected to each other by vias. In addition, the number of constituent layers in the insulating layer 2 can be set arbitrarily and is not limited to Figure 1 The example shown is a five-layer structure of the layers 2a, 2b, 2c, 2d and 2e. The same is true for the number of wiring layers.

[0132] A pixel electrode 3 is arranged on the constituent layer 2e. A photoelectric conversion layer 4 is stacked on the upper surface of the constituent layer 2e and the pixel electrode 3. On the upper surface of the photoelectric conversion layer 4, an opposing electrode 5, a buffer layer 6 and a sealing layer 7 are stacked in the order of the opposing electrode 5, the buffer layer 6 and the sealing layer 7. On the upper surface of the sealing layer 7, a color filter 8 of a transmission band corresponding to each pixel 20 is arranged. A planarization layer 9 is arranged on the upper surface of the color filter 8. A microlens 10 is arranged on the upper surface of the planarization layer 9. In addition, a constituent layer in which an insulating layer 2 is provided is inserted in the gap between adjacent pixel electrodes 3.

[0133] In this example, the imaging device 100 is a color image sensor. However, the color filter 8 may be omitted. In other words, the imaging device 100 may be a black-and-white image sensor.

[0134] The photoelectric conversion layer 4 is composed of a photoelectric conversion material that generates electric charge according to the intensity of the received light. The photoelectric conversion material is, for example, an organic semiconductor material, including at least one of a p-type organic semiconductor and an n-type organic semiconductor. In one specific example, the photoelectric conversion layer 4 has a uniform film thickness in the pixel region 30. In another specific example, the photoelectric conversion layer 4 has two or more portions with different film thicknesses in the pixel region 30.

[0135] The counter electrode 5 is opposed to the pixel electrode 3. Specifically, the counter electrode 5 is opposed to the plurality of pixel electrodes 3 and the shielding electrode 61 described later via the photoelectric conversion layer 4 in the pixel portion 30. The counter electrode 5 is arranged on the side of the imaging device 100 where light is incident when viewed from the photoelectric conversion layer 4. The counter electrode 5 may also have light-transmitting properties in order to allow light to be incident on the photoelectric conversion layer 4. Examples of the material of the counter electrode 5 include transparent oxide conductive materials such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0136] The expression "the first element and the second element are opposed to each other with the third element interposed therebetween" should not be interpreted as only referring to the manner in which the first element and the second element are in contact with the third element. For example, the expression "the counter electrode 5 is opposed to the pixel electrode 3 and the shielding electrode 61 with the photoelectric conversion layer 4 interposed therebetween" includes the manner in which the insulating portion 62 described later is interposed between the shielding electrode 61 and the photoelectric conversion layer 4 and the shielding electrode 61 is prevented from contacting the photoelectric conversion layer 4 by the insulating portion 62 interposed therebetween.

[0137] Next, the camera system will be described.

[0138] Light incident on the imaging device 100 from above passes through the sealing layer 7, the buffer layer 6 and the counter electrode 5 and enters the photoelectric conversion layer 4. The photoelectric conversion layer 4 performs photoelectric conversion on the incident light and generates charges in a state where an appropriate bias voltage is applied by the pixel electrode 3 and the counter electrode 5. The bias voltage is a potential difference between the counter electrode 5 and the pixel electrode 3.

[0139] As described above, the charges generated by the photoelectric conversion layer 4 are transferred from the pixel electrode 3 to the storage area in the detection circuit 12 through the pixel via 13 and temporarily stored. Then, the charges are output as signals to the outside of the detection circuit 12 in a timely manner through the switching action of the transistor element in the detection circuit 12.

[0140] (Shielding Electrode)

[0141] In the multilayer imaging device 100 described above, the photoelectric conversion layer 4 is disposed between the pixel electrode 3 and the counter electrode 5. Figure 3 As shown in FIG. 1 , a shielding electrode 61 is disposed in a region 60 between pixel electrodes 3. Specifically, an insulating layer 2 and a shielding electrode 61 are disposed in the region 60. Figure 3 In the figure, the insulating layer 2 is omitted. Figure 3 In the example of FIG. 1 , the region 60 has a lattice shape in a plan view. The plan view refers to, for example, observation along a direction perpendicular to the surface of the semiconductor substrate 1 .

[0142] Assume that there is no shielding electrode 61. In this case, the portion of the photoelectric conversion layer 4 that overlaps with the region 60 in a plan view has a smaller electric field strength applied thereto than the portion that overlaps with the pixel electrode 3. Therefore, in the portion of the photoelectric conversion layer 4 that overlaps with the region 60, the electric field strength to which the signal charge is subjected from the pixel electrode 3 is smaller.

[0143] In the overlapped portion, there may also be signal charges. The signal charges may not reach the pixel electrode 3 that it should reach, but reach the pixel electrode 3 adjacent to it. If the signal charges reaching the adjacent pixel electrode 3 are detected as pixel signals of the adjacent pixel, the resolution is reduced. From the perspective of suppressing the reduction in resolution, a shielding electrode can be used. In the case where the imaging device 100 is a color image sensor, color mixing can be suppressed by using a shielding electrode.

[0144] Hereinafter, the shield electrode will be described with reference to the drawings.

[0145] like Figure 1 As shown in the cross-sectional view of FIG. 1 , the shielding electrode 61 is arranged between the photoelectric conversion layer 4 and the semiconductor substrate 1. Figure 3 As shown, the shielding electrode 61 is electrically separated from the plurality of pixel electrodes 3 .

[0146] In this example, a shielding electrode 61 is arranged in a region 60 between pixel electrodes 3 and pixel electrodes 3. By configuring the shielding electrode 61, a voltage can be applied to the region between two adjacent pixel electrodes 3. Thus, the signal charge 65 generated by the portion of the photoelectric conversion layer 4 that overlaps with the region 60 in a plan view is collected by the shielding electrode 61. Thus, it is possible to suppress the signal charge 65 that should have reached a certain pixel electrode 3 from reaching the adjacent pixel electrode 3. In other words, it is possible to suppress the mixing of signal charges between adjacent pixels. Thus, a high-resolution image can be obtained. In the case where the imaging device 100 is a color image sensor, color mixing between adjacent pixels can be suppressed.

[0147] Examples of the material of the shielding electrode 61 include metals such as copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al). The material of the shielding electrode 61 may also be a compound or alloy formed by selecting at least two of these metals. The shielding electrode 61 may also include a stacked structure formed by selecting at least two of these metals. The stacked structure is, for example, a TiN / Ti structure.

[0148] In a specific example, the film thickness of each shield electrode 61 is uniform. The surface of each shield electrode 61 on the photoelectric conversion layer 4 side is flat.

[0149] exist Figure 1 and Figure 2In the example shown, the surface of the shielding electrode 61 and the surface of the pixel electrode 3 are on the same plane. Specifically, the surface of the shielding electrode 61 that is opposite to the semiconductor substrate 1 and the surface of the pixel electrode 3 that is opposite to the semiconductor substrate 1 are on the same plane. An imaging device having such a structure is easy to manufacture. However, the surface of the shielding electrode 61 and the surface of the pixel electrode 3 may not be on the same plane. Specifically, the surface of the shielding electrode 61 that is opposite to the semiconductor substrate 1 and the surface of the pixel electrode 3 that is opposite to the semiconductor substrate 1 may not be on the same plane.

[0150] The material of the shielding electrode 61 and the material of the pixel electrode 3 may also be the same. In this case, the shielding electrode 61 and the pixel electrode 3 can be formed without separate manufacturing processes. If so, the shielding electrode 61 and the pixel electrode 3 can be formed in the same manufacturing process and with the same mask. Therefore, there is no need to consider the alignment deviation. Here, the alignment deviation refers to the relative positional relationship between the shielding electrode 61 and the pixel electrode 3 deviating from the appropriate range.

[0151] The distance 71 between the pixel electrode 3 and the shielding electrode 61 is, for example, not less than 0.1 μm and not more than 1 μm.

[0152] (Insulating portion between shielding electrode 61 and photoelectric conversion layer 4)

[0153] In such Figure 1 and Figure 2 When the shielding electrode 61 is configured as shown, part of the signal charge 65 generated by the photoelectric conversion layer 4 is collected by the shielding electrode 61. If the signal charge that can be captured by the pixel electrode 3 decreases due to this collection, the sensitivity of the imaging device may be reduced. From the perspective of suppressing the reduction in the sensitivity of the imaging device, an insulating portion may be provided between the shielding electrode 61 and the photoelectric conversion layer 4. Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 5A , Figure 5B and Figure 6 Provide explanation.

[0154] exist Figure 4A and Figure 4BIn the example of , an insulating portion 62 is provided between the shielding electrode 61 and the photoelectric conversion layer 4. The insulating portion 62 is an insulator. By providing such an insulating portion 62, it is possible to maintain a state where an electric field is applied between the region between two adjacent pixel electrodes 3 and the counter electrode 5, and suppress the flow of signal charges into the shielding electrode 61, thereby suppressing the reduction in sensitivity of the imaging device. Therefore, this example is suitable for suppressing the reduction in sensitivity of the imaging device caused by the shielding electrode 61, and obtaining a high-resolution image through the shielding electrode 61.

[0155] exist Figure 4A and Figure 4B In the example of FIG. 5 , the insulating portion 62 covers the shield electrode 61 . Specifically, the insulating portion 62 covers the entire surface of the shield electrode 61 on the photoelectric conversion layer 4 side.

[0156] exist Figure 4A and Figure 4B In the example of FIG. 5 , the insulating portion 62 is in contact with the shielding electrode 61. Specifically, the insulating portion 62 is in contact with the entire surface of the shielding electrode 61 on the side close to the photoelectric conversion layer 4. The insulating portion 62 prevents the shielding electrode 61 from contacting the photoelectric conversion layer 4.

[0157] like Figure 4C As shown, in a plan view, the insulating portion 62 may include a portion extending from the shielding electrode 61 and not overlapping with the shielding electrode 61. If so, in a plan view, part or all of the outline of the insulating portion 62 can be made outside the outline of the shielding electrode 61. If so, the electric field in the upward direction from the end of the shielding electrode 61 toward the photoelectric conversion layer 4 can be suppressed. This is advantageous from the perspective of ensuring the insulation between the shielding electrode 61 and the pixel electrode 3, for example. In addition, in a plan view, the insulating portion 62 extends from the shielding electrode 61, which is advantageous from the perspective of suppressing signal charges from bypassing the insulating portion 62 from the side and flowing into the shielding electrode 61. Therefore, Figure 4C This method is suitable for obtaining high-resolution images.

[0158] In addition, the insulating portion 62 protrudes from the shielding electrode 61 in a plan view, which means that the insulating portion 62 includes a portion that exists outside the outline of the shielding electrode 61 in a plan view. It can also be said that the shielding electrode 61 includes a portion that exists inside the outline of the insulating portion 62 in a plan view. To explain in more detail, the insulating portion 62 protrudes from the shielding electrode 61 in a plan view is a concept that includes not only a case where the outline of the insulating portion 62 exists entirely outside the outline of the shielding electrode 61 in a plan view, but also a case where only a portion of the outline of the insulating portion 62 exists outside the outline of the shielding electrode 61 in a plan view. In a plan view, the outline of the insulating portion 62 may exist entirely outside the outline of the shielding electrode 61, or only a portion of the outline of the insulating portion 62 may exist outside the outline of the shielding electrode 61.

[0159] In a specific example, the insulating portion 62 is separated from each pixel electrode 3 in a plan view. In this case, the pixel electrode 3 is less likely to be hindered from capturing signal charges by the insulating portion 62. This is suitable for obtaining a high-resolution image.

[0160] The insulating portion 62 may cover a portion of the pixel electrode 3 .

[0161] exist Figure 4A and Figure 4B In the example of , the pixel electrode 3 and the photoelectric conversion layer 4 are electrically connected. Specifically, the pixel electrode 3 is in contact with the photoelectric conversion layer 4. However, a blocking layer may be provided between the pixel electrode 3 and the photoelectric conversion layer 4. The blocking layer allows the signal charge in the charge pair generated by photoelectric conversion in the photoelectric conversion layer 4 to pass through, and blocks the charge that is not the signal charge from being injected from the pixel electrode 3. Thus, the signal charge can be effectively transported to the pixel electrode 3. The blocking layer shows selective charge transport properties, and therefore does not correspond to an insulator.

[0162] Examples of the material of the insulating portion 62 are silicon dioxide (SiO2), silicon carbide (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN), etc. Other examples of the material of the insulating portion 62 are copper (Cu) compounds, titanium (Ti) compounds, tantalum (Ta) compounds, aluminum (Al) compounds, etc. The insulating portion 62 may also include a stacked structure formed by selecting at least two of these materials.

[0163] The material of the insulating portion 62 may be the same as or different from the material of the insulating layer 2 .

[0164] Typically, the insulating portion 62 has a film shape. In this example, the thickness direction of the film shape coincides with a direction perpendicular to the surface of the semiconductor substrate 1 .

[0165] The thickness of the film shape is, for example, 10 nm or more. By making the thickness of the film shape large to this extent, it is possible to suppress the signal charge from penetrating the insulating portion 62 by the tunnel effect. Therefore, it is possible to suppress the signal charge from being captured by the shielding electrode 61. Therefore, setting the thickness of the film shape to 10 nm or more is suitable for suppressing the reduction in sensitivity of the imaging device caused by the shielding electrode 61. The thickness of the film shape may also be 20 nm or more.

[0166] The thickness of the film shape is, for example, less than 500 nm. By making the thickness of the film shape small to this extent, when a voltage is applied to the shielding electrode 61, it is easy to collect the signal charge around the shielding electrode 61. If the signal charge generated between the pixel electrodes 3 is collected near the shielding electrode 61, it is possible to suppress the signal charge from being captured outside the desired pixel electrode 3. Therefore, setting the thickness of the film shape to less than 500 nm is suitable for obtaining a high-resolution image through the shielding electrode 61. The thickness of the film shape can also be less than 300 nm.

[0167] If the thickness of the film shape is adjusted to an appropriate range, the signal charge captured by the shielding electrode 61 is reduced to a substantially negligible level, and the signal charge generated between the pixel electrodes can be collected near the shielding electrode 61, so it is easy to suppress the signal charge from being captured outside the desired pixel electrode 3. Therefore, it is easy to suppress the reduction in sensitivity of the imaging device due to the shielding electrode 61, and obtain an image with high resolution.

[0168] The thickness of the film shape can be determined by a known method. The thickness of the film shape can be determined, for example, as follows. First, an electron microscope image of a cross section of the film shape is obtained. Next, the image is used to measure the thickness at any number of measurement points (e.g., 5 points) of the film shape. The average value of the thickness of these multiple measurement points is used as the thickness of the film shape.

[0169] In addition, in the following Figure 5A and Figure 5B In the case where the above-described exemplary determination method is applied in the example, the side surface 62c portion is excluded from the measurement point, and the measurement point is set at the upper surface 62a portion.

[0170] The method for forming the insulating portion 62 is not particularly limited.

[0171] In one example, the insulating portion 62 is formed as follows. A layer of the material of the insulating portion 62 is formed on the shielding electrode 61 (typically, the entire upper surface of the shielding electrode 61). Next, a portion of the layer is removed. In this way, the insulating portion 62 is obtained. In this way, a film-shaped insulating portion 62 can also be obtained.

[0172] The layer of the material of the insulating portion 62 can be formed by, for example, chemical vapor deposition (CVD). A portion of the layer of the material of the insulating portion 62 can be removed by, for example, photolithography, etching, or the like.

[0173] In a plan view, the insulating portion 62 may cover the entire upper surface of the shielding electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61, and a portion of the pixel electrode 3. In this way, the position of the step formed at the end of the insulating portion 62 can be made on the pixel electrode 3. For the advantages obtained by making the position of the step on the pixel electrode 3, refer to Figure 4D and Figure 4E Provide explanation. Figure 4D and Figure 4E It is a schematic diagram showing a method for manufacturing the insulating layer 2 and the photoelectric conversion layer 4 .

[0174] exist Figure 4D Part (a) and Figure 4E In the portion (a), the pixel electrode 3 and the shielding electrode 61 are covered by a layer 62x of the material of the insulating portion 62. A portion of the layer 62x is covered by a mask 81. The portion of the layer 62x not covered by the mask 81 is removed by etching.

[0175] In addition, Figure 4D Part (a) and Figure 4E In part (a), the insulating layer 2 is omitted. Figure 4D and Figure 4E In the related description, it is assumed that the insulating layer 2 exists between the pixel electrode 3 and the shielding electrode 61. Figure 4D and Figure 4E In the related description, before etching is performed, the upper surface of the insulating layer 2 located at the above position is set to be flush with the upper surfaces of the pixel electrode 3 and the upper surfaces of the shielding electrode 61 .

[0176] exist Figure 4D In part (a), the mask 81 covers the entire upper surface of the shielding electrode 61. However, the mask 81 does not cover the upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61. In addition, the mask 81 does not cover the upper surface of the pixel electrode 3. On the other hand, Figure 4E In the portion (a), the mask 81 covers the entire upper surface of the shielding electrode 61 and the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61. Figure 4E In part (a), the mask 81 also partially covers the upper surface of the pixel electrode 3.

[0177] By using Figure 4DBy etching the mask 81 of the portion (a), the insulating portion 62 covering only the entire upper surface of the shield electrode 61 can be obtained. Figure 4E By etching the mask 81 of part (a), it is possible to obtain an insulating portion 62 that covers the entire upper surface of the shielding electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61, and a portion of the upper surface of the pixel electrode 3.

[0178] Figure 4D Part (b) and Figure 4E Part (b) shows a state where the portion of the layer 62x not covered by the mask 81 is removed by etching. The layer 62x is processed into the insulating portion 62 by this removal.

[0179] In reality, it is difficult to cut only layer 62x by etching. Figure 4D If the mask 81 is configured as in the portion (a) of FIG. 1 , the pixel electrode 3 and the insulating layer 2 not covered by the mask 81 are also reduced to some extent. The pixel electrode 3 has a different etching rate than the insulating layer 2, and the reduction degree is different. Figure 4D As shown in the region surrounded by dotted line 84 of the portion (b), the pixel electrode 3 has a different upper surface height than the insulating layer 2. In addition, as shown in the region surrounded by dotted line 85, the insulating portion 62 has a different upper surface height than the insulating layer 2. The difference in upper surface height occurs at the boundary between the portion covered by the mask 81 and the portion not covered. Figure 4D The dot-dashed line 82 in part (b) shows the positions of the upper surfaces of the pixel electrode 3 and the insulating layer 2 .

[0180] The same is true for the case where the mask 81 covers the entire upper surface of the shielding electrode 61 and partially covers the upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61. In this case, the pixel electrode 3 has a difference in upper surface height due to the difference in etching rate compared with the insulating layer 2. In addition, on the insulating layer 2, a difference in upper surface height is generated between the portion where the insulating portion 62 is located and the portion where it is not located. The difference in upper surface height is generated at the boundary between the portion of the insulating layer 62x on the insulating layer 2 covered by the mask 81 and the portion that is not covered.

[0181] In contrast, if Figure 4E The mask 81 is configured as in part (a) of Figure 4E As shown in the dotted line 86 of the portion (b), a difference occurs in the height of the upper surface on the pixel electrode 3. This difference occurs at the boundary between the portion covered by the mask 81 and the portion not covered. However, since the insulating layer 2 is completely covered by the insulating portion 62, no difference occurs in the height of the upper surface on the insulating layer 2. Figure 4DCompared with the case of FIG. 8A , the number of steps on the upper surface formed by etching using the mask 81 can be reduced.

[0182] Figure 4D Part (c) and Figure 4E Part (c) shows a case where the photoelectric conversion layer 4 is formed on the upper surface formed by etching. If the photoelectric conversion layer 4 is formed on the upper surface formed by etching, the shape of the upper surface is also reflected in the shape of the upper surface of the photoelectric conversion layer 4. Figure 4D and Figure 4E The two-dot chain line 83 in the portion (c) indicates the position of the upper surface of the photoelectric conversion layer 4 .

[0183] According to the above explanation, it can be understood that Figure 4E The way and Figure 4D Compared with the method of making the photoelectric conversion layer 4 flat, it is advantageous from the viewpoint of making the shape of the photoelectric conversion layer 4 flat. Therefore, the structure in which the insulating portion 62 covers the entire upper surface of the shielding electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shielding electrode 61, and a part of the upper surface of the pixel electrode 3 can be said to be advantageous from the viewpoint of making the photoelectric conversion layer 4 flat.

[0184] exist Figure 4A , Figure 4B and Figure 4C In the specific example shown, the insulating portion 62 has a film shape. Figure 4B and Figure 4C As shown, the membrane shape has an upper surface 62a, a lower surface 62b and a side surface 62c. The side surface 62c extends from the lower surface 62b to the upper surface 62a. An angle 62d is formed by the upper surface 62a and the side surface 62c. An angle θ is formed between the lower surface 62b and the side surface 62c. The angle θ is relatively large. Specifically, the angle θ is approximately 90°. Therefore, the angle 62d is sharp.

[0185] exist Figure 5A and Figure 5B In another specific example shown, the insulating portion 62 has a film shape. Figure 5A and Figure 5B In the specific example of Figure 4A , Figure 4B and Figure 4C As compared with the specific example of , the angle θ is smaller. In this way, the sharp convexity of the corner 62d is relaxed, and cracks are less likely to occur at the corner 62d when the photoelectric conversion layer 4 is formed. Therefore, the photoelectric conversion layer 4 is less likely to deteriorate in the contact portion with the insulating portion 62.

[0186] The angle θ can be reduced or the sharpness of the angle 62 d can be reduced by, for example, reducing the angle of the insulating portion by a reverse sputtering effect using ions in plasma or by reducing the angle when making the insulating portion flat by CMP (Chemical Mechanical Polishing).

[0187] In reality, if Figure 6 As shown, protrusion 4p may be formed at a position overlapping insulating portion 62 in plan view in photoelectric conversion layer 4. In photoelectric conversion layer 4, protrusion 4p protrudes further in the thickness direction of the film shape of insulating portion 62 than the surrounding portion of protrusion 4p.

[0188] The protrusion width PW of the protrusion 4p may be the same as the thickness TH of the film shape of the insulating portion 62. Figure 6 As shown, the protrusion width PW can be made smaller than the thickness TH. In other words, the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the insulating portion 62 in a plan view can be made thinner than the thickness of the surrounding portion. For example, the protrusion width PW can be reduced by performing a heat treatment on the photoelectric conversion layer 4. In addition, the protrusion width PW being smaller than the thickness TH is a concept that includes the case where the protrusion width PW is zero.

[0189] As can be understood from the above description, the insulating portion 62 can be provided and the protrusion 4p has a small protrusion width PW or no protrusion 4p. If the upper surface of the photoelectric conversion layer 4 has high flatness, the upper layer of the photoelectric conversion layer 4 can be easily manufactured.

[0190] exist Figure 6 In the example, the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the pixel electrode 3 in a plan view is greater than the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the shielding electrode 61 in a plan view. This is suitable for promoting photoelectric conversion in the former portion to capture more signal charges by the pixel electrode 3, and suppressing photoelectric conversion in the latter portion to suppress the capture of signal charges by the shielding electrode 61.

[0191] In addition, the protrusion 4p in the photoelectric conversion layer 4 is Figure 4B The way shown is the case as well as the Figure 4C In any of the above cases, it is possible to form the photoelectric conversion layer 4 in the manner shown. In any of these cases, PW=TH or PW<TH can be set. In any of these cases, a photoelectric conversion layer 4 without a protrusion 4p can be realized. In any of these cases, the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the pixel electrode 3 in a plan view can be made larger than the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the shielding electrode 61 in a plan view.

[0192] It can also be used Figure 7 The specific example shown. Figure 7 In the specific example, the insulating portion 62 has a film shape. In this specific example, from the semiconductor substrate 1 toward the photoelectric conversion layer 4, the pixel via 13, the pixel electrode 3, the via 68 and the pixel electrode 69 are connected in the order of the pixel via 13, the pixel electrode 3, the via 68 and the pixel electrode 69. Therefore, they are electrically connected. The signal charge reaching the pixel electrode 69 flows in the order of the via 68, the pixel electrode 3 and the pixel via 13.

[0193] exist Figure 7 In the specific example shown, the insulating portion 62 surrounds the pixel electrode 69 in a plan view. The upper surface of the insulating portion 62 is flush with the upper surface of the pixel electrode 69. The insulating portion 62 also exists between the pixel electrode 3 and the pixel electrode 69.

[0194] exist Figure 7 In the specific example shown, the upper surface of the shield electrode 61 is covered with the insulating portion 62 . The upper surface of the pixel electrode 3 is also covered with the insulating portion 62 .

[0195] like Figure 7 Providing the via 68 and the pixel electrode 69 as in the specific example is advantageous from the viewpoint of making the lower surface of the photoelectric conversion layer 4 flat and providing the insulating portion 62 between the shielding electrode 61 and the photoelectric conversion layer 4. Therefore, this configuration is advantageous from the viewpoint of suppressing the generation of cracks in the photoelectric conversion layer 4. In particular, when the insulating portion 62 is thick, a large step difference caused by the insulating portion 62 may be generated on the insulating portion 62 or on the pixel electrode 69. In this case, since the photoelectric conversion layer 4 is formed on an uneven surface, cracks are likely to be generated in the photoelectric conversion layer 4. Therefore, in this case, by using Figure 7 The structure can exert crack suppression effect. Figure 7 In the specific example of , the thickness of the film shape of the insulating portion 62 refers to the thickness of a portion of the insulating portion 62 that overlaps with the shield electrode 61 in a plan view. The above-mentioned measurement point is set in this portion.

[0196] exist Figure 7 In the example of FIG. 1 , an insulator 67 is provided between the pixel electrode 3 and the shielding electrode 61. The material of the insulator 67 may be the same as or different from the material of the insulating portion 62. The insulator 67 may be an insulator of the insulating layer 2. Figure 4B , Figure 4C and Figure 5B In the embodiment shown in FIG. 6 , although not shown in the figure, the insulating layer 2 as an insulator is also located between the pixel electrode 3 and the shielding electrode 61 .

[0197] (Shielding Structure Using Vias Connected to Shielding Electrode 61)

[0198] In the stacked imaging device 100, a charge accumulation region is provided separately from the photoelectric conversion layer 4. The accumulation region is provided in the portion of the detection circuit 12 inside the semiconductor substrate 1. The charges generated in the photoelectric conversion layer 4 are transferred from the pixel electrode 3 through the pixel via 13 to the accumulation region.

[0199] In the stacked imaging device 100, parasitic capacitance may occur between a pixel via 13 connected to a certain pixel electrode 3 and a pixel via 13 connected to a pixel electrode 3 adjacent to the pixel electrode 3. The parasitic capacitance may cause crosstalk between pixels.

[0200] In order to suppress the crosstalk caused by parasitic capacitance, it is conceivable to connect the via hole to the shielding electrode 61 and use the via hole to shield the pixel via holes 13. In this way, the parasitic capacitance between the pixel via holes 13 can be reduced, so the crosstalk caused by the parasitic capacitance can be suppressed.

[0201] As described above, the imaging device 100 includes a plurality of wiring layers. The plurality of wiring layers are arranged between the shielding electrode and the semiconductor substrate 1. The plurality of wiring layers are located at different positions in a direction perpendicular to the surface of the semiconductor substrate 1. The first wiring layer 14 is the layer closest to the pixel electrode 3 among the plurality of wiring layers. In a region located closer to the side of the semiconductor substrate 1 than the first wiring layer 14, more wiring that can function as a shield to suppress crosstalk is arranged than in a region located closer to the side of the pixel electrode 3 than the first wiring layer 14. Therefore, the shielding effect based on the via connected to the shielding electrode 61 is easy to appear in a region closer to the side of the pixel electrode 3 than the first wiring layer 14. In addition, the shielding effect based on the via connected to the shielding electrode 61 is easy to appear when the interval between the pixel electrode 3 and the first wiring layer 14 is large.

[0202] In one example, the camera device 100 is a color image sensor. In one example of a color image sensor, pixels corresponding to RGB are arranged adjacent to each other. That is, pixels corresponding to different colors are arranged adjacent to each other. Therefore, if crosstalk between pixels occurs, color mixing occurs. By applying a shielding structure to the color image sensor, crosstalk is suppressed, and the degradation of image quality caused by color mixing is suppressed.

[0203] Hereinafter, a technique of using a via hole connected to the shield electrode 61 will be described. Hereinafter, a via hole extending from the shield electrode 61 may be referred to as a shield via hole.

[0204] In this embodiment, according to Figures 1 to 7It can be understood that the shielding vias 63 and 63C are connected to the shielding electrode 61. The shielding vias 63 and 63C extend from the shielding electrode 61 toward the semiconductor substrate 1. Specifically, the shielding vias 63 and 63C extend from the shielding electrode 61 to the first wiring layer 14.

[0205] A via hole electrically connected to the shield electrode 61 may be present on the semiconductor substrate 1 side relative to the first wiring layer 14 .

[0206] exist Figure 3 In the example of FIG. 1 , each pixel electrode 3 is surrounded by a frame-shaped portion included in the shielding electrode 61 in a plan view. The shielding vias 63C connected to the shielding electrode 61 are arranged at the four corners of the frame-shaped portion. Furthermore, the shielding vias 63 are also arranged between the four corners. Figure 3 In FIG. 1 , the shield vias 63C at the four corners of the frame-shaped portion surrounding the pixel electrode 3 located at the center of the figure are given reference numerals 63C.

[0207] It is also possible to make the number of shielding vias 63 and 63C smaller than Figure 3 The more shielding vias 63, 63C that surround one pixel electrode 3 in a plan view, the greater the effect of reducing crosstalk. A large number of shielding vias 63, 63C may be provided, and adjacent shielding vias 63, 63C may be connected to each other. A collection of a plurality of shielding vias 63, 63C provided in this way may also be referred to as a line via.

[0208] As described above, by connecting the shield vias 63 and 63C to the shield electrode 61 and extending the shield vias 63 and 63C toward the semiconductor substrate 1 , crosstalk between the pixels 20 can be suppressed.

[0209] When the imaging device 100 is a color image sensor, color mixture can be suppressed by suppressing crosstalk as described above.

[0210] As the material of the shield vias 63 and 63C, conductive materials such as copper (Cu), tungsten (W), and cobalt (Co) are exemplified.

[0211] The shield vias 63 and 63C can be formed by being buried in the insulating layer 2 .

[0212] A plurality of shielding vias 63 and 63C may be formed in the same manufacturing process as the pixel via 13 .

[0213] Instead of providing the insulating portion 62 between the shield electrode 61 and the photoelectric conversion layer 4 , a shield structure using a shield via connected to the shield electrode 61 may be provided.

[0214] Below, refer to Figure 8 , shielding based on shielded vias is further explained.

[0215] In the following, shielding vias are sometimes described by assigning ordinal numbers. Figure 8 , the position of the first shielding via as the shielding via 63 is represented by point P1. The position of the second shielding via as the shielding via 63 is represented by point P2. The position of the third shielding via as the shielding via 63 is represented by point P3. The position of the fourth shielding via as the shielding via 63 is represented by point P4. The position of the fifth shielding via as the shielding via 63C is represented by point P5. The position of the sixth shielding via as the shielding via 63C is represented by point P6. The position of the seventh shielding via as the shielding via 63C is represented by point P7. The position of the eighth shielding via as the shielding via 63C is represented by point P8. The position of the ninth shielding via as the shielding via 63 is represented by point P9. The position of the tenth shielding via as the shielding via 63 is represented by point P10. The position of the eleventh shielding via as the shielding via 63 is represented by point P11. The position of the twelfth shielding via as the shielding via 63 is represented by point P12. The position of the 13th shield via, which is the shield via 63, is represented by a point P13. The position of the 14th shield via, which is the shield via 63, is represented by a point P14.

[0216] In the following, the terms "part 1 X1", "part 2 X2", "part 3 X3", "part 4 X4", "part 5 X5", "part 6 X6", "part 7 X7" and "part 8 X8" may be used. Figure 8 In the example above, shadows are added to these parts. Figure 8 The insulating layer 2 is omitted in the figure.

[0217] Hereinafter, the term “planar view” may be used. Planar view refers to, for example, observation along a direction perpendicular to the surface of the semiconductor substrate 1 .

[0218] exist Figure 8 In the example, the plurality of pixel electrodes 3 include a first pixel electrode 3A, a first adjacent pixel electrode 3B1, a second adjacent pixel electrode 3B2, a third adjacent pixel electrode 3B3, and a fourth adjacent pixel electrode 3B4. The first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 are adjacent to the first pixel electrode 3A.

[0219] In addition, Figure 8In the example of , the plurality of pixel electrodes 3 include a first specific pixel electrode 3C1, a second specific pixel electrode 3C2, a third specific pixel electrode 3C3, and a fourth specific pixel electrode 3C4. The first specific pixel electrode 3C1 is adjacent to the first adjacent pixel electrode 3B1 and the second adjacent pixel electrode 3B2. The second specific pixel electrode 3C2 is adjacent to the second adjacent pixel electrode 3B2 and the third adjacent pixel electrode 3B3. The third specific pixel electrode 3C3 is adjacent to the third adjacent pixel electrode 3B3 and the fourth adjacent pixel electrode 3B4. The fourth specific pixel electrode 3C4 is adjacent to the fourth adjacent pixel electrode 3B4 and the first adjacent pixel electrode 3B1.

[0220] The shielding electrode 61 includes a first portion X1, a second portion X2, a third portion X3, and a fourth portion X4. The at least one shielding via includes a first shielding via, a second shielding via, a third shielding via, and a fourth shielding via. The first shielding via extends from the first portion X1 toward the semiconductor substrate 1. The second shielding via extends from the second portion X2 toward the semiconductor substrate 1. The third shielding via extends from the third portion X3 toward the semiconductor substrate 1. The fourth shielding via extends from the fourth portion X4 toward the semiconductor substrate 1.

[0221] In a plan view, the first pixel electrode 3A is a quadrilateral Q formed by connecting the first side S1, the second side S2, the third side S3 and the fourth side S4 in the order of the first side S1, the second side S2, the third side S3 and the fourth side S4. In a plan view, the first portion X1 is located between the first side S1 and the first adjacent pixel electrode 3B1. In a plan view, the second portion X2 is located between the second side S2 and the second adjacent pixel electrode 3B2. In a plan view, the third portion X3 is located between the third side S3 and the third adjacent pixel electrode 3B3. In a plan view, the fourth portion X4 is located between the fourth side S4 and the fourth adjacent pixel electrode 3B4.

[0222] exist Figure 8 In the example, specifically, in the plan view, the first side S1 is opposite to the first adjacent pixel electrode 3B1 via the first portion X1. In the plan view, the second side S2 is opposite to the second adjacent pixel electrode 3B2 via the second portion X2. In the plan view, the third side S3 is opposite to the third adjacent pixel electrode 3B3 via the third portion X3. In the plan view, the fourth side S4 is opposite to the fourth adjacent pixel electrode 3B4 via the fourth portion X4.

[0223] exist Figure 8In the example of , the shielding electrode 61 includes a fifth portion X5, a sixth portion X6, a seventh portion X7, and an eighth portion X8. At least one shielding via includes a fifth shielding via, a sixth shielding via, a seventh shielding via, and an eighth shielding via. The fifth shielding via extends from the fifth portion X5 toward the semiconductor substrate 1. The sixth shielding via extends from the sixth portion X6 toward the semiconductor substrate 1. The seventh shielding via extends from the seventh portion X7 toward the semiconductor substrate 1. The eighth shielding via extends from the eighth portion X8 toward the semiconductor substrate 1.

[0224] In a plan view, the plurality of pixel electrodes 3 are separated from each other via a grid-shaped region 60 including a plurality of intersections. In a plan view, the shielding electrode 61 is located in the grid-shaped region 60 .

[0225] In a plan view, the quadrilateral Q includes a first vertex V1, a second vertex V2, a third vertex V3, and a fourth vertex V4. The first vertex V1 is a vertex where the first side S1 and the second side S2 are connected. The second vertex V2 is a vertex where the second side S2 and the third side S3 are connected. The third vertex V3 is a vertex where the third side S3 and the fourth side S4 are connected. The fourth vertex V4 is a vertex where the fourth side S4 and the first side S1 are connected.

[0226] In a plan view, the plurality of intersections include a first intersection Y1, a second intersection Y2, a third intersection Y3, and a fourth intersection Y4. In a plan view, the first intersection Y1 is closest to the first vertex V1 among the plurality of intersections. In a plan view, the second intersection Y2 is closest to the second vertex V2 among the plurality of intersections. The third intersection Y3 is closest to the third vertex V3 among the plurality of intersections. The fourth intersection Y4 is closest to the fourth vertex V4 among the plurality of intersections.

[0227] The fifth portion X5 is located at the first intersection Y1 in plan view. The sixth portion X6 is located at the second intersection Y2 in plan view. The seventh portion X7 is located at the third intersection Y3 in plan view. The eighth portion X8 is located at the fourth intersection Y4 in plan view.

[0228] Furthermore, in Figure 8 In the example of , the at least one shielding via includes a 9th shielding via, a 10th shielding via, an 11th shielding via, a 12th shielding via, a 13th shielding via, and a 14th shielding via. The 9th shielding via and the 10th shielding via extend from the 1st portion X1 toward the semiconductor substrate 1. The 11th shielding via extends from the 2nd portion X2 toward the semiconductor substrate 1. The 12th shielding via and the 13th shielding via extend from the 3rd portion X3 toward the semiconductor substrate 1. The 14th shielding via extends from the 4th portion X4 toward the semiconductor substrate 1.

[0229] The vias connected to the shielding electrode 61 help to obtain a high-resolution image. Specifically, if the first to fourteenth shielding vias are set in this way, the number of shielding vias 63 and 63C surrounding one pixel electrode 3 in a plan view is large, and the effect of reducing crosstalk becomes greater. In addition, the crosstalk between pixels arranged in an oblique direction can also be reduced. Therefore, it is easy to obtain an image with a higher resolution. In addition, the oblique direction is Figure 8 In the example, it is the direction in which the diagonal of quadrilateral Q extends in the plane view.

[0230] Part of the shield vias 63 and 63C connected to the shield electrode 61 described above may be omitted. Shield vias 63 and 63C extending from the shield electrode 61 toward the semiconductor substrate 1 may be added.

[0231] exist Figure 8 In the example of FIG. 1 , the imaging device 100 includes a pixel via 13. The pixel via 13 is connected to the first pixel electrode 3A. The pixel via 13 extends from the first pixel electrode 3A toward the semiconductor substrate 1. Figure 8 In FIG. 1 , the position of the pixel via hole 13 is represented by a point PA. Figure 8 In the example, the pixel vias 13 extend toward the semiconductor substrate 1 not only from the pixel electrode 3A in the center of the figure but also from the other eight pixel electrodes 3B1 to 3B4 and 3C1 to 3C4.

[0232] In such an imaging device 100, the overlap of the signal charge flowing into the pixel via 13 connected to the first pixel electrode 3A due to the noise caused by the parasitic capacitance between the pixel via 13 connected to the first pixel electrode 3A and the pixel via connected to the adjacent pixel electrode can be suppressed by the shielding vias 63 and 63C connected to the shielding electrode 61. Therefore, such an imaging device 100 is suitable for obtaining a high-resolution image.

[0233] In a specific example, in a plan view, the pixel via 13 connected to the first pixel electrode 3A is surrounded by the first shield via, the second shield via, the third shield via, the fourth shield via, and the fifth shield via.

[0234] Specifically, in a plan view, the pixel via 13 connected to the first pixel electrode 3A is surrounded by the first shielding via, the second shielding via, the third shielding via, the fourth shielding via, the fifth shielding via, the sixth shielding via, the seventh shielding via, and the eighth shielding via.

[0235] More specifically, in a plan view, the pixel via 13 connected to the first pixel electrode 3A is surrounded by a first shielding via, a second shielding via, a third shielding via, a fourth shielding via, a fifth shielding via, a sixth shielding via, a seventh shielding via, an eighth shielding via, a ninth shielding via, a tenth shielding via, an eleventh shielding via, a twelfth shielding via, a thirteenth shielding via and a fourteenth shielding via.

[0236] exist Figure 8 In the example of FIG. 1 , the at least one shield via extends from the shield electrode 61 to the first wiring layer 14. This is suitable for obtaining a high-resolution image.

[0237] exist Figure 8 In the example, quadrilateral Q is a rectangle. Quadrilateral Q can also be a square.

[0238] exist Figure 8 In the example of , in a plan view, the first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 are quadrilaterals. Typically, in a plan view, the first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 have the same shape and size as the quadrilateral Q.

[0239] exist Figure 8 In the example of FIG. 1 , in a plan view, the first adjacent pixel electrode 3B1 and the third adjacent pixel electrode 3B3 are adjacent to the first pixel electrode 3A in the direction in which the second side S2 and the fourth side S4 extend. The second adjacent pixel electrode 3B2 and the fourth adjacent pixel electrode 3B4 are adjacent to the first pixel electrode 3A in the direction in which the first side S1 and the third side S3 extend.

[0240] exist Figure 8 In the example of FIG. 1 , the shielding electrode 61 as a single conductor shields the plurality of pixel electrodes 3. Specifically, the single conductor has a lattice shape in a plan view. However, other methods may be used. For example, the shielding electrode 61 may be electrically separated into a plurality of parts, and the plurality of parts may respectively shield the pixel electrodes 3 corresponding to each other.

[0241] Below, refer to 9A to 9E , describing the features of the camera device. The following description may overlap with the above description. The following description may also be combined with the above description. The terms in the following description may also be interpreted interchangeably with the terms in the above description. 9A to 9E In the figure, the insulating layer 2 is omitted.

[0242] Fig.9A The first shielding via SV1 corresponds to Figure 8The first shielding via at point P1. Fig.9A The second shielding via SV2 corresponds to Figure 8 The second shielding via at point P2. Fig.9A The third shielding via SV3 corresponds to Figure 8 The 5th shielding via at point P5. Fig.9A The fourth shielding via SV4 corresponds to Figure 8 The third shielding via at point P3. Fig.9A The fifth shielding via SV5 corresponds to Figure 8 The 6th shielding via at point P6. Fig.9A The sixth shielding via SV6 corresponds to Figure 8 The 4th shielding via at point P4. Fig.9A The seventh shielding via SV7 corresponds to Figure 8 The 7th shielding via at point P7. Fig.9A The eighth shielding via SV8 corresponds to Figure 8 The 8th shielding via at point P8. Fig.9A The ninth shielding via SV9 corresponds to Figure 8 The 9th shielding via at point P9. Fig.9A The 10th shielding via SV10 corresponds to Figure 8 The 10th shielding via at point P10. Fig.9A The 11th shielding via SV11 corresponds to Figure 8 The 11th shielding via at point P11. Fig.9A The 12th shielding via SV12 corresponds to Figure 8 The 12th shielding via at point P12. Fig.9A The 13th shielding via SV13 corresponds to Figure 8 The 13th shielding via at point P13. Fig.9A The 14th shielding via SV14 corresponds to Figure 8 The 14th shielding via at point P14.

[0243] The shielding vias SV1 to SV14 extend from the shielding electrode 61. Specifically, the shielding vias SV1 to SV14 extend from the shielding electrode 61 in a direction away from the incident surface of light. It can also be said that the shielding vias SV1 to SV14 extend downward from the shielding electrode 61. In this example, the shielding vias SV1 to SV14 extend to the first wiring layer 14.

[0244] Fig.9A The first pixel electrode PE1 corresponds to Figure 8 The first pixel electrode 3A. Fig.9A The second pixel electrode PE2 corresponds to Figure 8 The first adjacent pixel electrode 3B1. Fig.9AThe third pixel electrode PE3 corresponds to Figure 8 The second adjacent pixel electrode 3B2. Fig.9A The fourth pixel electrode PE4 corresponds to Figure 8 The first specific pixel electrode 3C1. Fig.9A The fifth pixel electrode PE5 corresponds to Figure 8 The third adjacent pixel electrode 3B3. Fig.9A The sixth pixel electrode PE6 corresponds to Figure 8 The second specific pixel electrode 3C2. Fig.9A The seventh pixel electrode PE7 corresponds to Figure 8 The 4th adjacent pixel electrode 3B4. Fig.9A The eighth pixel electrode PE8 corresponds to Figure 8 The third specific pixel electrode 3C3. Fig.9A The ninth pixel electrode PE9 corresponds to Figure 8 The first pixel electrode PE1 to the ninth pixel electrode PE9 collect charges. The first pixel electrode PE1 to the ninth pixel electrode PE9 are electrically separated from the shielding electrode 61.

[0245] The first pixel electrode PE1 is adjacent to the second pixel electrode PE2, the third pixel electrode PE3, the fifth pixel electrode PE5 and the seventh pixel electrode PE7. The fourth pixel electrode PE4 is adjacent to the second pixel electrode PE2 and the third pixel electrode PE3. The sixth pixel electrode PE6 is adjacent to the third pixel electrode PE3 and the fifth pixel electrode PE5. The eighth pixel electrode PE8 is adjacent to the fifth pixel electrode PE5 and the seventh pixel electrode PE7. The ninth pixel electrode PE9 is adjacent to the seventh pixel electrode PE7 and the second pixel electrode PE2.

[0246] Specifically, the first pixel electrode PE1 and the second pixel electrode PE2 are adjacent in the first direction. The first pixel electrode PE1 and the third pixel electrode PE3 are adjacent in the second direction. The first pixel electrode PE1 and the fifth pixel electrode PE5 are adjacent in the first direction. The first pixel electrode PE1 and the seventh pixel electrode PE7 are adjacent in the second direction. The fourth pixel electrode PE4 and the second pixel electrode PE2 are adjacent in the second direction. The fourth pixel electrode PE4 and the third pixel electrode PE3 are adjacent in the first direction. The sixth pixel electrode PE6 and the third pixel electrode PE3 are adjacent in the first direction. The sixth pixel electrode PE6 and the fifth pixel electrode PE5 are adjacent in the second direction. The eighth pixel electrode PE8 and the fifth pixel electrode PE5 are adjacent in the second direction. The eighth pixel electrode PE8 and the seventh pixel electrode PE7 are adjacent in the first direction. The ninth pixel electrode PE9 and the seventh pixel electrode PE7 are adjacent in the first direction. The ninth pixel electrode PE9 and the second pixel electrode PE2 are adjacent in the second direction.

[0247] Here, the first direction and the second direction are different directions. In the example shown in the figure, the first direction and the second direction are directions orthogonal to each other. In the example shown in the figure, the first direction is the row direction. The second direction is the column direction. In addition, in the example shown in the figure, the first direction corresponds to the X-axis direction. The second direction corresponds to the Y-axis direction.

[0248] For the expression that the first pixel electrode PE1 is adjacent to the second pixel electrode PE2, refer to Fig. 9B and Fig. 9C To be explained. This expression means that, in a plane view, the side Sj of the smallest rectangle RT1 accommodating the first pixel electrode PE1 and the side Sk of the smallest rectangle RT2 accommodating the second pixel electrode PE2 are opposite to each other. Rectangle is a concept that includes a square. Specifically, the first pixel electrode PE1 and the second pixel electrode PE2 being adjacent means that, in a plane view, the normal of the side Sj passes through the side Sk, and the normal of the side Sk passes through the side Sj. The normal of the side Sj can be a line passing through any point in the side Sj. The normal of the side Sk can be a line passing through any point in the side Sk. In a specific example, in a plane view, the perpendicular bisector of the side Sj passes through the midpoint of the side Sk, and the perpendicular bisector of the side Sk passes through the midpoint of the side Sj. The same is true for the expressions and specific examples related to the adjacency between other pixel electrodes, such as the first pixel electrode PE1 and the third pixel electrode PE3 being adjacent.

[0249] exist Figure 3 , Figure 8 , Fig.9A and Fig. 9B In the example shown, the smallest rectangle RT1 accommodating the first pixel electrode PE1 is identical to the outline of the first pixel electrode PE1 in a plan view. The same is true for other pixel electrodes such as the second pixel electrode PE2.

[0250] However, if Fig. 9C As shown in FIG. 1 , in a plan view, the contour of the first pixel electrode PE1 may also be rounded. Fig. 9C In the example of FIG. 1 , the smallest rectangle RT1 accommodating the first pixel electrode PE1 has a different outline from the first pixel electrode PE1. The second pixel electrode PE2 and other pixel electrodes may also have Fig. 9C In reality, when the size of the pixel electrode is small, the pixel electrode tends to have rounded corners in a plan view.

[0251] exist Figure 3 , Figure 8 and Fig.9AIn the example shown, a plurality of pixels are arranged in a matrix to form a pixel array. When a pixel array is formed in this way, a pixel electrode being adjacent to another pixel electrode means that the pixel electrodes are adjacent in the row direction or the column direction, rather than that the pixels are arranged in a direction inclined relative to the row direction and the column direction. Figure 3 , Figure 8 and Fig.9A In the example shown, the row direction corresponds to the left-right direction, and the column direction corresponds to the up-down direction.

[0252] return Fig.9A , a first pixel via hole PV1 extends from the first pixel electrode PE1. Fig.9A The first pixel via PV1 corresponds to Figure 8 A pixel via 13 is provided at a point PA of 1. The second pixel via PV2 extends from the second pixel electrode PE2. The third pixel via PV3 extends from the third pixel electrode PE3. The fourth pixel via PV4 extends from the fourth pixel electrode PE4. The fifth pixel via PV5 extends from the fifth pixel electrode PE5. The sixth pixel via PV6 extends from the sixth pixel electrode PE6. The seventh pixel via PV7 extends from the seventh pixel electrode PE7. The eighth pixel via PV8 extends from the eighth pixel electrode PE8. The ninth pixel via PV9 extends from the ninth pixel electrode PE9. The first pixel via PV1 to the ninth pixel via PV9 can electrically connect the first pixel electrode PE1 to the ninth pixel electrode PE9 to other elements. Specific examples of other elements are wiring layers, detection circuits 12, etc.

[0253] In a plan view, the first shielding via SV1 is located between the first pixel electrode PE1 and the second pixel electrode PE2. In a plan view, the second shielding via SV2 is located between the first pixel electrode PE1 and the third pixel electrode PE3. In a plan view, the fourth shielding via SV4 is located between the first pixel electrode PE1 and the fifth pixel electrode PE5. In a plan view, the sixth shielding via SV6 is located between the first pixel electrode PE1 and the seventh pixel electrode PE7. In a plan view, the ninth shielding via SV9 is located between the first pixel electrode PE1 and the second pixel electrode PE2. In a plan view, the tenth shielding via SV10 is located between the first pixel electrode PE1 and the second pixel electrode PE2. In a plan view, the eleventh shielding via SV11 is located between the first pixel electrode PE1 and the third pixel electrode PE3. In a plan view, the twelfth shielding via SV12 is located between the first pixel electrode PE1 and the fifth pixel electrode PE5. In plan view, the 13th shielding via SV13 is located between the 1st pixel electrode PE1 and the 5th pixel electrode PE5. In plan view, the 14th shielding via SV14 is located between the 1st pixel electrode PE1 and the 7th pixel electrode PE7. The presence of a shielding via between two pixel electrodes in plan view is suitable for obtaining a high-resolution image.

[0254] The first shielding via SV1 is located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view, which means that in a plan view, the first shielding via SV1 exists on a line segment having any point in the above-mentioned side Sj as one end and any point in the above-mentioned side Sk as the other end. In a specific example, in a plan view, the connection portion between the shielding electrode 61 and the first shielding via SV1 exists on the above-mentioned line segment. The same is true for the representation and specific examples related to the configuration of the shielding vias between other two adjacent pixel electrodes, such as the second shielding via SV2 being located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view. By having the shielding via located between two adjacent pixel electrodes in a plan view, the shielding via can shield at least a portion of the electric lines between the pixel electrodes.

[0255] In the illustrated example, the number of shielding vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in plan view is different from the number of shielding vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in plan view. The number of shielding vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in plan view is different from the number of shielding vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in plan view. The number of shielding vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in plan view is different from the number of shielding vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in plan view. The number of shielding vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in plan view is different from the number of shielding vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in plan view.

[0256] In the example shown in the figure, the number of shielding vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view is the same as the number of shielding vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view. The number of shielding vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view is the same as the number of shielding vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in a plan view.

[0257] Specifically, the shielding vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view are the first shielding via SV1, the ninth shielding via SV9, and the tenth shielding via SV10. The shielding vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view are the second shielding via SV2 and the eleventh shielding via SV11. The shielding vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view are the fourth shielding via SV4, the twelfth shielding via SV12, and the thirteenth shielding via SV13. The shielding vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in a plan view are the sixth shielding via SV6 and the fourteenth shielding via SV14.

[0258] In the example shown in the figure, in a plan view, the third shielding via SV3 is located between the first pixel electrode PE1 and the fourth pixel electrode PE4. In a plan view, the fifth shielding via SV5 is located between the first pixel electrode PE1 and the sixth pixel electrode PE6. In a plan view, the seventh shielding via SV7 is located between the first pixel electrode PE1 and the eighth pixel electrode PE8. In a plan view, the eighth shielding via SV8 is located between the first pixel electrode PE1 and the ninth pixel electrode PE9. If this is done, crosstalk between pixels arranged in an oblique direction can also be reduced. Therefore, it is easy to obtain an image with a higher resolution. In addition, in Fig.9A In the example of FIG. 1 , the outline of the first pixel electrode PE1 is a quadrilateral in a plan view, and the inclination direction is the direction in which the diagonal line of the quadrilateral extends.

[0259] Regarding the expression that the third shield via hole SV3 is located between the first pixel electrode PE1 and the fourth pixel electrode PE4 in a plan view, refer to Fig.9D For explanation. This expression means that, in a plan view, the third shielding via SV3 is located within a square Sx2 having as a diagonal a line segment connecting two opposite vertices, namely, the vertex of the smallest rectangle RT1 accommodating the first pixel electrode PE1 and the vertex of the smallest rectangle RT4 accommodating the fourth pixel electrode PE4. The two opposite vertices are selected in such a way that the square Sx2 becomes the smallest. In a specific example, in a plan view, the connection portion between the shielding electrode 61 and the third shielding via SV3 exists within the square Sx2. The same is true for the expression and specific examples related to the configuration of the shielding vias between other two pixel electrodes, such as the fifth shielding via SV5 being located between the first pixel electrode PE1 and the sixth pixel electrode PE6 in a plan view. By locating the shielding via between the two pixel electrodes in a plan view, the shielding via can shield at least a portion of the electric lines between the two pixel electrodes.

[0260] In the illustrated example, in a plan view, the third shielding via SV3 is located between the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4. In a plan view, the fifth shielding via SV5 is located between the first pixel electrode PE1, the third pixel electrode PE3, the fifth pixel electrode PE5 and the sixth pixel electrode PE6. In a plan view, the seventh shielding via SV7 is located between the first pixel electrode PE1, the fifth pixel electrode PE5, the seventh pixel electrode PE7 and the eighth pixel electrode PE8. In a plan view, the eighth shielding via SV8 is located between the first pixel electrode PE1, the seventh pixel electrode PE7, the second pixel electrode PE2 and the ninth pixel electrode PE9. Such a via existing between four pixel electrodes in a plan view is suitable for obtaining an image with high resolution.

[0261] Regarding the expression that the third shield via hole SV3 is located between the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 in a plan view, refer to Fig.9E This expression means that, in a plan view, the third shielding via SV3 is located within a quadrilateral Sx4 defined by four opposite vertices, namely, the vertex of the smallest rectangle RT1 accommodating the first pixel electrode PE1, the vertex of the smallest rectangle RT2 accommodating the second pixel electrode PE2, the vertex of the smallest rectangle RT3 accommodating the third pixel electrode PE3, and the vertex of the smallest rectangle RT4 accommodating the fourth pixel electrode PE4. The four opposite vertices are selected in such a way that the quadrilateral Sx4 becomes the smallest. In a specific example, in a plan view, the connection portion between the shielding electrode 61 and the third shielding via SV3 exists within the quadrilateral Sx4. The same is true for the expression and specific examples related to the configuration of the shielding vias between the other four pixel electrodes, such as the fifth shielding via SV5 being located between the first pixel electrode PE1, the third pixel electrode PE3, the fourth pixel electrode PE5, and the sixth pixel electrode PE6 in a plan view. Since the shielding via is located between the four pixel electrodes in a plan view, the shielding via can shield at least a portion of the electric field lines between the four pixel electrodes.

[0262] Fig.9E The quadrilateral Sx4 can correspond to Fig.9D The square Sx2. Fig.9D The square Sx2 and Fig.9E The quadrilateral Sx4 can correspond to Figure 8 The first intersection Y1. Use Fig.9D The above instructions and use Fig.9E The above description is carried out in the image Fig. 9C This can also be achieved when the pixel electrode has rounded corners in a planar view.

[0263] return Fig.9A , in a plan view, the 1st shielding via SV1 is located between the 1st pixel via PV1 and the 2nd pixel via PV2. In a plan view, the 3rd shielding via SV3 is located between the 1st pixel via PV1 and the 4th pixel via PV4. In a plan view, the 4th shielding via SV4 is located between the 1st pixel via PV1 and the 5th pixel via PV5. In a plan view, the 5th shielding via SV5 is located between the 1st pixel via PV1 and the 6th pixel via PV6. In a plan view, the 7th shielding via SV7 is located between the 1st pixel via PV1 and the 8th pixel via PV8. In a plan view, the 8th shielding via SV8 is located between the 1st pixel via PV1 and the 9th pixel via PV9.

[0264] The first shielding via SV1 is located between the first pixel via PV1 and the second pixel via PV2 in a plan view, which means that in a plan view, the first shielding via SV1 exists on a line segment having the first pixel via PV1 as one end and the second pixel via PV2 as the other end. In a specific example, in a plan view, the connection portion between the shielding electrode 61 and the first shielding via SV1 exists on a line segment having the connection portion between the first pixel electrode PE1 and the first pixel via PV1 as one end and the connection portion between the second pixel electrode PE2 and the second pixel via PV2 as the other end. The same is true for the representation and specific examples related to the configuration of vias between other pixel vias, such as the third shielding via SV3 being located between the first pixel via PV1 and the fourth pixel via PV4 in a plan view. By configuring shielding vias between pixel vias in a plan view, the shielding vias can shield at least a portion of the electric lines between the pixel vias.

[0265] Although in Fig.9A Although omitted from the illustration, in a plan view, the insulating portion 62 is separated from the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the fourth pixel electrode PE4, the fifth pixel electrode PE5, the sixth pixel electrode PE6, the seventh pixel electrode PE7, the eighth pixel electrode PE8 and the ninth pixel electrode PE9.

[0266] In a plan view, the shielding electrode 61 extends between the first pixel electrode PE1 and the second pixel electrode PE2. In a plan view, the shielding electrode 61 extends between the first pixel electrode PE1 and the third pixel electrode PE3. In a plan view, the shielding electrode 61 extends between the first pixel electrode PE1 and the fifth pixel electrode PE5. In a plan view, the shielding electrode 61 extends between the first pixel electrode PE1 and the seventh pixel electrode PE7. In a plan view, the shielding electrode 61 extends between the fourth pixel electrode PE4 and the second pixel electrode PE2. In a plan view, the shielding electrode 61 extends between the fourth pixel electrode PE4 and the third pixel electrode PE3. In a plan view, the shielding electrode 61 extends between the sixth pixel electrode PE6 and the third pixel electrode PE3. In a plan view, the shielding electrode 61 extends between the sixth pixel electrode PE6 and the fifth pixel electrode PE5. In a plan view, the shielding electrode 61 extends between the eighth pixel electrode PE8 and the fifth pixel electrode PE5. In plan view, the shielding electrode 61 extends between the eighth pixel electrode PE8 and the seventh pixel electrode PE7. In plan view, the shielding electrode 61 extends between the ninth pixel electrode PE9 and the seventh pixel electrode PE7. In plan view, the shielding electrode 61 extends between the ninth pixel electrode PE9 and the second pixel electrode PE2.

[0267] (Camera System)

[0268] In the following, a camera system to which the above-described imaging device 100 is applied will be described with reference to Fig.10 Provide explanation.

[0269] exist Fig.10 In the example of , the camera system 604 includes the imaging device 100 , an optical system 601 , a camera signal processing unit 602 , and a system controller 603 .

[0270] The optical system 601 collects light and includes, for example, a lens.

[0271] The camera signal processing unit 602 performs signal processing on the data captured by the imaging device 100 and outputs the data as an image or data.

[0272] The system controller 603 controls the imaging device 100 and the camera signal processing section 602 .

[0273] Industrial Applicability

[0274] The imaging device according to the present disclosure can be used in various camera systems and sensor systems such as digital cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras.

[0275] The imaging device of the present disclosure is described above based on the embodiments, but the imaging device and the manufacturing method thereof involved in the present disclosure are not limited to the above embodiments. Other embodiments realized by combining any constituent elements in the above embodiments, modified examples obtained by implementing various modifications thought of by those skilled in the art to the above embodiments without departing from the main purpose of the present disclosure, and various devices in which the solid-state imaging device of the present disclosure is built-in are all included in the present disclosure.

[0276] Description of reference numerals:

[0277] 1 Semiconductor substrate

[0278] 2 Insulation layer

[0279] 2a, 2b, 2c, 2d, 2e constituting layers

[0280] 3, 3A, 3B1, 3B2, 3B3, 3B4, 3C1, 3C2, 3C3, 3C4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, 69 pixel electrodes

[0281] 4 Photoelectric conversion layer

[0282] 4p protrusion

[0283] 5 Counter electrode

[0284] 6 Buffer layer

[0285] 7 Sealing layer

[0286] 8 Color Filters

[0287] 9 Planarization layer

[0288] 10 Microlens

[0289] 11 Photoelectric conversion unit

[0290] 12 Detection circuit

[0291] 13. PV1, PV2, PV3, PV4, PV5, PV6, PV7, PV8, PV9 pixel vias

[0292] 63, 63C, SV1, SV2, SV3, SV4, SV5, SV6, SV7, SV8, SV9, SV10, SV11, SV12, SV13, SV14 shielded vias

[0293] 14 1st wiring layer

[0294] 20 pixels

[0295] 30 pixels

[0296] 60 Area

[0297] 61 Shielding electrode

[0298] 62 Insulation

[0299] 62a Upper surface

[0300] 62b Lower surface

[0301] 62c Side

[0302] 62d Corner

[0303] 62x layers

[0304] 65 Signal Charge

[0305] 67 Insulator

[0306] 68 Vias

[0307] 71 Separation amplitude

[0308] 81 Mask

[0309] 100 Camera Device

[0310] 601 Optical System

[0311] 602 Camera signal processing unit

[0312] 603 System Controller

[0313] 604 Camera System

[0314] S1, S2, S3, S4 side

[0315] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, PA point

[0316] Q, Sx4 quad

[0317] Sx2 Square

[0318] RT1, RT2, RT3, RT4 Rectangular

[0319] Sk, Sj edge

[0320] V1, V2, V3, V4 vertices

[0321] X1, X2, X3, X4, X5, X6, X7, X8 parts

[0322] The intersection of Y1, Y2, Y3 and Y4.

Claims

1. A camera device comprising: A plurality of pixels arranged in row and column directions, including a first pixel and a second pixel adjacent to the first pixel along the row direction; A shielding electrode, located between the first pixel and the second pixel; as well as a first shielding via extending from the shielding electrode, The first pixel comprises: a first photoelectric conversion layer that converts incident light into electric charges; and a first pixel electrode for collecting charges generated by the first photoelectric conversion layer; The second pixel comprises: a second photoelectric conversion layer that converts incident light into electric charges; and a second pixel electrode for collecting charges generated by the second photoelectric conversion layer; The shielding electrode is electrically separated from the first pixel electrode and the second pixel electrode; The first shielding via hole is located between the first pixel electrode and the second pixel electrode in a plan view. The imaging device further includes an insulating portion located between the shielding electrode and the first photoelectric conversion layer. In the plan view, the insulating portion is separated from the first pixel electrode.

2. The imaging device according to claim 1, The plurality of pixels include a third pixel adjacent to the first pixel along a column direction, The third pixel comprises: a third photoelectric conversion layer that converts incident light into electric charges; and a third pixel electrode for collecting charges generated by the third photoelectric conversion layer; The camera device also includes: The second shielding via extends from the shielding electrode and is located between the first pixel electrode and the third pixel electrode in the plan view.

3. The imaging device according to claim 2, The plurality of pixels include a fourth pixel adjacent to the second pixel along a column direction, The fourth pixel comprises: a fourth photoelectric conversion layer that converts incident light into electric charges; and a fourth pixel electrode for collecting charges generated by the fourth photoelectric conversion layer; The camera device also includes: The third shielding via extends from the shielding electrode and is located between the first pixel electrode and the fourth pixel electrode in the plan view.

4. The imaging device according to claim 1, The camera device further comprises a fourth shielding via, The shielding electrode surrounds the plurality of pixels in a lattice shape. In a plan view, the fourth shielding vias extend from vertices of the lattice of the shielding electrodes.

5. The imaging device according to claim 1, further comprising: a first pixel via hole extending from the first pixel electrode; and The second pixel via hole extends from the second pixel electrode.

6. The imaging device according to claim 5, In the plan view, the first shielding via hole is located between the first pixel via hole and the second pixel via hole.

7. The camera device according to claim 1, The imaging device further comprises a first wiring layer. The first shield via extends from the shield electrode to the first wiring layer.

8. The imaging device according to claim 1, further comprising: The insulating portion is further located between the shield electrode and the second photoelectric conversion layer.

9. The imaging device according to claim 1, In the plan view, the insulating portion includes a portion that does not overlap with the shield electrode.

10. The camera device according to claim 1, The insulating portion has a film shape, The thickness of the film shape is 10 nm or more.

11. The imaging device according to claim 1, A surface of the first pixel electrode and a surface of the shielding electrode are located on the same plane.

12. The camera device according to claim 1, The camera device further comprises a fifth shielding via, The shielding electrode surrounds the plurality of pixels in a lattice shape. The first shield via and the fifth shield via extend from one side of the grid of the shield electrode.

13. A camera device comprising: A plurality of pixels are arranged in row and column directions, including a first pixel; a shielding electrode surrounding the plurality of pixels in a lattice shape; and a first shielding via extending from the shielding electrode, The first pixel comprises: The first photoelectric conversion layer converts incident light into electric charges; a first pixel electrode for collecting charges generated by the first photoelectric conversion layer; and an insulating portion located between the shielding electrode and the first photoelectric conversion layer, The insulating portion is separated from the first pixel electrode in a plan view.

14. The camera device according to claim 13, The insulating portion has a film shape, The thickness of the film shape is 10 nm or more.

15. The imaging device according to claim 13, further comprising: The amplifying transistor includes a gate electrode electrically connected to the first pixel electrode.

16. The imaging device according to claim 13, The insulating portion includes a portion that does not overlap with the shielding electrode in a plan view.

17. The camera device according to claim 13, An angle formed between the lower surface of the insulating portion and the side surface of the insulating portion is less than 90 degrees.

18. The imaging device according to claim 13, The shielding electrode surrounds the first pixel electrode. The four rectangular portions of the shielding electrode surrounding the first pixel electrode are located at equal intervals from the first pixel electrode.

19. The imaging device according to claim 13, The pixel electrode and the shielding electrode are spaced apart from each other by a width not less than 0.1 μm and not more than 1 μm.

20. The imaging device according to claim 13, In a plan view, the area of ​​the pixel electrode is larger than the area of ​​the shielding electrode.

21. A camera device comprising: a plurality of pixels arranged in row and column directions, including a first pixel and a second pixel adjacent to the first pixel along the row direction; and a shielding electrode, located between the first pixel and the second pixel, The first pixel comprises: The first photoelectric conversion layer converts incident light into electric charges; a first pixel electrode for collecting charges generated by the first photoelectric conversion layer; and an insulating portion located between the shielding electrode and the first photoelectric conversion layer, The angle between the lower surface of the insulating portion and the side surface of the insulating portion is less than 90 degrees, The insulating portion is separated from the first pixel electrode in a plan view.

Images