Method for controlling repair of volatile memory device and memory device

Abstract

A method for controlling repair of a volatile memory device and a storage device are provided. The method includes: repeatedly performing a patrol read operation to provide error location information of an error included in read data from the volatile memory device; generating cumulative error information by accumulating error location information based on the repeatedly performed patrol read operation; confirming an error attribute based on the cumulative error information, the error attribute indicating a correlation between the error and a structure of the volatile memory device; and performing a run-time repair operation for the volatile memory device based on the cumulative error information and the error attribute. Errors can be effectively managed to prevent failure of the volatile memory device, and thus the performance and life of the volatile memory device and the storage device can be improved.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2019-0088724 filed on July 23, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a method of controlling repair of a volatile memory device and an apparatus performing the method. Background Art

[0003] Semiconductor memory devices can be classified into non-volatile memory devices such as flash memory devices and volatile memory devices such as dynamic random access memory (DRAM) devices. The high-speed operation and cost efficiency of DRAMs provide for their effective use as system memory. Due to the continuous reduction in manufacturing design specifications for DRAMs, bit errors in DRAM memory cells can increase rapidly and the yield of DRAM devices can decrease.

[0004] Storage devices, such as solid-state drives (SSDs) based on flash memory, are widely used as large-capacity storage media for computing devices. SSDs store data in nonvolatile memory devices, such as flash memory devices, and use volatile memory devices, such as DRAM devices, as buffer memory to manage various information for controlling the flash memory devices. When a fault is found during the manufacturing process of a DRAM device, the faulty unit or failed unit can be repaired by various repair schemes. However, when a fault occurs after the DRAM device is installed in the SSD and the product is supplied to the user (i.e., after the SSD is used at the user level), in addition to the DRAM device, the SSD may not operate normally. Summary of the invention

[0005] One or more example embodiments may provide a method of controlling repair of a volatile memory device to improve reliability of the volatile memory device.

[0006] One or more example embodiments may provide a device having improved reliability and lifespan by adopting the method.According to one or more embodiments, the device is a memory device having improved reliability and lifespan by adopting the method of controlling repair of a volatile memory.

[0007] According to one aspect of the disclosure, a method for controlling repair of a volatile memory device is provided, the method comprising: repeatedly performing a patrol read operation to confirm error location information of one or more errors included in read data from the volatile memory device; obtaining cumulative error information by accumulating error location information based on the repeatedly performed patrol read operations; confirming error attribute information based on the cumulative error information, the error attribute information indicating a correlation between the one or more errors included in the read data and a structure of the volatile memory device; and performing a run-time repair operation for the volatile memory device based on the cumulative error information and the error attribute information.

[0008] According to another aspect of the disclosure, a method for controlling repair of a volatile memory device is provided, the volatile memory device being included in a storage device, the method comprising: when the storage device is in an idle mode, repeatedly performing a patrol read operation to confirm error location information of one or more errors included in read data from the volatile memory device; storing one or more candidate failed row addresses with correctable errors among all row addresses of the volatile memory device and the number of correctable errors respectively corresponding to each of the one or more candidate failed row addresses as cumulative error information in a cumulative error table by accumulating the error location information based on the repeatedly performed patrol read operations, each of the correctable error numbers indicating the number of errors in the corresponding candidate failed row address; confirming error attribute information based on the cumulative error information, the error attribute information indicating a correlation between the error and the structure of the volatile memory device; and performing a post-packaging repair operation on the volatile memory device based on the cumulative error information and the error attribute information.

[0009] According to another aspect of the disclosure, a storage device is provided, the storage device comprising: a non-volatile memory device; and a storage controller configured to control access to the non-volatile memory device, the storage controller comprising a volatile memory device and a memory controller configured to control access to the volatile memory device, wherein the memory controller or the volatile memory device comprises an error checking and correction (ECC) engine, the error checking and correction engine being configured to perform error detection and correction on access data of the volatile memory device, wherein the memory controller is configured to: repeatedly perform a patrol operation to provide error location information of one or more errors included in read data from the volatile memory device, regardless of an access read operation providing data read from the volatile memory device; obtain cumulative error information by accumulating error location information based on the repeatedly performed patrol read operations; confirm error attribute information based on the cumulative error information, the error attribute information indicating a correlation between the one or more errors included in the read data and a structure of the volatile memory device; and perform a run-time repair operation on the volatile memory device based on the cumulative error information and the error attribute information.

[0010] According to another aspect of the disclosure, a device is provided, the device comprising: a memory storing one or more instructions; and a processor configured to execute the one or more instructions to perform a first patrol read operation to read first data from a volatile memory device; confirm one or more first errors in the first data read from the volatile memory device based on the first patrol read operation; store error information corresponding to the confirmed one or more first errors; perform a second patrol read operation to read second data from the volatile memory device; confirm one or more second errors in the second data read from the volatile memory device based on the second patrol read operation; accumulate error information based on the confirmed one or more second errors; confirm error attribute information based on the accumulated error information and structural information corresponding to structural characteristics of the volatile memory device; and perform a run-time repair operation for the volatile memory device based on the accumulated error information and the error attribute information.

[0011] The method and memory device according to example embodiments may effectively manage errors to prevent failure of a volatile memory device, and thus the performance and lifespan of the volatile memory device and the memory device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The disclosed example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a flowchart illustrating a method of controlling repair of a volatile memory device according to example embodiments.

[0014] Figure 2 is a block diagram illustrating a memory system according to example embodiments.

[0015] Figure 3 Is a diagram used to describe the ECC level on a die in terms of data bits and parity bits.

[0016] Figure 4 is a block diagram illustrating a volatile memory device according to example embodiments.

[0017] Figure 5 It is shown Figure 4 A diagram of a portion of a volatile memory device.

[0018] Fig. 6A and Figure 6B is a diagram illustrating a patrol read operation of a method for controlling repair of a volatile memory device according to example embodiments.

[0019] Figure 7 is a diagram of a cumulative error table illustrating a method for controlling repair of a volatile memory device according to example embodiments.

[0020] Figure 8 is a flowchart illustrating a method of controlling repair of a volatile memory device according to example embodiments.

[0021] Fig. 9 is a block diagram illustrating a volatile memory device performing a post package repair operation according to example embodiments.

[0022] Fig.10 is a timing diagram showing signals used for post-packaging repair operations.

[0023] Fig.11 and Fig.12 is a diagram illustrating a patrol read operation of a method for controlling repair of a volatile memory device according to example embodiments.

[0024] Fig.13 is a diagram illustrating an example layout of a memory cell array included in a volatile memory device according to example embodiments.

[0025] Fig.14 and Fig.15 is a diagram for describing an example embodiment of determining an error attribute of a method for controlling repair of a volatile memory device according to example embodiments.

[0026] Fig.16is a diagram illustrating an example embodiment of a cumulative error table for a method of controlling repair of a volatile memory device according to example embodiments.

[0027] Fig.17 is a flowchart illustrating a method of controlling repair of a volatile memory device according to example embodiments.

[0028] Fig.18 is a diagram illustrating column repair via a method of controlling repair of a volatile memory device according to example embodiments.

[0029] Fig.19 is a diagram illustrating an example embodiment of a cumulative error table for a method of controlling repair of a volatile memory device according to example embodiments.

[0030] Fig. 20 It is shown that the use Fig.19 A diagram of a method for determining failed memory cells using a cumulative error table.

[0031] Fig.21 and Fig. 22 is a diagram illustrating a method of preventing a failure of a volatile memory device using accumulated error information according to example embodiments.

[0032] Fig.23 is a block diagram illustrating a storage device according to example embodiments.

[0033] Fig.24 is a flowchart illustrating a method of controlling repair of a volatile memory device included in a storage device according to example embodiments. DETAILED DESCRIPTION

[0034] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings showing one or more example embodiments. In the accompanying drawings, like reference numerals always refer to like elements. Repetitive descriptions may be omitted.

[0035] Figure 1 is a flowchart illustrating a method of controlling repair of a volatile memory device according to example embodiments.

[0036] Reference Figure 1 , repeatedly performing a patrol read operation to provide error location information of errors included in read data from the volatile memory device (S100). The patrol read operation may be performed regardless of an access read operation that provides data read from the volatile memory device to an external device. The patrol read operation may be repeatedly performed for all row addresses of the volatile memory device.

[0037] In S200, cumulative error information is generated by accumulating error position information based on repeatedly performed patrol read operations. The cumulative error information may be information reflecting a spatial history or a temporal history of a volatile memory device. According to an embodiment, the cumulative error information may be information reflecting both a spatial history and a temporal history of a volatile memory device. The cumulative error information may be stored in a cumulative error table and managed in the cumulative error table.

[0038] In S300, error attributes are determined based on the accumulated error information. According to an embodiment, the error attributes may indicate a correlation between errors and a structure of a volatile memory device. The error attributes may be determined and assigned (or associated) based on a distribution of errors according to the structure of the volatile memory device.

[0039] In S400, a runtime repair operation is performed for the volatile memory device based on the accumulated error information and the error attributes. The runtime repair operation indicates an operation of replacing an address where an error occurs with a repair address so that a correctable error occurring during normal operation of the volatile memory device may not be developed into an uncorrectable error that causes a malfunction of the volatile memory device.

[0040] Therefore, the method and memory device according to example embodiments may effectively manage errors to prevent malfunction of a volatile memory device, and thus the performance and lifespan of the volatile memory device and the memory device may be improved.

[0041] Figure 2 is a block diagram illustrating a memory system according to example embodiments.

[0042] Reference Figure 2 , the memory system 20 includes a memory controller 100 and a volatile memory device 200 .

[0043] The memory controller 100 may control the overall operation of the memory system 20, and the memory controller 100 may control the overall data exchange between the external host device and the volatile memory device 200. For example, the memory controller 100 may write data to the volatile memory device 200 or read data from the volatile memory device 200 in response to a request from the external host device. In addition, the memory controller 100 may issue an operation command for controlling the volatile memory device 200 to the volatile memory device 200.

[0044] In one or more example embodiments, the volatile memory device 200 may be a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SRAM), a low power double data rate (LPDDR) SRAM, etc. Example embodiments are not limited to a specific type of memory and may be applied to any type of memory requiring a repair operation.

[0045] The memory controller 100 transmits a clock signal CLK, a command CMD, and an address (signal) ADDR (CMD / ADDR) to the volatile memory device 200 , and exchanges data MD with the volatile memory device 200 .

[0046] The volatile memory device 200 includes a memory cell array (MCA) 300 storing data MD, an error correction code or an error check and correction (ECC) circuit 400, and a control logic circuit (or, control logic) 210. Figure 2 In the example embodiment shown in FIG. 1 , the ECC circuit 400 is included in the volatile memory device 200 , however, according to another example embodiment, the ECC circuit 400 may be included in the memory controller 100 .

[0047] The memory system 20 may communicate with an external host device through an interface protocol such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), etc.

[0048] The memory controller 100 may include a repair manager RMNG configured to perform a method of controlling repair of a volatile memory device according to an example embodiment. For example, the repair manager RMNG may be configured to perform Figure 1 That is, the repair manager RMNG may control the patrol read operation, generate cumulative error information, and determine error attributes. The runtime repair operation may be controlled by the repair manager RMNG or by an external host device. In one or more example embodiments, the repair manager RMNG may store and manage the cumulative error information in the cumulative error table (AET) 120. Figure 2 In the example embodiment shown in FIG. 1 , the accumulated error table 120 is included in the memory controller 100 , however, other example embodiments are not limited thereto.

[0049] In one or more example embodiments, the volatile memory device 200 may provide information CNFINF about the configuration of the volatile memory device 200 to the memory controller 100. In this case, the repair manager RMNG in the memory controller 100 may determine an error attribute based on the information CNFINF provided from the volatile memory device 200.

[0050] Figure 3 Is a diagram used to describe the ECC level on a die in terms of data bits and parity bits.

[0051] exist Figure 3 In the figure, SEC stands for single error correction, DED stands for double error detection, and DEC stands for double error correction. Figure 3 The parity bits and the corresponding size overhead of the parity bits (parity O / H) are shown. The parity bits correspond to Hamming codes or extended Hamming codes. The size overhead of the parity bits corresponds to the ratio of the parity bits of the parity data corresponding to the written data to the data bits of the written data. Figure 3 The case in is a non-limiting example. For example, if a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon code, etc. are used, the number of parity bits and the size overhead may be determined differently.

[0052] like Figure 3 As shown in , as the number of parity bits increases relative to the same number of data bits (e.g., as the ratio of the number of parity bits to the number of data bits increases), the error detection and correction capability increases. As the number of data bits increases for the same error detection and correction capability, the corresponding number of parity bits increases, but the ratio of the number of parity bits to the number of data bits decreases.

[0053] Thus, the error detection capability and / or error correction capability can be increased as the ratio of the number of parity bits to the corresponding number of data bits increases. As a result, the on-die ECC level can be increased as the ratio of the number of parity bits to the corresponding number of data bits increases. However, because the actual memory capacity decreases as the number of parity bits increases, the error correction capability is limited.

[0054] According to example embodiments, failure of a volatile memory device may be prevented by performing a run-time repair operation based on accumulated error information and error attributes with relatively low error correction capability. Here, failure of a volatile memory device indicates that an error that cannot be corrected by an ECC function occurs in the volatile memory device.

[0055] Figure 4 is a block diagram illustrating a volatile memory device according to example embodiments.

[0056] Reference Figure 4 The volatile memory device 200 may include a control logic circuit 210, an address register 220, a memory bank control logic 230, a refresh counter 245, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an I / O gating circuit block (or, I / O gating circuit) 290, an ECC circuit 400 and a data I / O buffer 295.

[0057] The ECC circuit 400 includes first to eighth ECC engines 400 a to 400 h , and the I / O gating circuit block 290 includes a plurality of I / O gating circuits corresponding to a plurality of bank arrays (or, memory bank arrays).

[0058] The memory cell array 300 includes first to eighth bank arrays 310 to 380. The row decoder 260 includes first to eighth bank row decoders 260a to 260h coupled to the first to eighth bank arrays 310 to 380, respectively, the column decoder 270 includes first to eighth bank column decoders 270a to 270h coupled to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifier unit 285 includes first to eighth bank sense amplifiers 285a to 285h coupled to the first to eighth bank arrays 310 to 380, respectively. The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form first to eighth banks. Each of the first to eighth memory bank arrays 310 to 380 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0059] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address ROW_ADDR to the row address multiplexer 240, and provides the received column address COL_ADDR to the column address latch 250.

[0060] The bank control logic 230 generates a bank control signal in response to the bank address BANK_ADDR. The bank row decoders corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 260a to 260h are activated in response to the bank control signal, and the bank column decoders corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 270a to 270h are activated in response to the bank control signal.

[0061] The row address multiplexer 240 receives the row address ROW_ADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the first to eighth bank row decoders 260a to 260h.

[0062] The activated memory row decoder among the first memory row decoder 260a to the eighth memory row decoder 260h decodes the row address RA output from the row address multiplexer 240, and activates the word line of the memory array corresponding to the row address RA. For example, the activated memory row decoder applies a word line drive voltage to the word line corresponding to the row address RA. The column address latch 250 receives the column address COL_ADDR from the address register 220, and temporarily stores the received column address COL_ADDR. In one or more example embodiments, in burst mode, the column address latch 250 generates a column address incremented from the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address to the first memory column decoder 270a to the eighth memory column decoder 270h.

[0063] The activated bank column decoders among the first to eighth bank column decoders 270a to 270h activate sense amplifiers (i.e., bank sense amplifiers) corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit block 290. Each I / O gating circuit in the I / O gating circuit block 290 includes a circuit for gating input / output data, and also includes a read data latch for storing data output from the first to eighth bank arrays 310 to 380 and a write driver for writing data to the first to eighth bank arrays 310 to 380.

[0064] The codeword CW read from one of the first to eighth memory bank arrays 310 to 380 is sensed by a sense amplifier coupled to the one memory bank array from which data is to be read, and is stored in a read data latch. The codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295 after the codeword CW is ECC decoded by the corresponding ECC engine. Data MD to be written in one of the first to eighth memory bank arrays 310 to 380 may be provided from the memory controller 100 to the data I / O buffer 295, and written into the one memory bank array by a write driver after the data MD is ECC encoded by the corresponding ECC engine.

[0065] The data I / O buffer 295 may provide data MD from the memory controller 100 to the ECC circuit 400 in a write operation of the volatile memory device 200 based on the clock signal CLK, and the data I / O buffer 295 may provide data MD from the ECC circuit 400 to the memory controller 100 in a read operation of the volatile memory device 200.

[0066] In a write operation, the ECC circuit 400 generates parity data (e.g., parity bits) based on the data MD from the data I / O buffer 295, and provides a codeword CW including the data MD and the parity bits to the I / O gating circuit block 290. The I / O gating circuit block 290 may write the codeword CW into one bank array.

[0067] Furthermore, in a read operation, the ECC circuit 400 may receive a codeword CW read from one memory bank array from the I / O gating circuit block 290. The ECC circuit 400 may perform ECC decoding on the data MD based on the parity bit in the codeword CW, may correct a single-bit error or a double-bit error in the data MD, and may provide the corrected data to the data I / O buffer 295. Furthermore, the ECC circuit 400 may provide error position information EPOS indicating a position (e.g., an address) of an error through the ECC decoding, and the error position information EPOS may be provided to the repair manager RMNG in the memory controller 100.

[0068] The control logic circuit 210 may control the operation of the volatile memory device 200. For example, the control logic circuit 210 may generate a control signal for the volatile memory device 200 to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the volatile memory device 200. For example, a value of the mode register 212 may indicate an operation mode.

[0069] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal ( / WE), a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), etc. The control logic circuit 210 may generate a column control signal CCS and a first control signal CTL1 to control the I / O gating circuit block 290 , and generate a second control signal CTL2 to control the ECC circuit 400 .

[0070] Figure 5 It is shown Figure 4 A diagram of a portion of a volatile memory device.

[0071] Reference Figure 5 , the volatile memory device 200a may include a control logic 210, a first memory array 310, an I / O gating circuit 290, and an ECC circuit 400. The first memory array 310 may include a normal cell array NCA and a redundant cell array RCA. The normal cell array NCA may include a plurality of first memory blocks MB0 to MBk (e.g., 311 to 313), and the redundant cell array RCA may include at least a second memory block EDB (e.g., 314), where k is a positive integer. The first memory blocks 311 to 313 are memory blocks that determine the memory capacity of the volatile memory device 200a. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 for ECC and / or redundancy repair is used for ECC, data line repair, or block repair to repair one or more failed cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block.

[0072] In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in rows and columns. In the second memory block 314, a plurality of second memory cells are arranged in rows and columns. The first memory cells connected to the intersection of the word line WL and the bit line BTL (for the first memory blocks 311 to 313) and the second memory cells connected to the intersection of the word line WL and the bit line RBTL (for the second memory block 314) may be dynamic memory cells.

[0073] The I / O gating circuit 290 may include a first switch circuit 291 connected to the first memory blocks 311 to 313 and a second switch circuit 292 connected to the second memory block 314. In the volatile memory device 200a, bit lines corresponding to data of a burst length (BL) may be accessed simultaneously to support the BL indicating the maximum number of accessible column positions. For example, the BL may be set to 8. In this case, each of the bit lines BTL and RBTL may be connected to a corresponding one of the column selectors MUX1 to MUXk and MUXp.

[0074] The ECC circuit 400 may be connected to the first switch circuit 291 and the second switch circuit 292 through the first data line GIO and the second data line EDBIO, respectively. The first data line GIO may be connected to the data node NDd of the ECC circuit 400, and the second data line EDBIO may be connected to the parity node NDp of the ECC circuit 400.

[0075] The control logic circuit 210 may decode the command CMD to generate a first control signal CTL1 for controlling the first and second switch circuits 291 and 292 and a second control signal CTL2 for controlling the ECC circuit 400 .

[0076] The ECC unit that is the object of each ECC operation can be determined as various combinations of data corresponding to the same row address. If the ECC unit includes more errors than the correctable number, the data is permanently lost, causing serious damage to the system using the volatile memory device. According to example embodiments, before an uncorrectable error occurs, a run-time repair operation can be performed by effectively managing correctable errors.

[0077] Fig. 6A and Figure 6B is a diagram illustrating a patrol read operation of a method for controlling repair of a volatile memory device according to example embodiments.

[0078] Reference Fig. 6A and Figure 6B , a plurality of patrol read operations PROPR1, PROPR2, and PROPR3 may be repeatedly performed. For example, each patrol read operation may be performed from a start row address STADD to an end row address EDADD among all row addresses of the volatile memory device. Fig. 6A A non-limiting example of performing multiple patrol read operations PROPR1, PROPR2, and PROPR3 in the same pattern is shown. In some example embodiments, repeated patrol read operations may be performed in different patterns.

[0079] Figure 6B1 shows the timing of one patrol read operation PROPRi. The patrol read operation may be suspended during an active mode (ACTIVE) when performing an access operation to a volatile memory device, and the patrol read operation may be performed only during an idle mode (IDLE). A pointer PADD (e.g., Fig.12 The PADD1 to PADDn-1 in the memory are stored in the repair manager RMNG. When the idle mode is restored, the patrol read operation can be continuously performed based on the stored pointer PADD.

[0080] Figure 7 is a diagram illustrating an example embodiment of a cumulative error table for a method of controlling repair of a volatile memory device according to example embodiments.

[0081] The cumulative error table may be generated and managed for each of the plurality of memory banks. As an example, Figure 7 Three accumulated error tables AET1 , AET2 , and AET3 corresponding to three memory banks are shown, and a detailed description of an example of accumulated error information stored in one accumulated error table AET1 is included.

[0082] The repair manager RMNG may store candidate fail row addresses (PFRADD) RAa to RAf having correctable errors among all row addresses of the volatile memory device and correctable error numbers (EN) 2, 1, 5, 4, 0, and 2 respectively corresponding to the candidate fail row addresses RAa to RAf in the accumulated error table AET1. For example, Figure 7 It is shown that the number of correctable errors of the candidate failed row address RAa is 2, the number of correctable errors of the candidate failed row address RAd is 4, etc. That is, the correctable error number EN is the number of correctable errors in the candidate failed row address. ATT indicates the above-mentioned error attribute. N / A indicates that the error attribute has not been determined and is not assigned to the corresponding candidate failed row address. Figure 7 An example is shown in which an error attribute ATT1 is assigned to (or associated with) candidate failed row addresses RAc, RAd, and RAe. The candidate failed row address RAe assigned with the error attribute may have a correctable error count of zero. In other words, if the error attribute is assigned to a row address, even if the row address has no error, the row address may be included in the cumulative error table, which will be referred to below. Figures 13 to 15 Give a description.

[0083] Figure 8 is a flowchart illustrating a method of controlling repair of a volatile memory device according to example embodiments.

[0084] Reference Figure 8 , whenever a patrol read operation is performed, the accumulated error information AEI may be updated (S11). For each candidate failed row address included in the accumulated error information AEI, it is determined whether the correctable error number EN is greater than the reference error number RN1 (S12). When the correctable error number EN of at least one of the candidate failed row addresses is greater than the reference error number RN1 (S12: Yes), a post package repair operation (PPR) is performed for all candidate failed row addresses corresponding to the correctable error number EN greater than the reference error number RN1 (S13). When the correctable error number EN of all candidate failed row addresses is not greater than the reference error number RN1 (S12: No), the patrol read operation is performed again to update the accumulated error information AEI, and it is determined again whether a post package repair operation is required based on the updated accumulated error information AEI.

[0085] Such an operation sequence may be repeated until the volatile memory device is powered off (S14: No). When the volatile memory device is powered off (S14: Yes), the accumulated error information AEI and the error attribute may be stored in the non-volatile memory device (S15). When the volatile memory device is powered on again, the accumulated error information AEI and the error attribute may be loaded from the non-volatile memory device to the volatile memory device, so that even if the volatile memory device is powered off, the method of controlling the repair of the volatile memory device according to the example embodiment may be continuously performed.

[0086] Fig. 9 1 is a block diagram showing a volatile memory device performing a post-packaging repair operation. For ease of illustration and description, only components used to describe the post-packaging repair operation are shown.

[0087] Reference Fig. 9 , the DRAM device 500 may include a memory cell array 510 , a row decoder (XDEC) 520 , a column decoder (CDEC) 530 , a control logic circuit 540 , and a fuse circuit 550 .

[0088] The memory cell array 510 may include a plurality of DRAM cells. The DRAM cells may be connected to word lines NWL and RWL and bit lines, respectively. A portion of the DRAM cells may be normal cells, and another portion of the DRAM cells may be redundant cells for replacing failed cells among normal cells.

[0089] The row decoder 520 may be connected to the memory cell array 510 through word lines NWL and RWL. The row decoder 520 may select one of a plurality of word lines based on an address ADDR (ie, a row address in the address ADDR) and control a voltage of the selected word line.

[0090] The column decoder 530 may be connected to the memory cell array 510 through the bit lines. The column decoder 530 may select a portion of the plurality of bit lines based on the address ADDR (ie, the column address in the address ADDR), and control or detect a voltage of the selected bit line.

[0091] The control logic circuit 540 may control the overall operation of the DRAM device 500. The fuse setting operation may be performed under the control of the control logic circuit 540. The control logic circuit 540 may be configured to reset the fuse setting of the fuse circuit 550 through a run-time repair operation. Through the fuse setting of the fuse circuit 550, a normal cell may be replaced with a redundant cell. For example, the fuse circuit 550 may receive an address ADDR from a memory controller. When the row address in the address ADDR corresponds to a normal word line NWL determined to be a failed word line, the fuse circuit 550 may output a repair address so that the row decoder 520 may select the redundant word line RWL instead of the normal word line NWL.

[0092] In other words, the fuse circuit 550 may change the fuse setting so that the row address corresponding to the fail address may be converted to the repair address. The row decoder 520 may select the redundant word line RWL based on the repair address from the fuse circuit 550. The fuse circuit 550 may transmit the row address that does not correspond to the fail address to the row decoder 520 without conversion.

[0093] In this way, the DRAM device 500 can perform a post-packaging repair operation for a failed address through the electrical fuse setting of the fuse circuit 550 .

[0094] Fig.10 is a timing diagram showing signals used for post-packaging repair operations.

[0095] For example, a runtime repair operation may be performed based on hard post package repair (hPPR). Fig.10 The signals in the timing diagram can be executed Fig. 9 The electrical fuse setting of the fuse circuit 550 in FIG.

[0096] Reference Fig.10, during the period from time point t1 to time point t2, a DRAM device operating based on clock signals CK_c and CK_t may enter hPPR mode in response to mode register setting commands MRS4 and MRS0 and address signals BG, BA, and ADDR provided from a memory controller. The address signals BG, BA, and ADDR accompanying the deselect command DES and the refresh command REF may include an invalid (i.e., no address) value (NA), and the address signals BG, BA, and ADDR accompanying other commands may include a valid value (VAL). For example, the value (VAL) of address bit A13 may be set to "1" indicating activation of the hPPR operation. In one or more example embodiments, before entering the hPPR mode, data stored in a memory bank including a faulty row may be flushed to a nonvolatile memory device. In addition, before entering the hPPR mode, all memory banks of the DRAM device may be precharged.

[0097] During the time point t2 to the time point t3, the DRAM device may perform the hPPR operation in response to the active command ACT, the automatic precharge write command WRA, and the address signals BGF and BAF. For example, the address signals BGF and BAF may correspond to the failed row. Fig. 9 The electrical fuses of the fuse circuit 550 are described as being arranged to perform hPPR operation.

[0098] During the period from time point t3 to time point t4, the DRAM device may perform hPPR recognition in response to the precharge command PRE, and during the period from time point t4 to time point t5, the DRAM device may exit from the hPPR mode in response to the mode register set command MRS4 and the value "0" of the address bit A13. After exiting the hPPR mode, the DRAM device may recover data based on the flushed data in the nonvolatile memory device.

[0099] Fig.10 A non-limiting example of direct repair is shown, and example embodiments are not limited thereto. In some example embodiments, a normal write command may be used instead of an automatic precharge write command WRA to perform an hPPR operation. In this case, a backup or flush of data stored in all memory banks of the DRAM device may be performed before entering the hPPR mode. Alternatively, direct repair may be performed based on soft post package repair (sPPR).

[0100] Fig.11 and Fig.12 is a diagram illustrating a patrol read operation of a method for controlling repair of a volatile memory device according to example embodiments.

[0101] Reference Fig.11 , a full scan read operation FSR may be sequentially performed for all row addresses of the volatile memory device (S21). In addition, a deep scan read operation DSR may be sequentially performed for candidate failed row addresses included in the accumulated error table more frequently than the full scan read operation FSR (e.g., Fig.11 In other words, while performing one full scan read operation FSR, two or more deep scan read operations DSR are performed. In this way, monitoring by the patrol read operation can be performed for candidate fail row addresses having errors or future errors with a high probability, and malfunction of the volatile memory device can also be prevented.

[0102] As an example, Fig.12 A patrol read operation PROPRi including a full scan read operation FSR and a plurality of deep scan read operations DSR1 to DSRn is shown. A full scan read operation FSR may be divided into a plurality of partial scan read operations PFSR1 to PFSRn, where n is a positive integer greater than 2. Whenever the full scan read operation reaches an intermediate row address among row addresses PADD1 to PADDn-1, each of the deep scan read operations DSR1 to DSRn may start. According to an example embodiment, for ease of explanation, Fig.12 It is shown that the candidate fail row addresses PFRADD for the scan read operation are adjacent in one address area, but the candidate fail row addresses PFRADD may be irregularly distributed on all row addresses addressed between the start row address STADD and the end row address EDADD.

[0103] As a result, multiple deep scan operations may be performed on the candidate fail row address PFRADD while full scan read operations are performed on other row addresses.

[0104] Fig.13 is a diagram illustrating an example layout of a memory cell array included in a volatile memory device according to example embodiments.

[0105] Fig.13 A memory cell array area MCA, a column decoder CDEC and a row decoder XDEC are shown, and other components of the volatile memory device are omitted for ease of explanation. The memory cell array area MCA includes a double word line structure including a main word line NWE and a plurality of sub word lines SWL, a connection area CJ, a sub word line driver area SWD, a sense amplifier area SA and a sub memory cell array area SMCA.

[0106] In one or more example embodiments, a word selection signal line PX, a main word line NWE, a sub word line SWL, a column selection signal line CSL, a local input-output data line LIO, and a global input-output data line GIO may be formed in an upper portion of the memory cell array area MCA. For ease of illustration, Fig.13 The power lines are omitted.

[0107] In the memory cell array area MCA, the connection area CJ, the sub word line driver area SWD, the sense amplifier area SA, and the sub memory cell array area SMCA are repeatedly arranged in the row direction X and the column direction Y. The memory cell MC is formed in the sub memory cell array area SMCA and is connected to the sub word line SWL and the bit line BL. Data can be written to or read from the memory cell MC in response to a signal transmitted through the word selection signal line PX, the main word line NWE, and the column selection signal line CSL.

[0108] The column decoder CDEC generates a signal on the column selection signal line CSL according to the supplied column address COL_ADDR to select one or more columns in the array for reading or writing. The row decoder XDEC decodes the row address ROW_ADDR to generate a signal for selecting one of the main word lines NWE and a signal for selecting one of the word line selection signal lines PX.

[0109] The main word line NWE extends in the row direction X on the sub-word line driver area SWD and the sub-memory cell array area SMCA, and the word selection signal line PX and the local input-output data line LIO extend in the row direction X on the junction area CJ and the sense amplifier area SA. The column selection signal line CSL and the global input-output data line GIO extend in the column direction Y on the sense amplifier area SA and the sub-memory cell array area SMCA.

[0110] Fig.14 and Fig.15 is a diagram for describing an example embodiment of determining an error attribute of a method for controlling repair of a volatile memory device according to example embodiments.

[0111] Fig.14 An example is shown in which a plurality of sub-word lines SWL1 to SWL4 are connected to one main word line NWE through a sub-word line driver SWD. Signals PXID1 to PXID4 and PXIB1 to PXIB4 are generated by address decoding. Fig.14 In FIG. 1 , BL1 to BL6 represent bit lines.

[0112] The sub-word lines SWL1 to SWL4 connected to the same main word line NWE have structural correlation. For example, when a failure occurs in the main word line NWE or in a driver driving the main word line NWE, the number of sub-word lines having errors or the sum of errors in the sub-word lines SWL1 to SWL4 increases. Fig.14 and Fig.15 In the example case shown in FIG. 1 , the error number of the sub-word line SWL3 is zero, but the sub-word line SWL3 may be quickly affected by a failure. To prevent the possibility of such a failure, an error attribute may be assigned to an address group including row addresses RA1 to RA4 corresponding to all sub-word lines SWL1 to SWL4 connected to the same main word line NWE, and the address group RA1 to RA4 may be stored in the cumulative error table as a candidate failed row address.

[0113] In one or more exemplary embodiments, when the sum of the correctable error numbers of the address group is greater than the risk error number, the post-package repair operation may be performed for all row addresses RA1 to RA4 included in the address group. In other words, the post-package repair operation may be performed for the row address RA3 without an error.

[0114] exist Fig.15 , AETb indicates the cumulative error table before the error attribute ATT1 is determined, and AETa indicates the cumulative error table after the error attribute ATT1 is determined. Therefore, according to an embodiment, the cumulative error table may be generated or modified based on the error attribute determination.

[0115] In one or more example embodiments, when the number of candidate failed row addresses included in the address group is greater than a reference number, a main address error attribute may be determined for an address group including row addresses of a plurality of sub word lines corresponding to a main word line of a volatile memory device. Fig.14 and Fig.15 In the example of , the number of candidate failed row addresses corresponds to three, and the reference number is assumed to be two.

[0116] In one or more example embodiments, when a sum of correctable error numbers corresponding to all row addresses included in the address group is greater than a reference error number, a main address error attribute may be determined for an address group including row addresses of a plurality of sub word lines corresponding to a main word line of a volatile memory device. Fig.14 and 15 In the example of , the sum of the number of correctable errors corresponds to 8, and the reference error number is assumed to be 7.

[0117] Fig.16 is a diagram illustrating an example embodiment of a cumulative error table for a method of controlling repair of a volatile memory device according to example embodiments.

[0118] In one or more example embodiments, the repair manager RMNG may store a candidate fail column address having a correctable error in the accumulated error table AET for each of the candidate fail row addresses.

[0119] and Figure 7 Compared with the cumulative error table AET1, Fig.16 The accumulated error table AET may further include a candidate failed column address (PFCADD) CAa to CAk for each of the candidate failed row addresses RAa to ARf.

[0120] In this case, when the number of candidate failed row addresses including the same candidate failed column address is greater than a reference number, a column error attribute may be determined for the same candidate failed column address.

[0121] exist Fig.16 In the example of FIG. 1 , the number of candidate failed row addresses RAa, RAc, RAd, and RAf including the same candidate failed column address CAb is four. If the reference error number is set to three, the column error attribute can be assigned to the candidate failed column address CAb. Fig.17 and Fig.18 As described, a post-packaging repair operation may be performed on the candidate failed column address CAb assigned with the column error attribute.

[0122] Fig.17 is a flowchart illustrating a method of controlling repair of a volatile memory device according to an example embodiment, Fig.18 is a diagram illustrating column repair by a method of controlling repair of a volatile memory device according to example embodiments.

[0123] Reference Fig.17 , each time a patrol read operation is performed, the accumulated error information AEI may be updated (S31). For each candidate failed column address included in the accumulated error information AEI, it is determined whether the number PFRN of candidate failed row addresses including the same candidate failed column address is greater than the reference number RN2 (S32). When the number PFRN is greater than the reference number RN2 (S32: Yes), a post-packaging repair operation is performed for all candidate failed column addresses corresponding to the number PFRN greater than the reference number RN2 (S23). When the number PFRN is not greater than the reference number RN2 (S32: No), a patrol read operation is performed again to update the accumulated error information AEI, and it is determined again whether a post-packaging repair operation is required based on the updated accumulated error information AEI.

[0124] Such an operation sequence may be repeated until the volatile memory device is powered off (S34: No). When the volatile memory device is powered off (S34: Yes), the accumulated error information AEI and the error attribute may be stored in the non-volatile memory device (S35). When the volatile memory device is powered on again, the accumulated error information AEI and the error attribute may be loaded from the non-volatile memory device to the volatile memory device, so that even if the volatile memory device is powered off, the method of controlling the repair of the volatile memory device according to the example embodiment may be continuously performed.

[0125] Fig.18 Shown in Fig.16 The cumulative error table AET case is applied by Fig.17 The bit lines BLa to BLk may be connected to the Fig.16 Corresponding to the candidate failed column addresses CAa to CAk in the table, the word lines WLa to WLf are respectively Fig.16 Corresponding to the candidate failed row addresses RAa to RAf in the reference Fig.16 Similar to the description, the number of failed cells in the memory cells connected by the same bit line BLb is greater than the set reference number. Fig.17 According to the method, by performing a post-packaging repair operation, the bit line BLb can be replaced by a redundant bit line RBLb that does not have a failed cell (or the memory cells connected to it are all good cells) (that is, the candidate failed column address CAb corresponding to the bit line BLb can be replaced by the column address corresponding to the redundant bit line RBLb), thereby preventing uncorrectable errors from occurring.

[0126] Fig.19 is a diagram illustrating an example embodiment of a cumulative error table for a method of controlling repair of a volatile memory device according to example embodiments.

[0127] Reference Fig.19 , previous accumulated error information may be stored in the accumulated error table based on a previous patrol read operation, and current accumulated error information may be stored in the accumulated error table based on a current patrol read operation immediately following the previous patrol read operation.

[0128] exist Fig.19 In the example, a value "0" of the index INX indicates previously accumulated error information, and a value "1" of the index INX indicates currently accumulated error information. Fig.19An example is shown in which an error corresponding to the candidate failed column address CAc is added to the candidate failed row address RAa after the current patrol read operation is performed. On the contrary, an error corresponding to the candidate failed column address CAe is reduced in the candidate failed row address RAb after the current patrol read operation is performed. In this way, the previous accumulated error information and the current accumulated error information can be compared, and the addresses of the candidate failed cells included in the previous accumulated error information but not included in the current accumulated error information can be determined. Based on the addresses of the candidate failed cells, the Fig. 20 Perform the test as described.

[0129] Fig. 20 It shows the use of Fig.19 A diagram of a method of determining a failed memory cell using a cumulative error table.

[0130] Reference Fig. 20 , the candidate failed cells can be determined by writing to and reading from the candidate failed cells using the data bits and the inversion bits of the data bits. Fig.19 Whether the candidate failed cell corresponding to the candidate failed column address CAe in is a failed cell.

[0131] For example, when a value of "0" is read for both the data bit and the inversion bit (for example, when the values ​​of the read bits obtained by performing the tests TST1 and TST2 using the inversion write bits are both "0"), the candidate failure cell can be determined as a card 0 failure cell (0-stucked fail cell) that always outputs a value of "0". On the contrary, when a value of "1" is read for both the data bit and the inversion bit (for example, when the values ​​of the read bits obtained by performing the tests TST1 and TST2 using the inversion write bits are both "1"), the candidate failure cell can be determined as a card 1 failure cell (1-stucked fail cell) that always outputs a value of "1". For other situations, the fault of the candidate failure cell may not be determined (UNKNOWN).

[0132] Fig.21 and Fig. 22 is a diagram illustrating a method of preventing a failure of a volatile memory device using accumulated error information according to example embodiments.

[0133] Reference Fig.21 and Fig. 22In order to prevent a real failure of the volatile memory device 620, when an access write operation NWR is performed by the memory controller 610 to store write data (DTi) to the candidate failure row address (PFADD) RAi in the normal cell array 621, a copy write operation RWR may be performed in the redundant (or copy) cell array 622 to additionally store the write data to the copy row address RRAi corresponding to the candidate failure row address RAi (S41). A normal read operation NRD is performed for the candidate failure row address RAi (S42). When the data read from the candidate failure row address RAi includes an uncorrectable error (S43: No), a copy read operation RRD is performed (S44). When the data read from the copy row address RRAi is correctable (S45: Yes), the data read from the copy row address RRAi instead of the data read from the candidate failure row address RAi may be provided as read data. When the data read from the copy row address RRAi is also uncorrectable (S45: No), the volatile memory device may be determined to be failed (S46).

[0134] In this way, through the replica write operation RWD and the replica read operation RRD, the failure of the volatile memory device can be further prevented, the reliability of the volatile memory device can be improved, and the life of the volatile memory device can be extended.

[0135] Fig.23 is a block diagram illustrating a storage device according to example embodiments.

[0136] Reference Fig.23 , the system 1000 includes a host device 2000 and a storage device 3000. For example, the host device 2000 may be an embedded multimedia card (eMMC).

[0137] The host device 2000 may be configured to control data processing operations, such as data read operations and data write operations. The data processing operations may be performed at a single data rate (SDR) or a double data rate (DDR).

[0138] The host device 2000 may be a data processing device that may process data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor. The host device 2000 and the storage device 3000 may be embedded in an electronic device or implemented in the electronic device. Fig.23 The system 1000 may be any electronic device.

[0139] The memory device 3000 may be electrically connected to other components of the system 1000 (electronic device) through a connection device (eg, a pad, a pin, a bus, or a communication line) to communicate with the host device 2000 .

[0140] The host device 2000 may include a processor (CPU) 2100 , a memory (MEM) 2200 , and a host controller interface (HCI) 2300 connected through a bus 1320 . An operating system (OS) and / or host firmware (FW) 2110 may be driven by the processor 2100 .

[0141] The processor 2100 may include hardware and / or software for controlling the generation of the command CMD, the analysis of the response, the storage of data in a register (e.g., an extended CSD (EXT_CSD) register (not shown)) of the storage device 3000, and / or data processing. The processor 2100 may drive the operating system and the host firmware 2110 to perform these operations. The host controller interface 2300 may interface with the storage device 3000.

[0142] The memory device 3000 may include a plurality of nonvolatile memory devices (NVMs) 3100 and a memory controller 3200 .

[0143] The nonvolatile memory device 3100 may be selectively supplied with an external high voltage VPP. The nonvolatile memory device 3100 may be implemented with a flash memory, a FRAM, a PRAM, an MRAM, or the like.

[0144] The memory controller 3200 may be connected to the nonvolatile memory device 3100 through a plurality of channels CH1 to CHi. The memory controller 3200 may include an ECC block 3220, a host interface 3230, a volatile memory device (VM) 3240, a nonvolatile memory interface 3250, a task queue (TQ) 3260, and one or more processors (CPUs) 3210 connected through a bus 1330. In some example embodiments, the nonvolatile memory device 3100 may include an on-chip ECC engine (not shown), and in this case, the ECC block 3220 may be omitted.

[0145] The volatile memory device 3240 may store data for driving the memory controller 3200. Fig.23 An example embodiment in which the volatile memory device 3240 is included in the memory controller 3200 is shown, but the volatile memory device 3240 is not limited thereto. For example, the volatile memory device 3240 may be placed outside the memory controller 3200.

[0146] The ECC block 3220 may calculate an error correction code value of data to be programmed at a write operation, and may correct errors of read data using the error correction code value at a read operation.

[0147] The processor 3210 is configured to control the overall operation of the memory controller 3200. For example, the processor 3210 may operate firmware including a flash translation layer (FTL), etc. The FTL may perform various functions, such as address mapping, read calibration, error correction, and the like.

[0148] The processor 3210 may have a function of controlling the volatile memory device 3240. In this case, the above-mentioned repair manager 3211 and the accumulated error table AET may be implemented in the processor 3210. The repair manager 3211 may be implemented in the processor 2310 as hardware, software, or a combination of hardware and software.

[0149] The task queue 3260 may store tasks (e.g., write tasks and read tasks provided from the host device 2000) and status information of each task. The host interface 3230 may provide an interface with an external device such as the host device 2000. The nonvolatile memory interface 3250 may provide an interface with the nonvolatile memory device 3100. The host device 2000 and the storage device 3000 may be connected via the bus 1310.

[0150] Fig.24 is a flowchart illustrating a method of controlling repair of a volatile memory device included in a storage device according to example embodiments.

[0151] Reference Fig.23 and Fig.24 , the processor 3210 may load repair information including cumulative error information AEI from the non-volatile memory device 3100 (S51), and store the cumulative error information AEI in the cumulative error table AET. As described above, the repair manager 3211 may repeatedly perform the patrol read operation PROPR (S52) to update the cumulative error information AEI (S53). The repair manager 3211 may determine the error attribute ATT based on the cumulative error information AEI (S54), and perform a runtime repair operation (e.g., a post-packaging repair operation) based on the cumulative error information AEI and the error attribute ATT (S55). When the storage device 3000 is powered off, the cumulative error information AEI may be backed up or flushed to the non-volatile memory device 3100 (S56). However, even if the storage device 3000 is not powered off, the backup of the cumulative error table may be performed periodically.

[0152] The inventive concept can be applied to any volatile memory device that needs to be repaired and a system including the volatile memory device. For example, the inventive concept can be applied to systems such as: memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0153] The above is an illustration of example embodiments and is not to be construed as limiting the example embodiments. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without substantially departing from the disclosure.

Claims

1. A method for controlling repair of a volatile memory device, the method comprising: repeatedly performing a patrol read operation to confirm error location information of one or more errors included in read data from the volatile memory device; acquiring accumulated error information by accumulating error position information based on repeatedly performed patrol read operations; confirming error attribute information based on the accumulated error information, the error attribute information indicating a correlation between the one or more errors included in the read data and a structure of the volatile memory device; as well as performing a run-time repair operation for the volatile memory device based on the accumulated error information and the error attribute information, The step of performing the run-time repair operation includes: when the sum of the correctable error numbers of the row addresses of the address group is greater than the risk error number, performing the post-packaging repair operation for all the row addresses included in the address group, The address group includes row addresses corresponding to all sub-word lines connected to the same main word line.

2. The method according to claim 1, in, The steps to obtain cumulative error information include: One or more candidate failed row addresses with correctable errors among all row addresses of the volatile memory device and the number of correctable errors corresponding to each of the one or more candidate failed row addresses are stored in a cumulative error table as cumulative error information, each of the correctable error numbers indicating the number of errors in the corresponding candidate failed row address.

3. The method according to claim 2, wherein: The steps to perform a patrol read operation include: sequentially performing a full scan read operation for all row addresses of the volatile memory device; and A deep scan read operation is sequentially performed for the one or more candidate failed row addresses.

4. The method according to claim 3, wherein: While one full scan read operation is being performed, two or more deep scan read operations are being performed.

5. The method according to claim 2, wherein: The steps to obtain cumulative error information also include: An address group is stored in the cumulative error table based on the error attribute information, the address group including row addresses having the same correlation with the structure of the volatile memory device as the candidate failed row address.

6. The method according to claim 5, wherein: The steps to confirm the error attribute information include: When the number of the one or more candidate failed row addresses included in an address group including row addresses of a plurality of sub word lines corresponding to main word lines of a volatile memory device is greater than a reference number, main address error attribute information is acquired for the address group.

7. The method according to claim 5, wherein: The steps to confirm the error attribute information include: When a sum of correctable error numbers corresponding to all row addresses included in an address group including row addresses of a plurality of sub word lines corresponding to main word lines of a volatile memory device is greater than a reference number, main address error attribute information is acquired for the address group.

8. The method according to claim 2, wherein: The steps to obtain cumulative error information also include: One or more candidate failing column addresses having correctable errors are stored in a cumulative error table for each of the one or more candidate failing row addresses.

9. The method according to claim 8, wherein: The steps to confirm the error attribute information include: When the number of the one or more candidate failed row addresses including the same candidate failed column address is greater than a reference number, column error attribute information is obtained for the same candidate failed column address.

10. The method according to claim 9, wherein: The steps to perform a runtime repair operation include: A post-packaging repair operation is performed for each of the candidate failed column addresses confirmed as column error attribute information.

11. The method according to claim 2, further comprising: When performing an access write operation to store the write data to the candidate failed row address, performing a copy write operation to additionally store the write data to the copy row address corresponding to the candidate failed row address; as well as When the data read from the candidate failed row address includes an uncorrectable error, the data read from the replica row address is provided instead of the data read from the candidate failed row address.

12. The method according to claim 11, wherein: The steps to perform a runtime repair operation include: performing a post-pack repair operation for a candidate failing row address including an uncorrectable error; and The data read from the replica row address is stored to a redundant word line identified as a word line corresponding to the candidate failed row address through a post-packaging repair operation.

13. The method according to claim 1, further comprising: storing the accumulated error information and the error attribute information in the non-volatile memory device when the volatile memory device is powered off; as well as When the volatile memory device is powered on, the accumulated error information and the error attribute information are loaded from the nonvolatile memory device to the volatile memory device.

14. The method according to claim 1, wherein: The steps to obtain cumulative error information include: storing previous accumulated error information in the accumulated error table based on a previous patrol read operation, the previous accumulated error information including one or more previous candidate failed row addresses having correctable errors among all row addresses of the volatile memory device and one or more previous candidate failed column addresses having correctable errors for each of the one or more previous candidate failed row addresses; and Current accumulated error information including one or more current candidate failed row addresses and one or more current candidate failed column addresses is stored in an accumulated error table based on a current patrol read operation.

15. The method according to claim 14, further comprising: comparing the previous accumulated error information with the current accumulated error information; Acquire addresses of candidate failure units included in previous accumulated error information but not included in current accumulated error information; as well as Whether the candidate fail cell is a fail cell is confirmed by writing to and reading from the candidate fail cell using a data bit and an inversion bit of the data bit.

16. A method of controlling repair of a volatile memory device, the volatile memory device being included in a storage device, the method comprising: repeatedly performing a patrol read operation to confirm error location information of one or more errors included in read data from the volatile memory device while the memory device is in an idle mode; By accumulating error position information based on repeatedly performed patrol read operations, one or more candidate failed row addresses having correctable errors among all row addresses of the volatile memory device and the number of correctable errors respectively corresponding to each of the one or more candidate failed row addresses are stored in a cumulative error table as accumulated error information, each of the numbers of correctable errors indicating the number of errors in the corresponding candidate failed row address; confirming error attribute information based on the accumulated error information, the error attribute information indicating a correlation between the error and a structure of the volatile memory device; as well as performing a post-packaging repair operation on the volatile memory device based on the accumulated error information and the error attribute information, The step of performing the post-packaging repair operation includes: when the sum of the correctable error numbers of the row addresses of the address group is greater than the risk error number, performing the post-packaging repair operation on all the row addresses included in the address group; The address group includes row addresses corresponding to all sub-word lines connected to the same main word line.

17. A storage device, comprising: a non-volatile memory device; as well as a memory controller configured to control access to a non-volatile memory device, the memory controller comprising a volatile memory device and a memory controller configured to control access to the volatile memory device, The memory controller or the volatile memory device includes an error checking and correction engine configured to perform error detection and correction on access data of the volatile memory device, and The memory controller is configured as follows: repeatedly performing a patrol read operation to provide error location information of one or more errors included in read data from the volatile memory device regardless of an access read operation that provides the data read from the volatile memory device, acquiring accumulated error information by accumulating error position information based on repeatedly performed patrol read operations, confirming error attribute information based on the accumulated error information, the error attribute information indicating a correlation between the one or more errors included in the read data and a structure of the volatile memory device, and performing a run-time repair operation for the volatile memory device based on the accumulated error information and the error attribute information, The step of performing the run-time repair operation includes: when the sum of the correctable error numbers of the row addresses of the address group is greater than the risk error number, performing the post-packaging repair operation for all the row addresses included in the address group, The address group includes row addresses corresponding to all sub-word lines connected to the same main word line.

18. The storage device according to claim 17, wherein: The patrol read operation is performed during an idle mode of the memory device.

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