Array substrate and manufacturing method thereof, display panel and device

Abstract

The present invention discloses an array substrate and a preparation method thereof, a display panel and a device, wherein the array substrate comprises a pixel circuit, wherein the pixel circuit comprises a first transistor and a second transistor, wherein the first transistor comprises a first active layer, wherein the second transistor comprises a second active layer, wherein both the first active layer and the second active layer comprise silicon; wherein the array substrate further comprises a first type inorganic layer, a second type inorganic layer and a first via hole, wherein the first via hole is located above the first active layer and at least penetrates the second type inorganic layer, wherein the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer. The first active layer is subjected to a high temperature process through the first via hole, so that the hydrogen ion concentration in the first crystal active layer is less than the hydrogen ion concentration in the second active layer, thereby ensuring that the performance of the first transistor is good while reducing the number of high temperature processes of the second transistor, thereby ensuring that the subthreshold swing of the second transistor is small, the turn-off characteristic is good, the leakage current is small, and the overall characteristic of the pixel circuit is good.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a device. Background Art

[0002] Organic light-emitting display is the mainstream technology for mobile phones, TVs, computers and other displays. Compared with traditional liquid crystal displays, organic light-emitting display has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed. Therefore, organic light-emitting display has gradually become the mainstream display technology.

[0003] Since organic light-emitting displays are current-driven, they require a stable current to control their light emission. The size and stability of the driving current of the organic light-emitting display mainly depend on the driving transistor in the pixel circuit of the organic light-emitting display. Therefore, in the prior art, the pixel circuit of the organic light-emitting display generally includes a driving transistor and a switching transistor, and the driving transistor and the switching transistor can be transistors of the same type. For the same type of driving transistors and switching transistors, they are generally prepared using the same process and have the same characteristics. However, since the functions of the driving transistor and the switching transistor are different, the driving transistor and the switching transistor prepared using the same process often cannot meet the actual display requirements. Summary of the invention

[0004] The present invention provides an array substrate and a preparation method thereof, a display panel and a device. By adding a first via hole at a position corresponding to a driving transistor in the array substrate, a high-temperature process can be performed only on the active layer of the first transistor through the first via hole, thereby ensuring that the first transistor has good characteristics while also ensuring that the second transistor has good turn-off characteristics and small leakage current, thereby ensuring that the overall characteristics of the pixel circuit are good.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, including:

[0006] substrate substrate;

[0007] A pixel circuit located on one side of the substrate, the pixel circuit comprising a first transistor and a second transistor, the first transistor comprising a first active layer, the second transistor comprising a second active layer, the first active layer and the second active layer comprising silicon;

[0008] The array substrate further comprises a first type inorganic layer and a second type inorganic layer located on a side of the first active layer away from the base substrate, the first type inorganic layer is located on a side close to the first active layer, and the second type inorganic layer is located on a side away from the first active layer;

[0009] The array substrate further includes a first via hole, the first via hole at least penetrates the second type inorganic layer, and the vertical projection of the first active layer on the plane where the base substrate is located covers the vertical projection of an end of the first via hole close to the first active layer on the plane where the base substrate is located;

[0010] A hydrogen ion concentration in the first active layer is lower than a hydrogen ion concentration in the second active layer.

[0011] In a second aspect, an embodiment of the present invention further provides a method for preparing an array substrate, which is used to prepare the array substrate improved in the first aspect, wherein the array substrate includes a pixel circuit, the pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon:

[0012] The preparation method comprises:

[0013] providing a substrate base plate;

[0014] Preparing a first active layer and a second active layer on one side of the substrate;

[0015] Preparing a first type of inorganic layer on a side of the first active layer away from the substrate;

[0016] performing a first heating process on the first active layer through the first type inorganic layer;

[0017] Prepare a second type of inorganic layer on a side of the first type of inorganic layer away from the substrate;

[0018] Prepare a first via hole, wherein the first via hole at least penetrates the second inorganic layer, and the vertical projection of the first active layer on the plane where the base substrate is located covers the vertical projection of one end of the first via hole close to the first active layer on the plane where the base substrate is located;

[0019] A second heating process is performed on the first active layer through the first via hole, so that the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer.

[0020] In a third aspect, an embodiment of the present invention further provides a display panel, which includes the array substrate provided in the first aspect.

[0021] In a fourth aspect, an embodiment of the present invention further provides a display device, which includes the display panel provided in the third aspect.

[0022] The array substrate provided by the embodiment of the present invention includes a pixel circuit, the pixel circuit includes a first transistor and a second transistor, and the first active layer in the first transistor and the second active layer in the second transistor both include silicon. By adding a first via hole in the array substrate, the first via hole penetrates at least part of the inorganic layer above the first active layer, and the first active layer can be subjected to a high-temperature process only through the first via hole, so that the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer, on the one hand, the performance of the first transistor is ensured to be good, and on the other hand, the number of high-temperature processes of the second transistor is reduced, so that the subthreshold swing of the second transistor is small, the turn-off characteristics of the second transistor are ensured to be good, the leakage current of the second transistor is small, the overall working effect of the pixel circuit is improved, and the overall characteristics of the pixel circuit are ensured to be good. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of an array substrate in the related art;

[0024] Figure 2 It is a schematic diagram of a subthreshold swing curve of a driving transistor in the related art;

[0025] Figure 3 It is a schematic diagram of a subthreshold swing curve of a switching transistor in the related art;

[0026] Figure 4 is a structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0027] Figure 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0028] Figure 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0029] Figure 7 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0030] Figure 8 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0031] Fig. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0032] Fig.10 is a schematic flow chart of a method for preparing an array substrate provided by an embodiment of the present invention;

[0033] Figure 11-Figure 17 yes Fig.10 The preparation process flow chart corresponding to the preparation method provided;

[0034] Fig.18 is a schematic flow chart of another method for preparing an array substrate provided by an embodiment of the present invention;

[0035] Figure 19-Figure 23 yes Fig.18 A partial preparation process flow chart corresponding to the preparation method provided;

[0036] Fig.24 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0037] Fig.25 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0039] Since the organic light emitting device is a current driven device, the array substrate of the organic light emitting display generally includes a driving transistor and a switching transistor. Figure 1 is a structural schematic diagram of an array substrate in the related art, such as Figure 1 As shown, the array substrate 10 includes a driving transistor 11 and a switching transistor 12. The driving transistor 11 includes a first active layer 111, and the switching transistor 12 includes a second active layer 121. The first active layer 111 and the second active layer 121 both include silicon. Optionally, the first active layer 111 and the second active layer 121 may both include polysilicon. For transistors including silicon, such as polysilicon transistors, it is generally necessary to repair defects in the active layer through a high-temperature process, and at the same time, the active layer is dehydrogenated through a high-temperature process to adjust the transistor performance. However, the high-temperature process will change the subthreshold swing of the transistor. Specifically, Figure 2 It is a schematic diagram of a subthreshold swing curve of a driving transistor in the related art. Figure 3 It is a schematic diagram of a subthreshold swing curve of a switching transistor in the related art, combined with Figure 2 and Figure 3 As shown in FIG. 1 , in order to alleviate the problem of uneven display, the subthreshold swing value of the driving transistor 11 is generally increased by increasing the number of high-temperature processes (the number of high-temperature processes is positively correlated with the subthreshold swing value). However, for the switching transistor 12, under the same number of high-temperature processes as the driving transistor 11, the subthreshold swing curve of the switching transistor 12 drifts to the right, resulting in a leakage current of the switching transistor 12 reaching 10 when the gate-source voltage difference is zero. -11The higher leakage current leads to poor switching characteristics of the switch transistor 12, especially in the case of low-frequency driving, where the data refresh cycle is long and the long-term leakage current leads to poor stability of the switch transistor. How to ensure the leakage current of the switch transistor is small while ensuring the characteristics of the drive transistor has become a technical problem that needs to be solved urgently.

[0040] Based on the above technical problems, an embodiment of the present invention provides an array substrate, including a base substrate; a pixel circuit located on one side of the base substrate, the pixel circuit including a first transistor and a second transistor, the first transistor including a first active layer, the second transistor including a second active layer, and the first active layer and the second active layer both including silicon; the array substrate also includes a first type of inorganic layer and a second type of inorganic layer located on a side of the first active layer away from the base substrate, the first type of inorganic layer is located on a side close to the first active layer, and the second type of inorganic layer is located on a side away from the first active layer; the array substrate also includes a first via hole, the first via hole at least passes through the second type of inorganic layer, and the vertical projection of the first active layer on the plane where the base substrate is located covers the vertical projection of one end of the first via hole close to the first active layer on the plane where the base substrate is located. By adopting the above technical solution, a first via hole is added in the array substrate, and the first via hole penetrates at least a part of the inorganic layer above the first active layer. The first via hole can be used to perform a high-temperature process only on the first active layer. In this way, the hydrogen ions in the first active layer escape through the first via hole, and the hydrogen ion concentration in the first active layer can be made lower than the hydrogen ion concentration in the second active layer. On the one hand, the performance of the first transistor is ensured to be good, and on the other hand, the number of high-temperature processes of the second transistor is reduced, thereby ensuring that the subthreshold swing of the second transistor is small, ensuring that the turn-off characteristics of the second transistor are good, and the leakage current of the second transistor is small, thereby improving the overall working effect of the pixel circuit and ensuring that the overall characteristics of the pixel circuit are good.

[0041] The above is the core idea of ​​the embodiment of the invention. The technical scheme in the embodiment of the invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the invention. Based on the embodiment of the invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the invention.

[0042] Figure 4 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention, such as Figure 4As shown, the array substrate 20 provided in the embodiment of the present invention includes a base substrate 21; a pixel circuit 22 located on one side of the base substrate 21, the pixel circuit 22 includes a first transistor 221 and a second transistor 222, the first transistor 221 includes a first active layer 2211, the second transistor 222 includes a second active layer 2221, the first active layer 2211 and the second active layer 2221 both include silicon, and optionally, the first active layer 111 and the second active layer 121 may both include polysilicon; the array substrate 20 also includes a first active layer 2211 and a second active layer 2221; 211 comprises a first type of inorganic layer 23 and a second type of inorganic layer 24 on a side away from the base substrate 21, the first type of inorganic layer 23 is located on a side close to the first active layer 2211, and the second type of inorganic layer 24 is located on a side away from the first active layer 2211; the array substrate 20 also includes a first via hole 25, the first via hole 25 at least passes through the second type of inorganic layer 24, and the vertical projection of the first active layer 2211 on the plane where the base substrate 21 is located covers the vertical projection of one end of the first via hole 25 close to the first active layer 2211 on the plane where the base substrate 21 is located.

[0043] Exemplarily, in the array substrate provided in the embodiment of the present invention, the pixel circuit 22 may include two transistors (2T), or include seven transistors (7T). The embodiment of the present invention does not limit the specific structure of the pixel circuit 22. Figure 4 Only two transistors are shown by way of example.

[0044] Specifically, Figure 4As shown, the pixel circuit 22 includes a first transistor 221 and a second transistor 222, wherein the first transistor 221 includes a first active layer 2211, and the second transistor 222 includes a second active layer 2221, and the first active layer 2211 and the second active layer 2221 both include silicon, and may optionally include polysilicon, that is, a polysilicon active layer, for example, both are low temperature polysilicon (LTPS) active layers. Further, the array substrate 20 also includes a first type of inorganic layer 23 and a second type of inorganic layer 24 located on a side of the first active layer 2211 away from the base substrate 21, the first type of inorganic layer 23 is located on a side close to the first active layer 2211, and the second type of inorganic layer 24 is located on a side away from the first active layer 2211, wherein the first type of inorganic layer 23 may be one or more inorganic layers, and the second type of inorganic layer 24 may be one or more inorganic layers, which is not limited in the embodiment of the present invention. On this basis, the array substrate 20 also includes a first via hole 25, and the vertical projection of the first via hole 25 on the plane where the base substrate 21 is located is located within the coverage range of the vertical projection of the first active layer 2211 on the plane where the base substrate 21 is located, and the first via hole 25 at least penetrates the second type of inorganic layer 24, so that the first active layer 2211 can be subjected to a high-temperature process through the first via hole 25, and the hydrogen ions in the first active layer 2211 can escape through the first via hole 25. Since the vertical projection of the first active layer 2211 on the plane where the base substrate 21 is located covers the vertical projection of one end of the first via 25 close to the first active layer 2211 on the plane where the base substrate 21 is located, the process of performing a high-temperature process on the first active layer 2211 through the first via 25 does not affect the second active layer 2221, that is, the hydrogen ion concentration in the first active layer 2211 is smaller than the hydrogen ion concentration in the second active layer 2221. In this way, while the first active layer 2211 is dehydrogenated, the hydrogen content of the second active layer 2221 remains unchanged or basically unchanged. While the characteristics of the first transistor 221 are guaranteed, the number of high-temperature processes of the second transistor 222 is reduced, the subthreshold swing of the second transistor is guaranteed to be small, the turn-off characteristics of the second transistor are guaranteed to be good, the leakage current of the second transistor is small, the overall working effect of the pixel circuit is improved, and the overall characteristics of the pixel circuit are guaranteed to be good.

[0045] In summary, the array substrate provided by the embodiment of the present invention, by adding a first via hole in the array substrate, the first via hole penetrates at least a portion of the inorganic layer above the first active layer, and can perform a high-temperature process only on the first active layer through the first via hole, so that the hydrogen ions in the first active layer escape through the first via hole, so that the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer, on the one hand, ensuring that the performance of the first transistor is good, and on the other hand, reducing the number of high-temperature processes of the second transistor, ensuring that the subthreshold swing of the second transistor is small, ensuring that the turn-off characteristics of the second transistor are good, and the leakage current of the second transistor is small, thereby improving the overall working effect of the pixel circuit and ensuring that the overall characteristics of the pixel circuit are good.

[0046] On the basis of the above embodiment, the first transistor 221 can be a driving transistor, and the second transistor 222 can be a switching transistor. Generally speaking, in a pixel circuit, the transistor whose gate is connected to the scanning signal or the light emitting control signal is a switching transistor, and the transistor other than the switching transistor in the pixel circuit is a driving transistor, and the driving transistor is arranged in series on the transmission path of the first power supply signal (PVDD signal), and the gate of the driving transistor writes the data signal, and as the data signal is written, the gate potential of the driving transistor changes. By performing a high-temperature process only on the first active layer in the driving transistor through the first via hole, the hydrogen ions in the first active layer escape through the first via hole, and the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer, on the one hand, the performance of the driving transistor is guaranteed to be good, and on the other hand, the number of high-temperature processes of the switching transistor is reduced, the subthreshold swing of the switching transistor is guaranteed to be small, the turn-off characteristics of the switching transistor are guaranteed to be good, the leakage of the switching transistor is small, the overall working effect of the pixel circuit is improved, and the overall characteristics of the pixel circuit are guaranteed to be good.

[0047] Based on the above embodiment, the first via hole at least penetrates the second type of inorganic layer. The first via hole may only penetrate the second type of inorganic layer, or the first via hole may penetrate both the second type of inorganic layer and the first type of inorganic layer. The above two situations are described below respectively.

[0048] Continue to refer Figure 4 As shown, Figure 4 The first via hole 25 penetrating the second inorganic layer 24 is used as an example for description. Figure 4 As shown, the first via hole 25 penetrates the second type inorganic layer 24, so in the process of preparing the first via hole 25, it is not necessary to etch the surface of the first active layer 2211, and the first active layer 2211 can be exempted from etching, ensuring the good integrity of the first active layer 2211. Moreover, even if the first via hole 25 is not etched to the first active layer 2211, the hydrogen ions in the first active layer 2211 can also escape through the first via hole 25, ensuring the normal escape of hydrogen ions on the basis of ensuring that the first active layer 2211 is exempted from etching, and ensuring the good characteristics of the first transistor 221.

[0049] Figure 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Figure 5 The first via hole 25 penetrates both the second type inorganic layer 24 and the first type inorganic layer 23 as an example for description. Figure 5 As shown, the first via 25 penetrates both the second type inorganic layer 24 and the first type inorganic layer 23, and the first via 25 is etched to the surface of the first active layer 2211, thereby ensuring that the hydrogen ions in the first active layer 2211 can escape through the first via 25 without hindrance, ensuring that the hydrogen ion escape channel is unobstructed, the hydrogen ion escape effect is good, and ensuring that the first transistor 221 has excellent characteristics.

[0050] Continue to refer Figure 4 and Figure 5 As shown, the first transistor 221 further includes a first source 2213 and a first drain 2214, and the second transistor 222 further includes a second source 2222 and a second drain 2223. The first source 2213 and the first drain 2214 are electrically connected to the first active layer 2211 through the first source-drain via 27 (second via 27), and the second source 2222 and the second drain 2223 are electrically connected to the second source 2221 through the second source-drain via 28 (third via 28). Figure 4 and Figure 5 As shown, no matter the first via 25 only penetrates the second inorganic layer 24 or the first via 25 penetrates both the second inorganic layer 24 and the first inorganic layer 23, in the direction perpendicular to the base substrate 21, the depth of the first via 25 is smaller than the first source-drain via 27 and the second source-drain via 28, that is, the end of the first via 25 away from the base substrate 21 is closer to the base substrate 21 and the first active layer 2211 than the ends of the first source-drain via 27 and the second source-drain via 28 away from the base substrate 21.

[0051] Figure 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Figure 7 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention, Figure 6 and Figure 7 As shown, the pixel circuit 22 provided in the embodiment of the present invention may further include a third transistor 223, the third transistor 223 includes a third active layer 2231, the third active layer 2231 includes an oxide semiconductor, that is, an oxide semiconductor active layer, and the third active layer 2231 is located on the side of the first active layer 2211 away from the substrate 21; the first type of inorganic layer 23 and the second type of inorganic layer 24 are located between the film layer where the first active layer 2211 is located and the film layer where the third active layer 2231 is located.

[0052] For example, Figure 6 and Figure 7 As shown, the pixel circuit 22 provided in the embodiment of the present invention may further include a third transistor 223, the third transistor 223 includes a third active layer 2231, the third active layer 2231 may include an oxide semiconductor, that is, an oxide semiconductor active layer, such as an indium gallium zinc oxide (IGZO) active layer, the leakage current in the oxide semiconductor transistor is very small, which can ensure that the leakage current is small during the operation of the pixel circuit 22, and ensure that the pixel circuit 22 has good performance.

[0053] Furthermore, since the oxide semiconductor active layer is sensitive to hydrogen ions, hydrogen ions will cause the performance of the oxide semiconductor transistor to deteriorate. Therefore, in the embodiment of the present invention, the first type of inorganic layer 23 and the second type of inorganic layer 24 are arranged between the film layer where the first active layer 2211 is located and the film layer where the third active layer 2231 is located. Correspondingly, in the actual preparation process, a first via 25 is first formed that at least penetrates the second type of inorganic layer 24, and after the first active layer 2211 is subjected to a high-temperature process through the first via 25, the third transistor 223 is prepared on the side of the second type of inorganic layer 24 away from the base substrate 21. In this way, the hydrogen ions escaping from the high-temperature process of the first active layer 2211 will not affect the third active layer 2231, thereby ensuring that the third transistor 223 has excellent performance.

[0054] Optional, continue to refer to Figure 6 and Figure 7 As shown, the pixel circuit 22 provided in the embodiment of the present invention may further include a capacitor 224, and the capacitor 224 includes a first capacitor substrate 2241 and a second capacitor substrate 2242 arranged opposite to each other; the first transistor 221 may further include a first gate 2212 located on the side of the first active layer 2211 away from the base substrate 21, the first capacitor substrate 2241 and the first gate 2212 are arranged in the same layer, and the second capacitor substrate 2242 is located on the side of the first capacitor substrate 2241 away from the base substrate 21; the array substrate 20 may further include a first insulating layer 31 located between the first active layer 2211 and the first gate 2212, a second insulating layer 32 located between the first gate 2212 and the second capacitor substrate 2242, and a third insulating layer 33 located between the second capacitor substrate 2242 and the third active layer 2231; at least one of the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer, and the first via 25 penetrates the silicon nitride layer.

[0055] Exemplarily, the pixel circuit 22 may further include a capacitor 224, which may be used as a storage element to ensure the stability of the gate potential of the first transistor 221. Specifically, the capacitor 224 may include a first capacitor substrate 2241 and a second capacitor substrate 2242, wherein the first capacitor substrate 2241 may be disposed on the same layer as the first gate 2212 of the first transistor 221, and the second capacitor substrate 2242 is located on a side of the first gate 2212 away from the base substrate 21, wherein Figure 6 and Figure 7 Taking the first gate 2212 reused as the first capacitor substrate 2241 as an example for explanation, this can ensure that the film structure of the array substrate 20 is streamlined while ensuring that the preparation process of the first gate 2212 and the first capacitor substrate 2241 is simple.

[0056] On this basis, the array substrate 20 may further include a first insulating layer 31 located between the first active layer 2211 and the first gate 2212, a second insulating layer 32 located between the first gate 2212 and the second capacitor substrate 2242, and a third insulating layer 33 located between the second capacitor substrate 2242 and the third active layer 2231, wherein the first insulating layer 31 may be the above-mentioned first type inorganic layer 23, the second insulating layer 32 and the third insulating layer 33 may be the above-mentioned second type inorganic layer 24, or the first insulating layer 31 and the second insulating layer 32 may be the above-mentioned first type inorganic layer 23, and the third insulating layer 33 may be the above-mentioned second type inorganic layer 24, which is not limited in this embodiment of the present invention. Figure 6 and Figure 7 The first insulating layer 31 is the first type inorganic layer 23, and the second insulating layer 32 and the third insulating layer 33 are the second type inorganic layer 24. Since the silicon nitride layer has a strong blocking effect on the escape of hydrogen ions, when at least one of the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer, the first via 25 penetrates the silicon nitride layer, thereby ensuring that the hydrogen ion escape channel is smooth, ensuring that the hydrogen ions in the first active layer 2211 can escape smoothly, and ensuring that the first active layer 2211 has excellent performance.

[0057] Specific, combined Figure 6 As shown, Figure 6 The second insulating layer 32 and / or the third insulating layer 33 in the embodiment may be a silicon nitride layer, and the first via hole 25 penetrates the silicon nitride layer; Figure 7 As shown, Figure 7 At least one of the first insulating layer 31, the second insulating layer 32 or the third insulating layer 33 may be a silicon nitride layer, and the first via 25 penetrates the silicon nitride layer to ensure that the hydrogen ion escape channel is smooth and the hydrogen ions in the first active layer 2211 can escape smoothly.

[0058] As a feasible implementation method, continue to refer to Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, the array substrate 20 provided by the embodiment of the present invention may also include a third inorganic layer 26 located on the side of the second inorganic layer 24 away from the base substrate 21. The third inorganic layer 26 may include multiple layers of third inorganic layers. The third inorganic layer close to the side of the second inorganic layer 24 covers the second inorganic layer 24 and fills the first via 25.

[0059] Exemplarily, after the first active layer 2211 is subjected to a high temperature process through the first via hole 25, the third inorganic layer close to the second inorganic layer 24 can fill the first via hole 25, so that there is no suspended unfilled area in the array substrate 20, ensuring the structural stability of the array substrate 20.

[0060] As a feasible implementation method, continue to refer to Figure 6 and Figure 7 As shown, the array substrate 20 provided in the embodiment of the present invention may further include a second via 27 and a third via 28, the second via 27 being the first source-drain via 27 mentioned above, the third via 28 being the second source-drain via 28 mentioned above, the second via 27 and the third via 28 both passing through the first type inorganic layer 23, the second type inorganic layer 24 and the third type inorganic layer 26; the vertical projection of the second via 27 on the plane where the base substrate 21 is located at least partially overlaps with the vertical projection of the first via 25 on the base substrate 21, the vertical projection of the second active layer 2221 on the base substrate 21 covers the vertical projection of the end of the third via 28 close to the second active layer 2221 on the plane where the base substrate 21 is located; the array substrate 20 may further include a fourth via 29, the fourth via 29 passing through the third type inorganic layer 26 on the side of the third active layer 2231 away from the base substrate 21, the third active layer 2231 on the base substrate 21 The vertical projection covers the vertical projection of one end of the fourth via 29 close to the third active layer 2231 on the plane of the base substrate 21; the first transistor 221 also includes a first source 2213 and a first drain 2214, the second transistor 222 also includes a second source 2222 and a second drain 2223, and the third transistor 223 also includes a third source 2232 and a third drain 2233; the first source 2213, the first drain 2214, the second source 2222, the second drain 2223, the third source 2232 and the third drain 2233 are arranged in the same layer; the first source 2213 and the first drain 2214 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29.

[0061] For example, continue to refer to Figure 6 and Figure 7 As shown, the first transistor 221 also includes a first source 2213 and a first drain 2214, the second transistor 222 also includes a second source 2222 and a second drain 2223, and the third transistor 223 also includes a third source 2232 and a third drain 2233; the first source 2213, the first drain 2214, the second source 2222, the second drain 2223, the third source 2232 and the third drain 2233 are arranged on the same layer, and the film layer structure of the array substrate 20 is simple. Furthermore, the array substrate 20 provided in the embodiment of the present invention may also include a second via 27, a third via 28 and a fourth via 29. The second via 27 and the third via 28 both penetrate the first inorganic layer 23, the second inorganic layer 24 and the third inorganic layer 26. The third via 29 penetrates the third inorganic layer 26 above the third active layer 2231, so that the first source 2213 and the first drain 2214 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29, thereby realizing a complete connection relationship among the first transistor 221, the second transistor 222 and the third transistor 223.

[0062] Based on the above implementation, continue to refer to Figure 6 and Figure 7 As shown, since the first transistor 221 and the second transistor 222 both include a polysilicon active layer, the first active layer 2211 and the second active layer 2221 can be arranged in the same layer, ensuring that the film structure of the array substrate 20 is simple. Further, the first transistor 221 of the present invention can also include a first gate 2212, and the second transistor 222 can also include a second gate 2224, wherein the first gate 2212 and the second gate 2224 can be arranged in the same layer, ensuring that the film structure of the array substrate 20 is simple.

[0063] Based on the above implementation, Figure 8 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Figure 8As shown, the third transistor 223 may be a dual-gate transistor, for example, the third transistor 223 may include a third gate 2234 located on the side of the third active layer 2231 away from the substrate 21 and a fourth gate 2235 located on the side of the third active layer 2231 close to the substrate 21, that is, the third transistor 223 is a dual-gate transistor with a top gate and a bottom gate structure, ensuring the stable performance of the third transistor 223. It should be noted that since the third transistor 223 may be an oxide semiconductor transistor, generally speaking, the volume of oxide semiconductor transistors is relatively large, setting the third transistor 223 as a dual-gate transistor with a top gate and a bottom gate stacked is conducive to reducing the volume of the third transistor, and further realizing the miniaturization design of the entire pixel circuit.

[0064] Based on the above implementation, the first transistor 221 and the second transistor 222 can also be dual-gate transistors (not shown in the figure). Since the active layers of the first transistor 221 and the second transistor 222 both include silicon, such as polysilicon, the first transistor 221 and the second transistor 222 can be, for example, polysilicon transistors. Since the polysilicon transistor is small in size, when the first transistor 221 and the second transistor 222 are both dual-gate structure transistors, the two gates of the first transistor 221 can both be top gate structures, for example, both are located on the side of the first active layer 2211 away from the substrate 21, and the two gates of the second transistor 222 can both be top gate structures, for example, both are located on the side of the second active layer 2221 away from the substrate 21. Of course, the two gates in the first transistor 221 can be located on both sides of the film layer where the first active layer 2211 is located, and the two gates in the second transistor 222 can be located on both sides of the film layer where the second active layer 2221 is located, and the two gates in the first transistor 221 and the two gates in the second transistor 222 can be arranged in the same layer, so that the array substrate structure is simple while ensuring the excellent performance of the first transistor (for example, small leakage current). The embodiment of the present invention does not limit the specific structure of the first transistor 221 and the second transistor 222.

[0065] Fig. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Fig. 9 As shown, in the direction perpendicular to the substrate, one end of the first via 25 close to the substrate 21 does not overlap with one end of the second via 27 close to the substrate 21, so that the setting position of the second via 27 does not have to be limited to the setting position of the first via 25. The setting position of the second via 27 has high flexibility, low process complexity, and meets the diversified design requirements of the second via 27.

[0066] Based on the inventive concept, the present invention also provides a method for preparing an array substrate, which is used to prepare the array substrate described in the above embodiment. Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, the array substrate 20 includes a pixel circuit 22, the pixel circuit 22 includes a first transistor 221 and a second transistor 222, the first transistor 221 includes a first active layer 2211, the second transistor 222 includes a second active layer 2221, and the first active layer 2211 and the second active layer 2221 both include silicon. Fig.10 FIG. 1 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present invention. Fig.10 As shown, the method for preparing the array substrate provided by the embodiment of the present invention includes:

[0067] S110, providing a substrate.

[0068] like Fig.11 As shown, the substrate 21 may be a flexible substrate or a rigid substrate, which is not limited in the embodiment of the present invention. When the substrate 21 is a flexible substrate, the substrate 21 may include a flexible layer, such as polyimide (PI), or may include two layers of polyimide (PI), which is not limited in the embodiment of the present invention.

[0069] S120, preparing a first active layer and a second active layer on one side of the substrate.

[0070] like Fig.12 As shown, the first active layer 2211 and the second active layer 2221 both include silicon, for example, both include polycrystalline silicon, and are polycrystalline silicon active layers, for example, low-temperature polycrystalline silicon active layers.

[0071] S130, preparing a first type inorganic layer on a side of the first active layer away from the substrate.

[0072] like Fig.12 As shown, the first type inorganic layer 23 covers the first active layer 2211 and the second active layer 2221, and the first type inorganic layer 23 may include one or more inorganic layers. Fig.12 The description is made by taking the example that the first type inorganic layer 23 includes one inorganic layer.

[0073] S140, performing a first heating process on the first active layer through the first type inorganic layer.

[0074] like Fig.14 As shown, a first heating process is performed on the first active layer 2211 and the second active layer 2221 through the first type inorganic layer 23 to activate the first active layer 2211 and the second active layer 2221 to repair defects.

[0075] S150, preparing a second type of inorganic layer on a side of the first type of inorganic layer away from the substrate.

[0076] like Fig.15 As shown, the second type inorganic layer 24 is located on the side of the first type inorganic layer 23 away from the substrate 21, and the second type inorganic layer 24 covers the first type inorganic layer 23. Further, the second type inorganic layer 24 may include one or more inorganic layers. Fig.15 The example in which the second inorganic layer 24 includes two inorganic layers is used for description.

[0077] Further, such as Fig.15 As shown, the first gate 2212 of the first transistor 221, the second gate 2224 of the second transistor 222 and the capacitor structure 224 can be prepared at the same time as the second type of inorganic layer is prepared. The capacitor structure 224 includes a first capacitor substrate 2241 and a second capacitor substrate 2242, wherein the first capacitor substrate 2241 and the first gate 2212 are arranged in the same layer. Fig.15 An example in which a first gate 2212 is reused as the first capacitor substrate 2341 is used for description.

[0078] S160, preparing a first via hole, wherein the first via hole at least penetrates the second inorganic layer, and a vertical projection of the first active layer on the plane where the base substrate is located covers a vertical projection of an end of the first via hole close to the first active layer on the plane where the base substrate is located.

[0079] like Fig.16 As shown, a first via hole 25 is prepared above the area corresponding to the first active layer 2211, that is, the vertical projection of the first active layer 2211 on the plane where the base substrate 21 is located covers the vertical projection of one end of the first via hole 25 close to the first active layer 2211 on the plane where the base substrate 21 is located. Further, the first via hole 25 at least penetrates the second inorganic layer 24, Fig.16 The first via hole 25 penetrating the second inorganic layer 24 is taken as an example for description.

[0080] S170 , performing a second heating process on the first active layer through the first via hole, so that the hydrogen ion concentration in the first active layer is lower than the hydrogen ion concentration in the second active layer.

[0081] like Fig.17 As shown, the first active layer 2211 is subjected to a second heating process through the first via hole 25, and the hydrogen ions in the first active layer 2211 are moved out through the first via hole 25, thereby ensuring that the hydrogen ion concentration in the first active layer 2211 is less than the hydrogen ion concentration in the second active layer 2221, on the one hand, ensuring good performance of the first transistor 221, and on the other hand, ensuring that the subthreshold swing of the second transistor 222 is small, ensuring that the turn-off characteristics of the second transistor 222 are good.

[0082] In summary, the method for preparing an array substrate provided by an embodiment of the present invention first performs a first high-temperature process on the first active layer and the second active layer to eliminate defects in the first active layer and the second active layer; then, a first via is prepared in at least the second type of inorganic layer, and the first via penetrates at least a portion of the inorganic layer above the first active layer, and the first active layer is subjected to a second high-temperature process through the first via, so that the hydrogen ions in the first active layer escape through the first via, so that the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer, on the one hand, ensuring good performance of the first transistor, and on the other hand, reducing the number of high-temperature processes of the second transistor, ensuring that the subthreshold swing of the second transistor is small, ensuring that the turn-off characteristics of the second transistor are good, and the leakage current of the second transistor is small, thereby improving the overall working effect of the pixel circuit and ensuring that the overall characteristics of the pixel circuit are good.

[0083] On the basis of the above embodiment, preparing a first via hole, wherein the first via hole at least penetrates the second type inorganic layer, includes: preparing a first via hole, wherein the first via hole penetrates the second type inorganic layer.

[0084] For example, Fig.16 As shown, the first via hole 25 penetrates the second type inorganic layer 24, so in the process of preparing the first via hole 25, it is not necessary to etch the surface of the first active layer 2211, and the first active layer 2211 can be exempted from etching, ensuring the good integrity of the first active layer 2211. Moreover, even if the first via hole 25 is not etched to the first active layer 2211, the hydrogen ions in the first active layer 2211 can also escape through the first via hole 25, ensuring the normal escape of hydrogen ions on the basis of ensuring that the first active layer 2211 is exempted from etching, and ensuring the good characteristics of the first transistor 221.

[0085] On the basis of the above embodiment, preparing a first via hole, wherein the first via hole at least penetrates the second type inorganic layer, includes: preparing a first via hole, wherein the first via hole penetrates the second type inorganic layer and the first type inorganic layer.

[0086] Exemplarily, the first via hole penetrates both the second type inorganic layer and the first type inorganic layer, and the first via hole is etched to the surface of the first active layer, thereby ensuring that the hydrogen ions in the first active layer can escape through the first via hole unimpeded, ensuring that the hydrogen ion escape channel is unobstructed, the hydrogen ion escape effect is good, and ensuring that the first transistor has excellent characteristics.

[0087] On the basis of the above embodiment, the pixel circuit further includes a third transistor, the third transistor includes a third active layer, the third active layer includes an oxide semiconductor, that is, an oxide semiconductor active layer, and correspondingly, Fig.18 FIG. 1 is a flow chart of another method for preparing an array substrate provided by an embodiment of the present invention. Fig.18 As shown, the method for preparing the array substrate provided by the embodiment of the present invention includes:

[0088] S210, providing a substrate.

[0089] Continue to refer Fig.11 shown.

[0090] S220, preparing a first active layer and a second active layer on one side of the substrate.

[0091] Continue to refer Fig.12 shown.

[0092] S230 , preparing a first type inorganic layer on a side of the first active layer away from the substrate.

[0093] Continue to refer Fig.12 shown.

[0094] S240, performing a first heating process on the first active layer through the first type inorganic layer.

[0095] Continue to refer Fig.14 shown.

[0096] S250, preparing a second type of inorganic layer on a side of the first type of inorganic layer away from the substrate.

[0097] Continue to refer Fig.15 shown.

[0098] S260, preparing a first via hole, wherein the first via hole at least penetrates the second inorganic layer, and a vertical projection of the first active layer on the plane where the base substrate is located covers a vertical projection of an end of the first via hole close to the first active layer on the plane where the base substrate is located.

[0099] Continue to refer Fig.16 shown.

[0100] S270 , performing a second heating process on the first active layer through the first via hole, so that the hydrogen ion concentration in the first active layer is lower than the hydrogen ion concentration in the second active layer.

[0101] Continue to refer Fig.17 shown.

[0102] S280, preparing a third active layer on a side of the second inorganic layer away from the substrate.

[0103] Exemplarily, before, during or after preparing the third active layer, a third type of inorganic layer is prepared on the side of the second type of inorganic layer away from the substrate, the third type of inorganic layer includes multiple layers of third inorganic layers, and the third inorganic layer close to the side of the second type of inorganic layer covers the second type of inorganic layer and fills the first via.

[0104] The following description will be made by taking an example where the third type of inorganic layer includes multiple third inorganic layers and the third active layer is prepared while the multiple third inorganic layers are prepared.

[0105] like Fig.19 As shown, a third inorganic layer is prepared on the side of the second type inorganic layer 24 away from the base substrate 21, and the third inorganic layer fills the first via hole 25. The first via hole 25 is filled by the third inorganic layer close to the side of the second type inorganic layer 24, so that there is no suspended unfilled area in the array substrate 20, ensuring the stability of the structure of the array substrate 20.

[0106] like Fig. 20 As shown, a third active layer 2231 is prepared on the side of the third inorganic layer away from the substrate 21. The third active layer 2231 may include an oxide semiconductor, that is, an oxide semiconductor active layer, such as an indium gallium zinc oxide (IGZO) active layer. The leakage current in the oxide semiconductor transistor is very small, which can ensure that the leakage current is small during the operation of the pixel circuit 22 and ensure that the pixel circuit 22 has good performance.

[0107] S290 , preparing a second via hole, a third via hole, and a fourth via hole.

[0108] like Fig.21 As shown, the second via hole 27 and the third via hole 28 both penetrate the first type inorganic layer 23, the second type inorganic layer 24 and the third type inorganic layer 26; the vertical projection of the second via hole 27 on the plane where the base substrate 21 is located overlaps at least partially with the vertical projection of the first via hole 25 on the base substrate 21, and the vertical projection of the second active layer 2221 on the base substrate 21 covers the vertical projection of the end of the third via hole 28 close to the second active layer 2221 on the plane where the base substrate 21 is located. Optionally, the second via hole 27 and the third via hole 28 can be prepared simultaneously using the same mask process.

[0109] like Fig. 22 As shown, the fourth via 29 penetrates the third type inorganic layer 26 on the side of the third active layer 2231 away from the base substrate 21, and the vertical projection of the third active layer 2231 on the base substrate 21 covers the vertical projection of the end of the fourth via 29 close to the third active layer 2231 on the plane where the base substrate 21 is located.

[0110] It should be noted that the embodiment of the present invention does not limit the preparation order of the second via, the third via and the fourth via. The fourth via can be prepared after the second via and the third via are prepared, or the second via and the third via can be prepared after the fourth via.

[0111] S300, preparing a first source and a first drain of a first transistor, a second source and a second drain of a second transistor, and a third source and a third drain of a third transistor on a side of the third inorganic layer away from the substrate.

[0112] like Fig.23As shown, the first source 2213 and the first drain 2213 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29, thereby realizing a complete connection relationship among the first transistor 221, the second transistor 222 and the third transistor 223.

[0113] Based on the above embodiment, preparing the first active layer and the second active layer on one side of the substrate may include:

[0114] The first active layer 2211 and the second active layer 2221 are prepared on one side of the base substrate 21 by using the same mask process. The first active layer 2211 and the second active layer 2221 are arranged in the same layer, thus ensuring that the preparation process of the first active layer 2211 and the second active layer 2221 is simple.

[0115] Furthermore, the preparation method may also include:

[0116] Using the same mask process, a first gate is prepared on a side of the first active layer away from the substrate, and a second gate is prepared on a side of the second active layer away from the substrate. The first gate and the second gate are arranged in the same layer.

[0117] Continue to refer Fig.15 As shown, the first gate 2212 and the second gate 2224 are prepared by using the same mask process, and the first gate 2212 and the second gate 2224 can be arranged in the same layer, ensuring that the film structure of the array substrate 20 is simple.

[0118] Based on the same inventive concept, an embodiment of the present invention also provides a display panel, including the array substrate described in any of the above embodiments. Therefore, the display panel also has the technical effects of the array substrate provided in the above implementation mode. The similarities can be understood by referring to the explanation of the array substrate in the above text and will not be repeated below.

[0119] For example, the display panel 40 may be an organic light emitting diode (OLED) display panel, such as Fig.24 As shown, an organic light emitting diode (OLED) display panel 40 includes an array substrate 20 and an organic light emitting diode 30. Further, the display panel may also be other types of display panels known to those skilled in the art, such as a micro light emitting diode display panel, which is not limited in the embodiment of the present invention.

[0120] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes any one of the display panels provided in the above embodiments. Fig.25 The display device 50 includes a display panel 40. Therefore, the display device also has the beneficial effects of the display panel and the array substrate in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel and the array substrate, which will not be repeated below.

[0121] The display device 50 provided in the embodiment of the present invention can be Fig.25 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0122] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A pixel circuit located on one side of the substrate, the pixel circuit comprising a first transistor and a second transistor, the first transistor comprising a first active layer, the second transistor comprising a second active layer, and the first active layer and the second active layer both comprising silicon; The array substrate further comprises a first type inorganic layer and a second type inorganic layer located on a side of the first active layer away from the base substrate, the first type inorganic layer is located on a side close to the first active layer, and the second type inorganic layer is located on a side away from the first active layer; The array substrate further includes a first via hole, the first via hole at least penetrates the second type inorganic layer, and the vertical projection of the first active layer on the plane where the base substrate is located covers the vertical projection of an end of the first via hole close to the first active layer on the plane where the base substrate is located; A hydrogen ion concentration in the first active layer is lower than a hydrogen ion concentration in the second active layer.

2. The array substrate according to claim 1, characterized in that: The first transistor further includes a first source and a first drain, wherein the first source and the first drain are electrically connected to the first active layer through second via holes respectively; In a direction perpendicular to the base substrate, an end of the first via hole away from the base substrate is closer to the base substrate than an end of the second via hole away from the base substrate.

3. The array substrate according to claim 1, characterized in that: The first transistor is a driving transistor, and the second transistor is a switching transistor.

4. The array substrate according to claim 1, characterized in that: The first via hole penetrates the second inorganic layer.

5. The array substrate according to claim 1, characterized in that: The first via hole penetrates the first type inorganic layer and the second type inorganic layer.

6. The array substrate according to claim 1, characterized in that: The pixel circuit further includes a third transistor, the third transistor includes a third active layer, the third active layer includes an oxide semiconductor, and the third active layer is located on a side of the first active layer away from the substrate; The first type of inorganic layer and the second type of inorganic layer are located between the film layer where the first active layer is located and the film layer where the third active layer is located.

7. The array substrate according to claim 6, characterized in that: The pixel circuit further includes a capacitor, and the capacitor includes a first capacitor substrate and a second capacitor substrate arranged opposite to each other; The first transistor further comprises a first gate located on a side of the first active layer away from the base substrate, the first capacitor substrate and the first gate are arranged on the same layer, and the second capacitor substrate is located on a side of the first capacitor substrate away from the base substrate; The array substrate further comprises a first insulating layer located between the first active layer and the first gate, a second insulating layer located between the first gate and the second capacitor substrate, and a third insulating layer located between the second capacitor substrate and the third active layer; At least one of the first insulating layer, the second insulating layer and the third insulating layer is a silicon nitride layer, and the first via hole penetrates the silicon nitride layer.

8. The array substrate according to claim 6, characterized in that: The array substrate also includes a third type inorganic layer located on the side of the second type inorganic layer away from the base substrate, the third type inorganic layer includes multiple third inorganic layers, and the third inorganic layer close to the second type inorganic layer covers the second type inorganic layer and fills the first via hole.

9. The array substrate according to claim 8, characterized in that: The array substrate further includes a second via hole and a third via hole, the second via hole and the third via hole both penetrate the first type inorganic layer, the second type inorganic layer and the third type inorganic layer; a vertical projection of the second via hole on the plane where the base substrate is located at least partially overlaps with a vertical projection of the first via hole on the base substrate, and a vertical projection of the second active layer on the base substrate covers a vertical projection of an end of the third via hole close to the second active layer on the plane where the base substrate is located; The array substrate further includes a fourth via hole, the fourth via hole penetrating the third type inorganic layer on the side of the third active layer away from the base substrate, and the vertical projection of the third active layer on the base substrate covers the vertical projection of one end of the fourth via hole close to the third active layer on the plane where the base substrate is located; The first transistor further includes a first source and a first drain, the second transistor further includes a second source and a second drain, and the third transistor further includes a third source and a third drain; the first source, the first drain, the second source, the second drain, the third source and the third drain are arranged in the same layer; The first source electrode and the first drain electrode are electrically connected to the first active layer through the second via hole; The second source electrode and the second drain electrode are electrically connected to the second active layer through the third via hole; The third source electrode and the third drain electrode are electrically connected to the third active layer through the fourth via hole.

10. The array substrate according to claim 9, characterized in that: The first transistor further includes a first gate located at one side of the first active layer; The second transistor further comprises a second gate located on a side of the second active layer away from the substrate; The second active layer is disposed in the same layer as the first active layer, and the second gate is disposed in the same layer as the first gate.

11. The array substrate according to claim 2, characterized in that: In a direction perpendicular to the base substrate, an end of the first via hole close to the base substrate does not overlap with an end of the second via hole close to the base substrate.

12. A method for preparing an array substrate, used for preparing the array substrate according to any one of claims 1 to 11, characterized in that: The array substrate includes a pixel circuit, the pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon: The preparation method comprises: providing a substrate base plate; Preparing a first active layer and a second active layer on one side of the substrate; Preparing a first type of inorganic layer on a side of the first active layer away from the substrate; performing a first heating process on the first active layer through the first type inorganic layer; Prepare a second type of inorganic layer on a side of the first type of inorganic layer away from the substrate; Prepare a first via hole, wherein the first via hole at least penetrates the second inorganic layer, and the vertical projection of the first active layer on the plane where the base substrate is located covers the vertical projection of one end of the first via hole close to the first active layer on the plane where the base substrate is located; A second heating process is performed on the first active layer through the first via hole, so that the hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer.

13. The preparation method according to claim 12, characterized in that: Preparing a first via hole, wherein the first via hole at least penetrates the second type inorganic layer, comprising: A first via hole is prepared, wherein the first via hole penetrates the second inorganic layer.

14. The preparation method according to claim 12, characterized in that: Preparing a first via hole, wherein the first via hole at least penetrates the second type inorganic layer, comprising: A first via hole is prepared, wherein the first via hole penetrates the second type inorganic layer and the first type inorganic layer.

15. The preparation method according to claim 12, characterized in that: The pixel circuit further includes a third transistor, the third transistor includes a third active layer, and the third active layer includes an oxide semiconductor; The preparation method further comprises: A third active layer is prepared on a side of the second inorganic layer away from the substrate.

16. The preparation method according to claim 15, characterized in that: The preparation method further comprises: A third inorganic layer is prepared on the side of the second inorganic layer away from the substrate, wherein the third inorganic layer includes multiple third inorganic layers, and the third inorganic layer close to the second inorganic layer covers the second inorganic layer and fills the first via hole.

17. The preparation method according to claim 16, characterized in that: The preparation method further comprises: A second via hole and a third via hole are prepared, wherein the second via hole and the third via hole both penetrate the first type inorganic layer, the second type inorganic layer and the third type inorganic layer; a vertical projection of the second via hole on the plane where the base substrate is located at least partially overlaps with a vertical projection of the first via hole on the base substrate, and a vertical projection of the second active layer on the base substrate covers a vertical projection of an end of the third via hole close to the second active layer on the plane where the base substrate is located; Prepare a fourth via hole, wherein the fourth via hole penetrates the third type inorganic layer on the side of the third active layer away from the base substrate, and the vertical projection of the third active layer on the base substrate covers the vertical projection of one end of the fourth via hole close to the third active layer on the plane where the base substrate is located; The first source and the first drain of the first transistor, the second source and the second drain of the second transistor, and the third source and the third drain of the third transistor are prepared on the side of the third inorganic layer away from the base substrate; the first source and the first drain are electrically connected to the first active layer through the second via; the second source and the second drain are electrically connected to the second active layer through the third via; the third source and the third drain are electrically connected to the third active layer through the fourth via.

18. The preparation method according to claim 17, characterized in that: A first active layer and a second active layer are prepared on one side of the substrate, comprising: Using the same mask process, a first active layer and a second active layer are prepared on one side of the base substrate, wherein the first active layer and the second active layer are arranged in the same layer; The preparation method further comprises: Using the same mask process, a first gate is prepared on a side of the first active layer away from the base substrate, and a second gate is prepared on a side of the second active layer away from the base substrate. The first gate and the second gate are arranged in the same layer.

19. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 11.

20. A display device, characterized in that: Comprising the display panel as claimed in claim 19.

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