Display panel, electronic device including the same, and method for manufacturing the display panel

Abstract

A display panel includes: a base substrate including a front surface and a rear surface, and including a hole area, an effective area surrounding the hole area, and a peripheral area adjacent to the effective area, wherein a through hole passing through the front surface and the rear surface and a groove portion surrounding the through hole and recessed from the front surface are defined in the hole area; a circuit layer including a first circuit insulating layer arranged on the base substrate, a second circuit insulating layer arranged on the first circuit insulating layer, and a thin film transistor arranged in the effective area; a display layer including a first display insulating layer arranged on the circuit layer, a second display insulating layer arranged on the first display insulating layer, and a light emitting device arranged in the effective area and connected to the thin film transistor; a guide pattern arranged on the circuit layer and disposed between the light emitting device and the groove portion; and an encapsulation layer covering the light emitting device and including a first inorganic layer, a second inorganic layer, and an organic layer, wherein the organic layer covers at least a portion of the guide pattern.

Description

Technical Field

[0001] The present invention relates to a display panel and a method for manufacturing the same, and more particularly, to a display panel having improved reliability and a method for manufacturing the same. Background Art

[0002] The organic light emitting display panel includes an organic light emitting element. The organic light emitting element is susceptible to moisture or oxygen and thus is easily damaged. Therefore, in the organic light emitting display panel, since moisture or oxygen introduced from the outside is stably blocked, the reliability and life of the organic light emitting display device can be improved. Summary of the invention

[0003] Technical issues

[0004] Therefore, an object of the present invention is to provide a display panel with improved process reliability and a method for manufacturing the display panel.

[0005] Technical Solution

[0006] A display panel according to an embodiment of the present invention includes: a base substrate having a front surface and a rear surface, and including a hole area, an effective area surrounding the hole area, and a peripheral area adjacent to the effective area, wherein a through hole passing through the front surface and the rear surface and a groove portion surrounding the through hole and recessed from the front surface are defined in the hole area; a circuit layer including a first circuit insulating layer arranged on the base substrate, a second circuit insulating layer arranged on the first circuit insulating layer, and a thin film transistor arranged in the effective area; a display layer including a first display insulating layer arranged on the circuit layer, a second display insulating layer arranged on the first display insulating layer, and a light-emitting element arranged in the effective area and connected to the thin film transistor; a guide pattern arranged on the circuit layer and between the light-emitting element and the groove portion; and an encapsulation layer covering the light-emitting element and including a first inorganic layer arranged in the effective area and the hole area, a second inorganic layer arranged on the first inorganic layer, and an organic layer arranged between the first inorganic layer and the second inorganic layer, wherein the organic layer covers at least a portion of the guide pattern.

[0007] The guide pattern may be a recessed pattern defined in at least one of the first display insulating layer and the second display insulating layer.

[0008] The guide pattern may pass through the second display insulating layer in a cross-section and be recessed from a top surface of the first display insulating layer.

[0009] The guide pattern may be defined in the second display insulating layer and spaced apart from the first display insulating layer.

[0010] The guide pattern may include: a first guide pattern defined in the second display insulating layer and recessed from a top surface of the second display insulating layer; and a second guide pattern defined in the first display insulating layer and recessed from a top surface of the first display insulating layer, wherein the first guide pattern and the second guide pattern may be spaced apart from each other when viewed on a plane.

[0011] The guide pattern may be a pattern disposed on the second circuit insulating layer and spaced apart from at least one of the first display insulating layer and the second display insulating layer when viewed on a plane.

[0012] The guide pattern may include the same material as at least one of the first display insulating layer and the second display insulating layer.

[0013] When viewed on a plane, the guide pattern may include a plurality of island patterns spaced apart from each other.

[0014] The island pattern may be arranged radially from the center of the through hole.

[0015] The island patterns can be arranged randomly.

[0016] When viewed on a plane, the guide pattern may have a closed line shape surrounding the groove portion.

[0017] The closed line shape may include a circular shape, an elliptical shape, and a polygonal shape.

[0018] The groove portion may have an undercut shape in cross section.

[0019] The groove portion may include: a first groove portion adjacent to the through hole; and a second groove portion disposed between the first groove portion and the guide pattern to surround the first groove portion, wherein each of an inner surface of the first groove portion and an inner surface of the second groove portion may be covered by a first inorganic layer.

[0020] When viewed on a plane, the organic layer may overlap the second groove portion and be spaced apart from the first groove portion.

[0021] The display panel may further include a filling pattern disposed at the first groove portion and spaced apart from the organic layer to be sealed by the first and second inorganic layers, wherein the filling pattern may include the same material as the organic layer.

[0022] When viewed on a plane, the organic layer may overlap the first groove portion and the second groove portion.

[0023] The display panel may further include a dam portion disposed between the groove portion and the through hole to surround the through hole, wherein the first inorganic layer may cover the dam portion.

[0024] An electronic device according to an embodiment of the present invention includes: a display panel, in which a through hole and a groove pattern are defined, the groove pattern is adjacent to the through hole and is configured to provide a predetermined recessed space; and an electronic module, which is configured to overlap with the through hole when viewed on a plane, wherein the display panel includes: a base substrate; a circuit layer, including a first circuit insulating layer arranged on the base substrate, a second circuit insulating layer arranged on the first circuit insulating layer, and a thin film transistor arranged in an effective area; a display layer, including a first display insulating layer arranged on the circuit layer, a second display insulating layer arranged on the first display insulating layer, and a light-emitting element arranged in the effective area and connected to the thin film transistor; a recessed pattern, which is arranged between the recessed pattern and the effective area and is defined in at least one of the first display insulating layer and the second display insulating layer; and an encapsulation layer, which covers the light-emitting element and includes a first inorganic layer arranged in the effective area and the hole area, a second inorganic layer arranged on the first inorganic layer, and an organic layer arranged between the first inorganic layer and the second inorganic layer, wherein at least a portion of the recessed pattern is filled with the organic layer.

[0025] The recessed pattern may be recessed from a top surface of the second display insulation layer.

[0026] The concave pattern may pass through the second display insulating layer and extend up to the first display insulating layer.

[0027] The recessed pattern may be recessed from a top surface of the first display insulating layer and spaced apart from the second display insulating layer when viewed on a plane.

[0028] The recessed pattern may be provided in plurality, each of the plurality of recessed patterns has an island shape, and the plurality of recessed patterns may be radially arranged from a center of the through hole.

[0029] The concave pattern may be provided in plurality, each of the plurality of concave patterns has an island shape, and the plurality of concave patterns may be randomly arranged.

[0030] The display panel may further include a dam portion disposed adjacent to the through hole, the groove pattern may include a first groove pattern and a second groove pattern, the first groove pattern being disposed between the through hole and the dam portion, the second groove pattern being disposed between the dam portion and the recessed pattern to surround the first groove pattern, and the second groove pattern may be filled with an organic layer.

[0031] The concave pattern may have a closed line shape surrounding the through hole.

[0032] A method for manufacturing a display panel according to an embodiment of the present invention includes: forming a circuit layer on a base substrate, the circuit layer including a first circuit insulating layer, a second circuit insulating layer and a thin film transistor, and when viewed on a plane, the base substrate is divided into a hole area and an effective area surrounding the hole area; forming a first initial display insulating layer and a second initial display insulating layer on the circuit layer; forming a groove portion at the base substrate; and patterning at least one of the first initial display insulating layer and the second initial display insulating layer to form a guide pattern.

[0033] The guide pattern and the groove portion are formed at the same time.

[0034] The method may also include forming a mask, the mask including a first opening portion exposing a portion of the hole area of ​​the base substrate and a second opening portion exposing a portion of the hole area of ​​the second initial display insulating layer, wherein a groove portion is formed by removing a portion of the area exposed by the first opening portion, and a guide pattern is formed by removing a portion of the area exposed by the second opening portion.

[0035] A second display insulating layer may be formed after forming the first display insulating layer, and forming the second display insulating layer may include: forming a first electrode connected to the thin film transistor on the first display insulating layer; forming an initial insulating layer covering the first electrode; and forming an opening at the initial insulating layer to expose at least a portion of the first electrode, and the guide pattern and the opening may be formed at the same time.

[0036] Beneficial Effects

[0037] According to the present invention, when forming an organic layer pattern of an encapsulation layer, diffusion of the organic layer can be controlled. Therefore, the region in which the organic layer pattern is formed can be easily controlled to simplify the process.

[0038] In addition, according to the present invention, since the guide pattern is formed in the existing process without adding a separate process, the process time can be reduced and the process cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a perspective view of an electronic device according to an embodiment of the present invention.

[0040] Figure 2a yes Figure 1 An exploded perspective view of an electronic device.

[0041] Figure 2b yes Figure 1 Block diagram of an electronic device.

[0042] Figure 3a It is shown Figure 2a A schematic equivalent circuit diagram of a portion of a component.

[0043] Figure 3b It is along Figure 2a A cross-sectional view taken along line II'.

[0044] Figure 4a and Figure 4b It is shown Figure 2a Floor plan of area XX'.

[0045] Figure 5a It is along Figure 2a A cross-sectional view taken along line II-II'.

[0046] Figure 5b It is shown Figure 5a A magnified view of a local area.

[0047] Figures 6a to 6c is a cross-sectional view showing a display panel according to an embodiment of the present invention.

[0048] Figure 7a and Figure 7b is a cross-sectional view showing a partial area of ​​an electronic panel according to an embodiment of the present invention.

[0049] Figures 8a to 8d is a schematic plan view showing a partial area of ​​a display panel according to an embodiment of the present invention.

[0050] Figures 9a to 9c is a cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention.

[0051] Figures 10a to 10i is a schematic cross-sectional view illustrating a method for manufacturing a display panel according to an embodiment of the present invention.

[0052] Figures 11a to 11f is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] Hereinafter, embodiments of the present invention for achieving the above-mentioned object will be described in detail with reference to the accompanying drawings.

[0054] The advantages and features of the present invention and the implementation method of the present invention will be explained by the following embodiments described with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In addition, the present invention is limited only by the scope of the claims. Throughout the disclosure, the same reference numerals refer to the same elements. In the accompanying drawings, a portion of the components is enlarged or reduced in proportion to clearly represent the various layers and regions. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view of an electronic device according to an embodiment of the present invention. Figure 2a yes Figure 1 An exploded perspective view of an electronic device. Figure 2b yes Figure 1 In the following, reference will be made to Figure 1 to Figure 2b An electronic device according to an embodiment of the present invention is described.

[0056] The electronic device EA may be a device activated according to an electrical signal. The electronic device EA may include various examples. For example, the electronic device EA may include a tablet computer, a laptop computer, a computer, a smart TV, etc. In this embodiment, an electronic device EA including a smart phone will be described as an example.

[0057] like Figure 1 As shown in , the electronic device EA may provide a display surface on which an image IM is displayed on its front surface. The display surface may be defined as a surface parallel to the surface defined by the first direction DR1 and the second direction DR2. The display surface may include a transmission area TA and a frame area BZA adjacent to the transmission area TA.

[0058] The image IM is displayed on the transmission area TA of the electronic device EA. Figure 1 An Internet search window is shown as an example of the image IM. The transmissive area TA may have a rectangular shape parallel to the first direction DR1 and the second direction DR2. However, this is only an example. For example, the electronic device EA may have various shapes and is not limited to any one embodiment.

[0059] The border area BZA is adjacent to the transmission area TA. The border area BZA may surround the transmission area TA. However, this is merely an example. For example, the border area BZA may be arranged to be adjacent to only one side of the transmission area TA, or the border area BZA may be omitted. The electronic device EA according to an embodiment of the present invention may include various embodiments, but is not limited to any one embodiment.

[0060] The normal direction of the display surface may correspond to the thickness direction of the electronic device EA (hereinafter referred to as the third direction). In this embodiment, the front surface (or top surface) or the rear surface (or bottom surface) of each of the components may be defined relative to the direction along which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3.

[0061] The directions indicated as the first direction to the third direction DR1, DR2 and DR3 may be relative concepts and thus may be changed to different directions. Hereinafter, the first direction to the third direction may be directions indicated by the first direction to the third direction DR1, DR2 and DR3, respectively, and respectively represented by the same reference numerals.

[0062] like Figure 2a As shown in FIG. 1 , the electronic device EA includes an electronic panel 100, a window member 200, an electronic module 300, and a receiving member 400. Figure 2b As shown in , the electronic device EA may further include an electronic panel 100, a first electronic module EM1, a second electronic module EM2 and a power module PM. Figure 2a In, omitted Figure 2b In the following, reference will be made to Figure 2a and Figure 2b Describe the electronic device EA.

[0063] The electronic panel 100 may display an image IM or sense an input applied from the outside. For example, the electronic panel 100 may include a display unit DPU that displays an image IM and an input sensing unit ISU that senses an external input.

[0064] The input sensing unit ISU senses an input applied from the outside. The external input includes various types of external inputs such as a part of a user's body, light, heat, pressure, etc. The external input may be an input applied to the window member 200 .

[0065] The display unit DPU and the input sensing unit ISU may be provided independently and may be physically combined with each other by a predetermined adhesive member. Alternatively, the display unit DPU and the input sensing unit ISU may be sequentially laminated on a single base substrate.

[0066] Optionally, in the electronic panel 100 according to the embodiment of the present invention, the input sensing unit ISU may be omitted. A case where the electronic panel 100 according to the embodiment (hereinafter, referred to as a display panel) includes a display unit DPU and omits the input sensing unit ISU will be exemplarily described.

[0067] Reference Figure 2a, the display panel 100 may include an active area DA, a peripheral area NDA, and a hole area PA divided on a plane. The active area DA may be an area in which an image IM is displayed. The display panel 100 includes a pixel PX disposed in the active area DA. The pixel PX may be provided in plurality and arranged in the active area DA. Light generated by the pixel PX realizes the image IM.

[0068] The peripheral area NDA may be an area covered by the frame area BZA. The peripheral area NDA is adjacent to the active area DA. The peripheral area NDA may surround the active area DA. A driving circuit or a driving line for driving the active area DA may be provided in the peripheral area NDA.

[0069] Although not shown, a portion of the peripheral area NDA of the display panel 100 may be curved. Therefore, a portion of the peripheral area NDA may face the front surface of the electronic device EA, and another portion of the peripheral area NDA may face the rear surface of the electronic device EA. Alternatively, in the display panel 100 according to an embodiment of the present invention, the peripheral area NDA may be omitted.

[0070] The hole area PA may be an area in which a module hole MH is defined. The display panel 100 according to an embodiment of the present invention may include at least one module hole MH.

[0071] The edge of the hole area PA may be surrounded by the active area DA. On a plane, the hole area PA may be spaced apart from the peripheral area NDA, and the active area DA is located between the hole area PA and the peripheral area NDA. The module hole MH may be defined in the hole area PA. Therefore, on a plane, the module hole MH may be surrounded by the active area DA in which the image IM is displayed.

[0072] The module hole MH passes through the display panel 100. The module hole MH may be a through hole connected from the front surface of the display panel 100 to the rear surface. The module hole MH may be in a cylindrical shape having a certain height in the third direction DR3. The module hole MH overlaps with the electronic module 300 on a plane. The electronic module 300 may be accommodated in the module hole MH, or may have a size similar to that of the module hole MH. A component disposed on the rear surface of the display panel 100 and overlapping with the module hole MH may be visible through the module hole MH at the front surface of the display panel 100. The electronic module 300 may receive an external input through the module hole MH. The electronic module 300 will be described in more detail below.

[0073] The window member 200 is disposed on the front surface of the electronic device EA. The window member 200 may be disposed on the front surface of the display panel 100 to protect the display panel 100. For example, the window member 200 may include a glass substrate, a sapphire substrate, or a plastic film. The window member 200 may have a single-layer or multi-layer structure. For example, the window member 200 may have a laminated structure of a plurality of plastic films bonded to each other using an adhesive or a laminated structure of a glass substrate and a plastic film bonded to each other using an adhesive.

[0074] The window member 200 may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area through which incident light is transmitted. The transmission area TA may have a shape corresponding to the shape of the active area DA. For example, the transmission area TA overlaps the entire surface or at least a portion of the active area DA. The image IM displayed in the active area DA of the display panel 100 may be visible from the outside through the transmission area TA.

[0075] The bezel area BZA may be an area having a light transmittance relatively smaller than that of the transmission area TA. The bezel area BZA defines the shape of the transmission area TA. The bezel area BZA may be disposed adjacent to the transmission area TA and surround the transmission area TA.

[0076] The frame area BZA may have a predetermined color. The frame area BZA may cover the peripheral area NDA of the display panel 100 to prevent the peripheral area NDA from being visible from the outside. However, this is only an example. For example, in the window member 200 according to an embodiment of the present invention, the frame area BZA may be omitted.

[0077] The receiving member 400 may be coupled to the window member 200. The receiving member 400 may be disposed on the rear surface of the electronic device EA. The receiving member 400 is coupled to the window member 200 to define an internal space.

[0078] The receiving member 400 may include a material having relatively high rigidity. For example, the receiving member 400 may include a plurality of frames and / or plates made of glass, plastic, and metal. The receiving member 400 may stably protect the components of the electronic device EA received in the internal space from external impact. Figure 2b The display panel 100 and various components may be received in an inner space provided by the receiving member 400 .

[0079] Reference Figure 2b , the electronic device EA may include a power module PM, a first electronic module EM1 and a second electronic module EM2. The power module PM supplies power required for the overall operation of the electronic device EA. The power module PM may include a general battery module.

[0080] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for driving the electronic device EA. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the display panel 100, or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

[0081] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM and an external interface IF. Some of the modules may not be mounted on the motherboard but may be electrically connected to the motherboard through a flexible circuit board.

[0082] The control module CM controls the overall operation of the electronic device EA. The control module CM may be a microprocessor. For example, the control module CM may activate or deactivate the display panel 100. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on a touch signal received from the display panel 100.

[0083] The wireless communication module TM can send / receive wireless signals to / from another terminal by using a Bluetooth or Wi-Fi line. The wireless communication module TM can send / receive audio signals by using a general communication line. The wireless communication module TM includes a transmitter TM1 that modulates and sends a signal to be sent and a receiver TM2 that demodulates a received signal.

[0084] The image input module IIM processes the image signal to convert the processed image signal into image data displayable on the display panel 100. The audio input module AIM receives an external audio signal by using a microphone during a recording mode or a voice recognition mode to convert the received audio signal into electrical sound data.

[0085] The external interface IF serves as an interface to an external charger, a wired / wireless data port, and a card (eg, a memory card and a SIM / UIM card) slot.

[0086] The second electronic module EM2 may include an audio output module AOM, a light transmitting module LM, a light receiving module LRM, and a camera module CMM. The above components may be directly mounted on a motherboard, may be mounted on a separate board and electrically connected to the display panel 100 through a connector (not shown), or may be electrically connected to the first electronic module EM1.

[0087] The audio output module AOM converts audio data received from the wireless communication module TM or audio data stored in the memory MM to output the converted audio data to the outside.

[0088] The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED. The light receiving module LRM may sense infrared rays. The light receiving module LRM may be activated when infrared rays having a predetermined level or higher are sensed. The light receiving module LRM may include a CMOS sensor. Infrared rays generated in the light emitting module LM may be output and then reflected by an external object (e.g., a user's finger or face), and the reflected infrared rays may be incident into the light receiving module LRM. The camera module CMM captures external images.

[0089] Figure 2a The electronic module 300 may receive an external input transmitted through the module hole MH or provide an output through the module hole MH. The electronic module 300 may be one of the modules constituting the first electronic module EM1 and the second electronic module EM2. For example, the electronic module 300 may be a camera, a speaker, or a sensor for sensing light or heat. The electronic module 300 may sense an external object received through the module hole MH, or provide a sound signal such as voice to the outside through the module hole MH. Here, the remaining components of the first electronic module EM1 and the second electronic module EM2 may be arranged at different positions, and therefore may not be shown. However, this is merely an example. The electronic module 300 may include a plurality of modules among the modules constituting the first electronic module EM1 and the second electronic module EM2, but is not limited to any one embodiment. Although not shown, the electronic device EA according to an embodiment of the present invention may further include a transparent member disposed between the electronic module 300 and the display panel 100. The transparent member may be an optically transparent film so that the external input transmitted through the module hole MH passes through the transparent member and is transmitted to the electronic module 300. The transparent member may be attached to the rear surface of the display panel 100, or may be disposed between the display panel 100 and the electronic module 300 without an adhesive layer. The electronic device EA according to the embodiment of the present invention may have various shapes, but is not limited to any one embodiment.

[0090] In the present invention, the display panel 100 may include a module hole MH. Therefore, a separate space provided for the electronic module 300 in the peripheral area NDA may be omitted. In addition, the module hole MH may be defined in the hole area PA surrounded by the active area DA, so that the electronic module 300 is arranged to overlap with the transmissive area TA, but not with the frame area BZA. Therefore, the area of ​​the frame area BZA may be reduced to realize an electronic device EA with a narrow frame. In addition, when the electronic module 300 is accommodated in the module hole MH, a compact electronic device EA may be realized.

[0091] Figure 3a It is shown Figure 2a A schematic equivalent circuit diagram of a portion of a component. Figure 3b It is along Figure 2a A cross-sectional view taken along line I-I'. Figure 3a In order to facilitate the description, an equivalent circuit diagram of a pixel PX is briefly shown. Figure 3a and Figure 3b The present invention is described.

[0092] The display panel 100 may include an insulating substrate 10, pixels PX, a plurality of lines (eg, driving signal lines) CL, a power connection pattern E-VSS, a peripheral dam portion DM, and a plurality of insulating layers 20, 30, and 40. The insulating layers 20, 30, and 40 may include a circuit insulating layer 20, a display insulating layer 30, and an encapsulation layer 40.

[0093] The insulating substrate 10 may include a base layer 11 and an auxiliary layer 12. The base layer 11 includes an insulating material. The base layer 11 may include a flexible material. For example, the base layer 11 may include polyimide (PI). However, this is only an example. For example, the base layer 11 may include a rigid material, or may be made of various materials such as glass and plastic, but is not limited to any one embodiment.

[0094] The auxiliary layer 12 is disposed on the base layer 11. The auxiliary layer 12 may completely cover the base layer 11.

[0095] The auxiliary layer 12 may include a barrier layer and / or a buffer layer. Therefore, the auxiliary layer 12 may reduce the surface energy of the insulating substrate 10, thereby preventing oxygen or moisture introduced through the base layer 11 from penetrating into the pixel PX or stably forming the pixel PX on the insulating substrate 10.

[0096] In the insulating substrate 10, at least one of the base layer 11 and the auxiliary layer 12 may be provided in multiple and alternately laminated. Optionally, at least one of the barrier layer and the buffer layer constituting the auxiliary layer 12 may be provided in multiple or may be omitted. However, this is only an example. For example, the insulating substrate 10 according to an embodiment of the present invention may include various embodiments, but is not limited to any one embodiment.

[0097] The pixel PX may be disposed on the insulating substrate 10. As described above, the pixel PX may be disposed in the active area DA of the insulating substrate 10. Figure 3a , the pixel PX can be connected to a plurality of signal lines. In the present embodiment, the gate line GL, the data line DL and the power line VDD in the signal line are shown as examples. However, this is only an example. For example, the pixel PX according to the embodiment of the present invention can be connected to various signal lines in addition, but is not limited to any one embodiment.

[0098] The pixel PX may include a first thin film transistor TR1, a capacitor CAP, a second thin film transistor TR2, and a light emitting element OD. The first thin film transistor TR1 may be a switching element that controls turning on / off of the pixel PX. The first thin film transistor TR1 may transmit or block a data signal transmitted through the data line DL in response to a gate signal transmitted through the gate line GL.

[0099] The capacitor CAP is connected to the first thin film transistor TR1 and the power line VDD. The capacitor CAP is charged with electric charges of an amount corresponding to a difference between a data signal received from the first thin film transistor TR1 and a first power voltage applied to the first power line VDD.

[0100] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CAP and the light emitting element OD. The second thin film transistor TR2 controls the driving current flowing through the light emitting element OD in response to the amount of charge stored in the capacitor CAP. The on time of the second thin film transistor TR2 can be determined according to the amount of charge charged in the capacitor CAP. The second thin film transistor TR2 provides the first power voltage transmitted through the power line VDD to the light emitting element OD during the on time.

[0101] The light emitting element OD connects the second thin film transistor TR2 to the power terminal VSS. The light emitting element OD emits light at a voltage corresponding to the difference between the signal transmitted through the second thin film transistor TR2 and the second power voltage received through the power terminal VSS. The light emitting element OD can emit light during the on time of the second thin film transistor TR2.

[0102] The light emitting element OD includes a light emitting material. The light emitting element OD may generate light having a color corresponding to the light emitting material. The color of the light generated in the light emitting element OD may have one of red, green, blue, and white.

[0103] Figure 3b 2 shows an example of a thin film transistor TR and a light emitting element OD in components of a pixel PX. The thin film transistor TR may correspond to Figure 3a The second thin film transistor TR2.

[0104] The thin film transistor TR is disposed on the insulating substrate 10. The thin film transistor TR may constitute a circuit layer together with the circuit insulating layer 20. The thin film transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The circuit insulating layer 20 may include a first circuit insulating layer 21 and a second circuit insulating layer 22 sequentially laminated on the insulating substrate 10.

[0105] The semiconductor pattern SP is disposed on the insulating substrate 10. The semiconductor pattern SP may include a semiconductor material. The control electrode CE is spaced apart from the semiconductor pattern SP, and the first circuit insulating layer 21 is located between the control electrode CE and the semiconductor pattern SP. The control electrode CE may be connected to one electrode of each of the first thin film transistor TR1 and the capacitor CAP as described above.

[0106] The input electrode IE and the output electrode OE may be spaced apart from the control electrode CE, and the second circuit insulating layer 22 is located between the input electrode IE and the output electrode OE and the control electrode CE. The input electrode IE and the output electrode OE of the thin film transistor TR are connected to one side and the other side of the semiconductor pattern SP respectively by passing through the first circuit insulating layer 21 and the second circuit insulating layer 22.

[0107] In the thin film transistor TR, the control electrode CE may be disposed under the semiconductor pattern SP, and the input electrode IE and the output electrode OE may be disposed under the semiconductor pattern SP, or may be disposed on the same layer as the semiconductor pattern SP to be directly connected to the semiconductor pattern SP. The thin film transistor TR according to an embodiment of the present invention may have various structures, but is not limited to any one embodiment.

[0108] The light emitting element OD is disposed on the circuit insulating layer 20. The light emitting element OD may constitute a display element layer together with the display insulating layer 30. The light emitting element OD includes a first electrode E1, an emission layer EL, a control layer OL, and a second electrode E2. The display insulating layer 30 may include a first display insulating layer 31 and a second display insulating layer 32 sequentially laminated. Each of the first display insulating layer 31 and the second display insulating layer 32 may include an organic material and / or an inorganic material.

[0109] The first electrode E1 may be connected to the thin film transistor TR by passing through the first display insulating layer 31. Although not shown, the display panel 100 may further include a separate connection electrode disposed between the first electrode E1 and the thin film transistor TR. In this case, the first electrode E1 may be electrically connected to the thin film transistor TR through the connection electrode.

[0110] The second display insulating layer 32 is disposed on the first display insulating layer 31. An opening may be defined in the second display insulating layer 32. The opening may expose at least a portion of the first electrode E1. The second display insulating layer 32 may be a pixel defining layer.

[0111] The emission layer EL may be disposed in the opening and on the first electrode E1 exposed by the opening. The emission layer EL may include a light-emitting material. For example, the emission layer EL may be made of at least one of materials emitting light having red, green and blue colors, and include a fluorescent material or a phosphorescent material. In addition, the emission layer EL may include an organic material and / or an inorganic material. The emission layer EL may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0112] The control layer OL is disposed between the first electrode E1 and the second electrode E2. The control layer OL is disposed adjacent to the emission layer EL. In the present embodiment, the control layer OL is shown as being disposed between the emission layer EL and the second electrode E2. However, this is merely an example. For example, the control layer OL may be disposed between the emission layer EL and the first electrode E1, or may be disposed as a plurality of layers laminated in the third direction DR3 with the emission layer EL therebetween.

[0113] The control layer OL may have an integral shape extending from the active area DA to the peripheral area NDA. The control layer OL may be provided in common to a plurality of pixels.

[0114] The second electrode E2 is disposed on the emission layer EL. The second electrode E2 may have an integral shape extending from the active area DA to the peripheral area NDA. The second electrode E2 may be commonly disposed for a plurality of pixels.

[0115] The second electrode E2 may face the first electrode E1. The second electrode E2 may be connected to Figure 2a The light emitting element OD receives the second power voltage through the second electrode E2.

[0116] The second electrode E2 may include a transmissive conductive material or a transflective conductive material. Therefore, the light generated in the emission layer EL can be easily emitted along the third direction DR3 through the second electrode E2. However, this is only an example. For example, the light emitting element OD according to an embodiment of the present invention may be driven in a bottom emission mode including a transmissive or semi-transmissive material, or may be driven in a double-sided emission mode in which light is emitted from all surfaces of the front surface and the rear surface, but is not limited to any one embodiment.

[0117] The encapsulation layer 40 may be disposed on the light emitting element OD to encapsulate the light emitting element OD. The encapsulation layer 40 may have an integral shape extending from the active area DA to the peripheral area NDA. The encapsulation layer 40 may be provided in common for a plurality of pixels. Although not shown, a cap layer covering the second electrode E2 may also be provided between the second electrode E2 and the encapsulation layer 40.

[0118] The encapsulation layer 40 may include a first inorganic layer 41, an organic layer 42, and a second inorganic layer 43 sequentially laminated in the third direction DR3. However, the embodiments of the present invention are not limited thereto. For example, the encapsulation layer 40 may also include a plurality of inorganic layers and organic layers.

[0119] The first inorganic layer 41 may cover the second electrode E2. The first inorganic layer 41 may prevent external moisture or oxygen from penetrating into the light emitting element OD. For example, the first inorganic layer 41 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 41 may be formed by a deposition process.

[0120] The organic layer 42 may be disposed on the first inorganic layer 41 to contact the first inorganic layer 41. The organic layer 42 may provide a flat surface on the first inorganic layer 41. A curved surface disposed on the top surface of the first inorganic layer 41 or particles present on the first inorganic layer 41 may be covered by the organic layer 42 to prevent the surface state of the top surface of the first inorganic layer 41 from affecting components disposed on the organic layer 42. In addition, the organic layer 42 may reduce stress between layers in contact with each other. The organic layer 42 may include an organic material and may be formed by a solution process such as spin coating, slit coating, an inkjet process, or the like.

[0121] The second inorganic layer 43 may be disposed on the organic layer 42 to cover the organic layer 42. When compared with when the second inorganic layer 43 is directly disposed on the first inorganic layer 41, the second inorganic layer 43 may be relatively stably formed on a flat surface provided by the organic layer 42. The second inorganic layer 43 may encapsulate moisture discharged from the organic layer 42 to prevent moisture from being introduced to the outside. The second inorganic layer 43 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 43 may be formed by a deposition process.

[0122] Although not shown, the input sensing unit ISU (see Figure 2b ) may also be disposed on the encapsulation layer 40. The sensor pattern constituting the input sensing unit ISU may be directly formed on the encapsulation layer 40 through a deposition and patterning process, or may be formed separately and then bonded to the encapsulation layer 40. However, this is merely an example. For example, the display panel 100 according to an embodiment of the present invention may include various embodiments, but is not limited to any one embodiment.

[0123] The drive signal line CL, the peripheral dam portion DM, and the power connection pattern E-VSS may be disposed in the peripheral area NDA. The drive signal line CL may be disposed in plurality and disposed on the circuit insulation layer 20. The drive signal line CL may be a wiring connected to a pad (or referred to as a "pad" or "pad") (not shown) or a line constituting an integrated circuit IC. For example, the drive signal line CL may include a power line, an initialization voltage line, or an emission control line.

[0124] The power connection pattern E-VSS supplies the second power voltage to the light emitting element OD. The power connection pattern E-VSS may correspond to the power terminal VSS of the pixel PX. The second electrode E2 extends until the peripheral area NDA and is connected to the power connection pattern E-VSS. In the present embodiment, the second power voltage supplied to the pixel PX may be a common voltage relative to all pixels PX.

[0125] The peripheral dam portion DM may be disposed at a position covering a portion of the power connection pattern E-VSS. In the present embodiment, the peripheral dam portion DM may have a multi-layered structure including a first dam DM1 and a second dam DM2.

[0126] The first dam DM1 may include the same material as that of the first display insulating layer 31. The first dam DM1 may be formed simultaneously with the first display insulating layer 31, and may be disposed on the same layer as the first display insulating layer 31.

[0127] The second dam DM2 is laminated on the first dam DM1. In the present embodiment, a portion of the second electrode E2 may be interposed between the first dam DM1 and the second dam DM2. That is, the second dam DM2 according to the present embodiment may be formed by a separate process after forming the second electrode E2. This is merely an example. For example, the second dam DM2 may be formed simultaneously with the second display insulating layer 32. Alternatively, the peripheral dam portion DM may have a single-layer structure and is not limited to any one embodiment.

[0128] The peripheral dam portion DM may be disposed adjacent to at least one side of the active area DA. The peripheral dam portion DM may surround the active area DA on a plane. The peripheral dam portion DM may be defined as a region into which the liquid organic material diffuses during the formation of the organic layer 42. The organic layer 42 may be formed in an inkjet manner in which the liquid organic material is applied to the first inorganic layer 41. Here, the peripheral dam portion DM may set a boundary of a region in which the liquid organic material is disposed and prevent the liquid organic material from overflowing to the outside of the peripheral dam portion DM.

[0129] The first inorganic layer 41 and the second inorganic layer 43 may extend from the active area DA to the outside of the peripheral dam portion DM. Therefore, the peripheral dam portion DM may be covered by the first inorganic layer 41 and the second inorganic layer 43. The organic layer 42 may be disposed inside the peripheral dam portion DM. However, this is merely an example. For example, a portion of the organic layer 42 may extend to a region overlapping the peripheral dam portion DM, but is not limited to any one embodiment.

[0130] Figure 4a and Figure 4b It is shown Figure 2a For ease of description, Figure 4a and Figure 4b Some components are omitted. When compared with each other Figure 4a and Figure 4b When Figure 4a The guide pattern GPT and the organic layer 42 are omitted, and Figure 4b The signal lines are omitted in the following. Figure 4a and Figure 4b Describe the present invention. Figures 1 to 3b The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0131] The hole area PA may be surrounded by the active area DA. The hole area PA may include a groove area GA and a line area LA. The module hole MH may be defined in the center of the hole area PA. Each of the line area LA and the groove area GA may surround the module hole MH. The line area LA and the groove area GA may be sequentially arranged from the active area DA in a direction toward the module hole MH. Specifically, the groove area GA may be defined as an annular shape surrounding the module hole MH, and the line area LA may be defined as an annular shape surrounding the groove area GA.

[0132] The display panel 100 according to the embodiment may include a plurality of signal lines SCL1 and SCL2 disposed in the hole area PA, a groove pattern GV, and a guide pattern GPT.

[0133] The signal lines SCL1 and SCL2 are connected to the pixels PX-A1, PX-A2, PX-B1, and PX-B2 via the line area LA. In the present embodiment, for the convenience of description, two signal lines SCL1 and SCL2 and four pixels PX-A1, PX-A2, PX-B1, and PX-B2 connected to the two signal lines SCL1 and SCL2 are exemplarily shown. Hereinafter, the two signal lines SCL1 and SCL2 are referred to as the first signal line SCL1 and the second signal line SCL2, and the four pixels PX-A1, PX-A2, PX-B1, and PX-B2 will be referred to as the first pixel to the fourth pixel PX-A1, PX-A2, PX-B1, and PX-B2.

[0134] The first signal line SCL1 is connected to each of the first pixel PX-A1 and the second pixel PX-A2 spaced apart from each other, and the hole area PA is located between the first pixel PX-A1 and the second pixel PX-A2. The first pixel PX-A1 and the second pixel PX-A2 may be pixels constituting the same row. The first signal line SCL1 connected to the first pixel PX-A1 is connected to the second pixel PX-A2 through the line area LA of the hole area PA.

[0135] The first pixel PX-A1 and the second pixel PX-A2 are connected through the first signal line SCL1 to receive the same electrical signal. For example, the first signal line SCL1 may correspond to Figure 3a The gate line GL shown in FIG. Figure 3a ). Therefore, the first pixel PX-A1 and the second pixel PX-A2, which are spaced apart from each other with the module hole MH located therebetween, may be turned on / off by substantially the same gate signal.

[0136] The second signal line SCL2 is connected to each of the third pixel PX-B1 and the fourth pixel PX-B2 spaced apart from each other, and the hole area PA is located between the third pixel PX-B1 and the fourth pixel PX-B2. The third pixel PX-B1 and the fourth pixel PX-B2 may be pixels constituting the same column. The second signal line SCL2 connected to the third pixel PX-B1 is connected to the fourth pixel PX-B2 via the line area LA of the hole area PA.

[0137] The third pixel PX-B1 and the fourth pixel PX-B2 are connected through the second signal line SCL2 to receive the same electrical signal. For example, the second signal line SCL2 may correspond to Figure 3a The data line DL shown in Figure 3a ). Therefore, the third pixel PX-B1 and the fourth pixel PX-B2, which are spaced apart from each other with the module hole MH located therebetween, may receive substantially the same data signal.

[0138] In the present embodiment, the first signal line SCL1 and the second signal line SCL2 may be patterns disposed only in the line area LA. Here, each of the first signal line SCL1 and the second signal line SCL2 may be used as a bridge pattern, and the bridge pattern is connected to the signal lines respectively connected to the pixels PX-A1, PX-A2, PX-B1, and PX-B2 to connect the signal lines to each other. However, this is merely an example. For example, the display panel 100 according to an embodiment of the present invention includes a plurality of signal lines disposed in the line area LA to improve the organic combination between the pixels spaced apart from each other relative to the module hole MH. Therefore, it is possible to facilitate the electrical control of the pixels spaced apart from each other relative to the module hole MH.

[0139] The groove pattern GV may be provided in the groove area GA. The groove pattern GV may be a pattern recessed from the front surface of the display panel 100. The groove pattern GV may be provided by removing a portion of a component of the display panel 100 to be recessed from the front surface of the display panel 100. This will be described in detail later.

[0140] Unlike the module hole MH, the groove pattern GV may not penetrate the display panel 100. Therefore, the groove pattern GV may not open at least the rear surface of the insulation substrate 10.

[0141] The groove pattern GV may surround the module hole MH. The groove pattern GV may have a closed line shape surrounding the module hole MH. In the present embodiment, the groove pattern GV is shown in the shape of a circular closed line. However, this is only an example. For example, the groove pattern GV may have various closed line shapes, such as a polygonal shape or an elliptical shape, but is not limited to any one embodiment.

[0142] When viewed on a plane, the guide pattern GPT may be disposed between the pixels PX-A1, PX-A2, PX-B1, and PX-B2 and the groove pattern GV. For example, the guide pattern GPT may be disposed in the line area LA. The guide pattern GPT may include a plurality of pattern GPTs spaced apart from each other. The pattern GPTs may be radially arranged around the module hole MH. In the present embodiment, the pattern GPTs are shown as being arranged four by four in a direction from the center of the module hole MH toward the active area DA. However, this is merely an example. For example, the pattern GPTs may be arranged in various numbers and are not limited to any one embodiment.

[0143] The guide pattern GPT improves the uniformity of diffusion of the organic layer 42. Figure 4b In the embodiment, the organic layer 42 is shaded for ease of description. In the present embodiment, the organic layer 42 is shown as being disposed in the line area LA. However, this is merely an example. For example, the organic layer 42 may be disposed to extend up to the groove area GA, but is not limited to any one embodiment.

[0144] The organic layer 42 covers the guide pattern GPT. When viewed on a plane, the organic layer 42 and the guide pattern GPT may overlap each other. The organic layer 42 may be disposed to have a uniform thickness in the hole area PA by the guide pattern GPT. In addition, the area in the hole area PA in which the organic layer 42 is disposed may be uniformly distributed by the guide pattern GPT.

[0145] According to the present invention, since the organic layer 42 is uniformly diffused in the hole area PA, the area occupied by the organic layer 42 in the hole area PA can be easily designed. In addition, due to the uniform coating of the organic layer 42 in the hole area PA, especially in the line area LA where the guide pattern GPT is disposed, the organic layer 42 can be prevented from excessively overflowing to the groove area GA via the line area LA. Therefore, the organic layer 42 can be stably disposed in the hole area PA, especially in the line area LA.

[0146] Figure 5a It is along Figure 2a A cross-sectional view taken along line II-II', and Figure 5b It is shown Figure 5a For the sake of illustration, Figure 5a and Figure 5bIn the following, we will refer to Figure 5a and Figure 5b The present invention is described.

[0147] like Figure 5a As shown in FIG. 1 , the module hole MH is spaced apart from the pixel PX disposed in the active area DA and is disposed in the hole area PA. The module hole MH may be defined at the center of the hole area PA. The module hole MH may be a through hole penetrating the display panel 100. The module hole MH penetrates a component disposed in the hole area PA among components of the display panel 100.

[0148] Specifically, the module hole MH is formed by penetrating the base layer 11, the auxiliary layer 12, the first circuit insulating layer 21, the second circuit insulating layer 22, the control layer OL, the second electrode E2, the first inorganic layer 41, and the second inorganic layer 43. Therefore, the inner surface MH-IS of the module hole MH may be defined by the cross section 11-E of the base layer 11, the cross section 12-E of the auxiliary layer 12, the cross section 21-E of the first insulating layer 21, the cross section 22-E of the second insulating layer 22, the cross section OL-E of the control layer OL, the cross section E2-E of the second electrode E2, the cross section 41-E of the first inorganic layer 41, and the cross section 43-E of the second inorganic layer 43.

[0149] In the present embodiment, the groove pattern GV may be defined in the groove area GA surrounding the module hole MH, and the guide pattern GPT may be defined in the line area LA surrounding the groove pattern GV. Figure 5b The groove pattern GV and the guide pattern GPT are described in detail.

[0150] The groove pattern GV may be disposed to correspond to the groove portion HM of the insulating substrate 10. The groove pattern GV may have a position corresponding to the groove portion HM in a plane and have a certain shape in a cross section. That is, the predetermined recessed space provided by the groove pattern GV may be similar in position and shape to the recessed space provided by the groove portion HM.

[0151] The groove pattern GV may be provided by covering the inner surface of the groove portion HM by at least one of the first inorganic layer 41 and the second inorganic layer 43. The portion of the first inorganic layer 41 or the second inorganic layer 43 covering the inner surface of the groove portion HM may be recessed than the portion covering the periphery of the groove portion HM to provide a groove pattern GV having a predetermined recessed space. The first inorganic layer 41 covers the inner surface of the groove portion HM and defines the inner surface of the groove pattern GV. Therefore, the inner surface of the groove pattern GV may have a shape corresponding to the shape of the inner surface of the groove portion HM. In the present embodiment, the groove pattern GV is shown as the groove portion HM covered by the first inorganic layer 41 and the second inorganic layer 43.

[0152] The groove portion HM may be provided by passing through the remaining components except only a portion of the base layer 11 of the insulating substrate 10. The groove portion HM may include a first portion H1 disposed in the auxiliary layer 12 and a second portion H2 disposed in the base layer 11.

[0153] The first portion H1 may be a through hole passing through the auxiliary layer 12. The first portion H1 may define an entrance portion of the groove portion HM. The second portion H2 may be a recessed pattern provided by removing a portion of the base layer 11. The second portion H2 is provided to be recessed from the top surface of the base layer 11. The top surface of the base layer 11 may be a surface in contact with the auxiliary layer 12. This is merely an example. For example, the shape or depth of the groove portion HM may vary according to the layer configuration of the insulating substrate 10, but is not limited to any one embodiment.

[0154] In the present embodiment, the base layer 11 may be disposed by being relatively undercut with respect to the auxiliary layer 12. Therefore, the groove portion HM may have an undercut shape so that the end of the auxiliary layer 12 defines a tip portion TP protruding toward the inside of the groove portion HM. Specifically, the width of the first portion H1 may be smaller than the width of the upper side of the second portion H2. When viewed from a plane, the tip portion TP defining the first portion H1 of the auxiliary layer 12 may overlap with the second portion H2. As long as the tip portion TP is disposed in the groove portion HM, the display panel 100 according to an embodiment of the present invention may have various layer structures, but is not limited to any one embodiment.

[0155] The first inorganic layer 41 covers the inner surface of the groove portion HM. Specifically, the first inorganic layer 41 covers the inner side of the first portion H1 and the inner side of the second portion H2 constituting the groove portion HM. The second inorganic layer 43 is disposed along the first inorganic layer 41. Therefore, the tip portion TP may provide the groove pattern GV while being covered by the first inorganic layer 41 and the second inorganic layer 43.

[0156] The organic layer 42 is disposed on the light emitting element OD. In the present embodiment, the organic layer 42 may be spaced apart from the groove pattern GV. The organic layer 42 may be disposed on the guide pattern GPT and sealed by the first inorganic layer 41 and the second inorganic layer 43. Therefore, the spacing distance between the organic layer 42 and the module hole MH (which may become a moving path for external contaminants / moisture to penetrate from the module hole MH) may be increased to prevent the display panel 100 from being damaged by external contaminants, thereby improving the process reliability of the display panel 100.

[0157] Alternatively, although not shown, the organic layer 42 according to an embodiment of the present invention may extend up to the groove area GA in which the groove pattern GV is disposed to fill at least a portion of the groove pattern GV. The organic layer 42 may support the tip portion TP by filling the inside of the groove pattern GV. Therefore, damage to the tip portion TP due to the protruding shape of the tip portion TP may be prevented to improve the durability of the display panel 100. The display panel 100 according to an embodiment of the present invention may include various embodiments, but is not limited to one embodiment.

[0158] In the present embodiment, the control layer OL and the second electrode E2 may be formed after removing a portion of the auxiliary layer 12 and the first circuit insulating layer 21. The control layer OL and the second electrode E2 may be provided by a deposition process. Therefore, the control layer OL and the second electrode E2 may cover the cross section of the auxiliary layer 12 exposed by the first portion H1 of the groove portion HM. Thereafter, the control layer OL and the second electrode E2 may be covered by the first inorganic layer 41.

[0159] The display panel 100 may further include a predetermined additional organic pattern OL-P disposed in the groove portion HM. The additional organic pattern OL-P may include the same material as that of at least one of the control layer OL and the second electrode E2. The additional organic pattern OL-P may be spaced apart from the control layer OL and the second electrode E2 and disposed in the groove portion HM, and may also be covered by the first inorganic layer 41 so as not to be exposed to the outside.

[0160] When viewed on a plane, the guide pattern GPT may be disposed between the light emitting element OD and the groove pattern GV. The guide pattern GPT may be a recessed pattern defined in at least one of the first display insulating layer 31 and the second display insulating layer 32 .

[0161] The guide pattern GPT may have a depth defined by passing through the second display insulating layer 32 and removing at least a portion of the first display insulating layer 31. The guide pattern GPT may have a shape passing through the second display insulating layer 32 and recessed from a top surface of the first display insulating layer 31 when viewed in cross section.

[0162] The guide pattern GPT may be composed of pattern GPTs, each of which is recessed from the top surface of the second display insulating layer 32. In the present embodiment, the pattern GPTs are shown as recessed patterns having the same width and the same depth. However, this is merely an example. For example, the width or depth of the pattern GPTs may be different from each other according to process error or process design, but is not limited to any one embodiment.

[0163] In this embodiment, the control layer OL, the second electrode E2 and the first inorganic layer 41 may be disposed along the inner surface of each of the patterns GPTs. Therefore, even when the control layer OL, the second electrode E2 and the first inorganic layer 41 are disposed, the concave shape of the guide pattern GPT may be stably maintained.

[0164] The organic layer 42 according to the present embodiment can be formed by applying a liquid organic material to the active area DA by a solution process such as a screen printing process or an inkjet process. The liquid organic material having a predetermined diffusion property can gradually diffuse from the center of the active area DA toward the hole area PA. When the liquid organic material covers the guide pattern GPT, the concave shape of the guide pattern GPT can be partially filled. The flow rate or diffusibility of the liquid organic material can be controlled by the guide pattern GPT. Therefore, the organic layer 42 can be formed with uniform diffusibility within the line area LA by the guide pattern GPT.

[0165] The display panel 100 according to the present embodiment may further include a spacer SPS. The spacer SPS may protrude from the top surface of the second display insulating layer 32. The spacer SPS may be independent of the second display insulating layer 32 and may be disposed between the second display insulating layer 32 and the control layer OL, or may be integrated with the second display insulating layer 32. The spacer SPS may include an insulating material. The spacer SPS may support a mask to prevent a mask for forming the emission layer EL from contacting the second display insulating layer 32. However, this is merely an example. In the display panel 100 according to an embodiment of the present invention, the spacer SPS may be omitted. The display device 100 according to an embodiment of the present invention may have various shapes, but is not limited to any one embodiment.

[0166] Figures 6a to 6c is a cross-sectional view showing a display panel according to an embodiment of the present invention. Figure 5b The area corresponding to the area shown in . In the following, reference will be made to Figures 6a to 6c The present disclosure is described.

[0167] like Figure 6a As shown in FIG. 1 , the guide pattern GPT- 1 may be a recessed pattern defined in the second display insulating layer 32 . The guide pattern GPT- 1 has a shape recessed from a top surface of the second display insulating layer 32 .

[0168] The guide pattern GPT-1 may have a depth defined by removing a portion of the second display insulating layer 32 without reaching the first display insulating layer 31. The guide pattern GPT-1 may have a shape recessed from a top surface of the second display insulating layer 32 and spaced apart from the first display insulating layer 31 when viewed in cross section.

[0169] Alternatively, if Figure 6bAs shown in , the guide pattern GPT-2 may be a recessed pattern defined in the first display insulating layer 31. The guide pattern GPT-2 has a shape recessed from the top surface of the first display insulating layer 31. The guide pattern GPT-2 may have a depth defined by removing a portion of the first display insulating layer 31 without reaching the second circuit insulating layer 22.

[0170] When viewed on a plane, the guide pattern GPT-2 has a shape spaced apart from the second display insulating layer 32. The guide pattern GPT-2 may be exposed by the second display insulating layer 32 so that the concave shape of the guide pattern GPT-2 is stably exposed to the organic layer 42.

[0171] Alternatively, if Figure 6c As shown in FIG. 1 , the guide pattern GPT-3 may be a recessed pattern defined in each of the first display insulating layer 31 and the second display insulating layer 32. The guide pattern GPT-3 may include a first recessed pattern GPTa defined in the second display insulating layer 32 and a second recessed pattern GPTb defined in the first display insulating layer 31.

[0172] In cross-section, the first recessed pattern GPTa is recessed from the top surface of the second display insulating layer 32 and is spaced apart from the first display insulating layer 31. In cross-section, the second recessed pattern GPTb is recessed from the top surface of the first display insulating layer 31 and is spaced apart from the second circuit insulating layer 22. The distance by which the first recessed pattern GPTa is spaced apart from the top surface of the second circuit insulating layer 22 and the distance by which the second recessed pattern GPTb is spaced apart from the top surface of the second circuit insulating layer 22 may be the same as or different from each other.

[0173] When viewed on a plane, the first recessed pattern GPTa and the second recessed pattern GPTb may be disposed to be spaced apart from each other. The second recessed pattern GPTb may be exposed by the second display insulating layer 32. Therefore, the recessed shape of each of the first recessed pattern GPTa and the second recessed pattern GPTb is stably exposed to the organic layer 42, making it easy to control the diffusivity of the organic layer 42.

[0174] Figure 7a and Figure 7b 1 is a cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention. Figure 7a and Figure 7b Shown with Figure 5b In the following, reference will be made to Figure 7a and Figure 7b Describe the present invention. Figures 1 to 6c The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0175] like Figure 7a and Figure 7b As shown in , when viewed in cross section, the guide patterns GPT-R1 and GPT-R2 according to an embodiment of the present invention may be protrusion patterns spaced apart from at least one of the first display insulating layer 31 and the second display insulating layer 32 . Figure 7a and Figure 7b Each of the guide patterns GPT-R1 and GPT-R2 shown in FIG. 4 may have a configuration that is independent and separable from the display insulating layers 31 and 32 of the display layer.

[0176] For example, Figure 7a As shown in , the guide pattern GPT-R1 may have a shape that is spaced apart from the first display insulating layer 31 and the second display insulating layer 32 and protrudes from the top surface of the second circuit insulating layer 22. In the present embodiment, the guide pattern GPT-R1 may be a laminated structure including a first layer R1 and a second layer R2. The first layer R1 may be disposed on the same layer as the first display insulating layer 31, and may include the same material as the first display insulating layer 31. The second layer R2 may be disposed on the first layer R1, disposed on the same layer as the second display insulating layer 32, and include the same material as the second display insulating layer 32.

[0177] The organic layer 42 may cover the guide pattern GPT-R1. At least a portion of the organic layer 42 may fill a space IV1 between a plurality of protruding patterns constituting the guide pattern GPT-R1 or a space between the guide pattern GPT-R1 and the display insulating layer 30. The guide pattern GPT-R1 may allow a region in which the organic layer 42 is formed to be freely designed by controlling the diffusivity of the organic layer 42.

[0178] Alternatively, for example, Figure 7b As shown in FIG. 3 , the guide pattern GPT-R2 may include a protruding pattern disposed on the first display insulating layer 31 and spaced apart from the second display insulating layer 32 . The guide pattern GPT-R2 has a shape protruding from a top surface of the first display insulating layer 31 and spaced apart from the second display insulating layer 32 .

[0179] At least a portion of the organic layer 42 may fill the space IV2 between the plurality of protruding patterns constituting the guide pattern GPT-R2 or the space between the guide pattern GPT-R2 and the second display insulating layer 32. The guide pattern GPT-R2 may allow a region in which the organic layer 42 is formed to be freely designed by controlling the diffusivity of the organic layer 42.

[0180] Figures 8a to 8d 1 is a schematic plan view showing a partial area of ​​a display panel according to an embodiment of the present invention. Figures 8a to 8d In the figure, it is schematically shown that Figure 4b The hole area PA in the area shown in Figure 4b ) corresponding to the area. In the following, reference will be made to Figures 8a to 8d Describe the present invention. Figures 1 to 7b The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0181] like Figure 8a As shown in FIG. 1 , the guide pattern GPT-A may be composed of a plurality of island patterns GPTs-A spaced apart from each other. The island patterns GPTs-A may be spaced apart from each other in the line area LA. In this embodiment, the island patterns GPTs-A may be randomly arranged. Figure 4b Unlike the pattern GPTs shown in , the island patterns GPTs-A may be disposed to be distributed within the line area LA without dividing the column or row by using the module hole MH as the center HC.

[0182] Alternatively, if Figure 8b As shown in , the guide pattern GPT-B may be composed of a plurality of line patterns GPTs-B spaced apart from each other. Each of the line patterns GPTs-B may have a line shape extending in one direction. The line patterns GPTs-B may be arranged so that the extension direction of each of the line patterns GPTs-B is not limited to any one direction but faces different directions.

[0183] The line patterns GPTs-B according to an embodiment of the present invention may be arranged such that the extension direction is set in a direction at least surrounding the module hole MH. Therefore, one end of each of the line patterns GPTs-B may be set in a direction other than the direction toward the center HC of the module hole MH. Therefore, the line patterns GPTs-B may be set in a direction in which each of the extension directions is aligned with the organic layer 42 (see FIG. Figure 5a ) intersects with the direction along which the diffusion of the organic layer 42 proceeds. Therefore, overflow of the organic layer 42 toward the module hole MH or excessive diffusion of the organic layer 42 toward the groove area GA can be easily prevented.

[0184] Alternatively, if Figure 8c As shown in , the guide pattern GPT-C may be composed of closed linear patterns GPTs-C spaced apart from each other. Each of the closed linear patterns GPTs-C may surround the module hole MH. Each of the closed linear patterns GPTs-C may have a circular shape corresponding to the module hole MH.

[0185] Alternatively, if Figure 8dAs shown in , each of the closed linear patterns GPTs-D constituting the guide pattern GPT-D may have a shape different from the shape of the module hole MH. In the present embodiment, each of the closed linear patterns GPTs-D is shown to have a polygonal shape. In the present embodiment, each of the closed linear patterns GPTs-D is shown to have a similar shape. Therefore, each of the closed linear patterns GPTs-D has a hexagonal shape. However, this is merely an example. For example, the closed linear patterns GPTs-D may have shapes different from each other, but are not limited to any one embodiment.

[0186] The guide patterns GPT-C and GPT-D may be configured as a single closed linear pattern or three or more closed linear patterns, but are not limited to any one embodiment.

[0187] Figures 9a to 9c is a cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention. Figures 9a to 9c Describe the present invention. Figures 1 to 8d The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0188] like Figure 9a As shown in FIG. 1 , the display panel 100 - 1 may include a plurality of groove patterns GV1 and GV2 . When viewed on a plane, the groove patterns GV1 and GV2 may include a first groove pattern GV1 and a second groove pattern GV2 spaced apart from each other.

[0189] The first groove pattern GV1 surrounds the module hole MH. The first groove pattern GV1 may be a groove pattern closer to the module hole MH among the first groove pattern GV1 and the second groove pattern GV2. The first groove pattern GV1 may correspond to the first groove portion HM1 defined in the substrate 10-1. The concave space of the first groove pattern GV1 may be provided by the first inorganic layer 41 and the second inorganic layer 43 covering the inner surface of the first groove portion HM1.

[0190] The second groove pattern GV2 surrounds the first groove pattern GV1. The second groove pattern GV2 may be a groove pattern closer to the active area DA among the first groove pattern GV1 and the second groove pattern GV2. The second groove pattern GV2 may correspond to the second groove portion HM2 defined in the substrate 10-1. The concave space of the second groove pattern GV2 may be provided by the first inorganic layer 41 covering the inner surface of the second groove portion HM2.

[0191] In the present embodiment, the second groove pattern GV2 may be filled with the organic layer 42, and the first groove pattern GV1 may be exposed by the organic layer 42. When viewed on a plane, the organic layer 42 may overlap the second groove portion HM2 and may be spaced apart from the first groove portion HM1.

[0192] The display panel 100-1 according to the present invention may further include a hole dam portion DM-H (hereinafter referred to as a dam portion). The dam portion DM-H may be disposed in the hole area PA and may be disposed between the first groove pattern GV1 and the second groove pattern GV2. The dam portion DM-H may be disposed on the same layer as the first display insulating layer 31 or on the same layer as the second display insulating layer 32. The dam portion DM-H may control the diffusion of the organic layer 42 so that the organic layer 42 does not extend to the first groove pattern GV1.

[0193] Alternatively, if Figure 9b As shown in Figure 9a Compared with the display panel 100-1 shown in FIG. 1 , the display panel 100-2 further includes a filling pattern FL disposed in the first groove pattern GV1. The filling pattern FL fills at least a portion of the first groove pattern GV1.

[0194] The filling pattern FL may be spaced apart from the organic layer 42. The filling pattern FL may be sealed by the first inorganic layer 41 and the second inorganic layer 43. The filling pattern FL may include the same material as that of the organic layer 42. Here, the filling pattern FL may be a pattern separated from the organic layer 42. That is, according to the present invention, even if the dam portion DM-H is provided in the display panel 100-2, a portion of the organic layer 42 may pass through the dam portion DM-H and then be filled in the first groove pattern GV1.

[0195] Alternatively, if Fig.9c As shown in FIG. 1 , in the display panel 100-3, a portion of the organic layer 42-F may overlap with the dam portion DM-H. When the fluidity and droplet of the organic layer 42-F are large, a portion of the organic layer 42-F may diffuse to the area overlapping with the dam portion DM-H, and thus, at least a portion of the dam portion DM-H may be covered by the organic layer 42-F.

[0196] This is merely an example. For example, the filling pattern FL may include a material different from that of the organic layers 42 and 42 -F. The display panels 100 - 1 , 100 - 2 , and 100 - 3 according to the embodiment of the present invention may include various embodiments, but are not limited to any one embodiment.

[0197] Figures 10a to 10i is a schematic cross-sectional view showing a method for manufacturing a display panel according to an embodiment of the present invention. Figures 10a to 10i Shown with Figure 5a hereinafter, reference will be made to Figures 10a to 10i Describe the present invention. Figures 1 to 9c The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0198] like Fig.10a As shown in FIG. 1 , an initial insulating substrate 10-I, an initial circuit insulating layer 20-I, and an initial display layer 30-I are formed. The initial insulating substrate 10-I may include an initial base layer 11-I and an initial auxiliary layer 12-I formed on the initial base layer 11-I. The initial auxiliary layer 12-I may be formed by depositing an inorganic material on the entire surface of the initial base layer 11-I to cover the active area DA and the hole area PA.

[0199] Before forming the initial display layer 30-I, a thin film transistor TR, a plurality of signal lines SCL1 and SCL2, a first initial circuit insulating layer 21-I, and a second initial circuit insulating layer 22-I may be formed. The thin film transistor TR includes a semiconductor pattern SP formed by depositing / patterning a semiconductor material, and a control electrode CE, an input electrode IE, and an output electrode OE formed by depositing / patterning a conductive material, respectively.

[0200] The signal lines SCL1 and SCL2 may be formed by depositing / patterning a conductive material in the line area LA. Here, each of the signal lines SCL1 and SCL2 may be formed of the same material as each of the control electrode CE and the input electrode IE, and may be formed simultaneously by the same process. However, this is merely an example. For example, the signal lines SCL1 and SCL2 may be formed by a process separate from the thin film transistor TR, but are not limited to any one embodiment. Each of the first initial circuit insulating layer 21-I and the second initial circuit insulating layer 22-I may be formed by depositing / patterning an insulating material.

[0201] The initial display layer 30-I is formed on the initial circuit insulating layer 20-I. The initial display layer 30-I may include a first initial display insulating layer 31-I and a second initial display insulating layer 32-I.

[0202] A first initial display insulating layer 31-I may be formed on the second initial circuit insulating layer 22-I. The first initial display insulating layer 31-I may be formed by depositing / patterning an insulating material. Here, the first initial display insulating layer 31-I may be patterned to cover the active area DA and the line area LA and to form an opening 31-OP that opens an area corresponding to the initial hole area HA. ​​However, this is merely an example. For example, the opening 31-OP in the first initial display insulating layer 31-I may be omitted, but is not limited to any one embodiment.

[0203] Here, the first electrode E1 may be formed on the first initial display insulating layer 31-I. The first electrode E1 may be formed by depositing / patterning a conductive material. The first electrode E1 may be connected to the thin film transistor TR by passing through the first initial display insulating layer 31-I. The through portion of the first initial display insulating layer 31-I penetrated by the first electrode E1 may be formed simultaneously with the opening 31-OP. However, this is merely an example. For example, the portion penetrated by the first electrode E1 may be formed in a process different from that of the opening 31-OP.

[0204] A second initial display insulating layer 32-I is formed on the first initial display insulating layer 31-I. The second initial display insulating layer 32-I may be formed on the entire surface of the initial insulating substrate 10-I to cover the first electrode E1 and fill the opening 31-OP. The second initial display insulating layer 32-I may be formed by depositing an insulating material.

[0205] Afterwards, if Fig.10b As shown in , the display insulating layer 30 is formed by patterning the second initial display insulating layer 32-I. In this case, a pixel opening OP and a guide pattern GPT may be formed. The pixel opening OP is formed in the active area DA. The pixel opening OP may be formed by removing a portion of the second initial display insulating layer 32-I so that at least a portion of the first electrode E1 is exposed. The pixel opening OP and the guide pattern GPT may be formed in the same process through one mask.

[0206] The guide pattern GPT is formed in the hole area PA. The guide pattern GPT may be formed in the line area LA by being spaced apart from the active area DA. The guide pattern GPT may be formed by removing at least a portion of the second preliminary display insulating layer 32-I.

[0207] Here, the depth of the guide pattern GPT may be determined according to the etching degree of the second initial display insulating layer 32-I. In the present embodiment, the guide pattern GPT may be formed to have a depth at which at least a portion of the first initial display insulating layer 31-I is removed. Therefore, the guide pattern GPT is formed to have a depth that passes through the second initial display insulating layer 32-I and recesses a portion of the first initial display insulating layer 31-I. However, this is merely an example. For example, the etching rate or etching time of the second initial display insulating layer 32-I may be controlled to variously design the depth of the guide pattern GPT, but is not limited to any one embodiment.

[0208] When the second display insulating layer 32 is formed, an opening 32-OP that opens the initial hole area HA may also be formed. In the present embodiment, the opening 31-OP of the first display insulating layer 31 and the opening 32-OP of the second display insulating layer 32 are shown as being independently formed by different processes, but are not limited thereto. Alternatively, the opening 31-OP of the first display insulating layer 31 and the opening 32-OP of the second display insulating layer 32 may be simultaneously formed by the same process, but are not limited to any one embodiment.

[0209] Afterwards, if Fig.10c As shown in FIG. 1 , the circuit insulating layer 20 is formed by forming an opening 20-OP in the preliminary circuit insulating layer 20-I. The opening 20-OP is formed to pass through the first preliminary circuit insulating layer 21-I and the second preliminary circuit insulating layer 22-I.

[0210] The opening 20-OP may be formed in the hole area HA. ​​The opening 20-OP may correspond to a region in which a groove (to be described later) is formed. Therefore, the opening 20-OP may be formed in a closed line shape around the center of the initial hole area HA to surround a module hole described later.

[0211] Afterwards, if Fig.10d As shown in , a mask MSK in which a predetermined opening portion OP-M is formed is formed. The mask MSK may be formed on the display insulating layer 30 and the circuit insulating layer 20. The mask MSK may be formed by depositing / patterning an inorganic material. For example, the mask MSK may be formed of a metal or a metal oxide. The opening portion OP-M of the mask MSK is formed in a region overlapping with the opening 20-OP formed in the circuit insulating layer 20 so as to expose a portion of the entire surface of the initial insulating substrate 10-I.

[0212] Afterwards, if Fig.10e As shown in FIG. 1 , the auxiliary layer 12 is formed by etching the initial auxiliary layer 12-I using a mask MSK. The portion of the initial auxiliary layer 12-I exposed by the opening portion OP-M of the mask MSK is etched to form a first portion H1. The first portion H1 exposes the top surface of the initial base layer 11-I.

[0213] Afterwards, if Fig.10fAs shown in , the insulating substrate 10 is formed by further etching the initial base layer 11-I using the mask MSK. Due to the difference in etching selectivity between the initial base layer 11-I and the initial auxiliary layer 12-I, the initial base layer 11-I includes a second portion H2 undercut from the opening portion OP-M or the first portion H1 of the mask MSK. The width of the first portion H1 in the first direction DR1 may be smaller than the width of the uppermost side of the second portion H2 in the first direction DR1. The auxiliary layer 12 may be formed with a tip portion TP protruding by undercutting. Therefore, the groove portion HM may include the first portion H1 and the second portion H2, and thus may include the tip portion TP having an undercut shape.

[0214] Afterwards, if Figure 10g As shown in , a light emitting element OD and a first inorganic layer 41 are formed. The light emitting element OD may be formed by sequentially forming an emission layer EL, a control layer OL, and a second electrode E2. The emission layer EL may be formed by printing or spraying a light emitting material into the opening OP through a mask supported by a spacer SPS formed on the top surface of the second display insulating layer 32.

[0215] The control layer OL may be formed by depositing an organic material. The control layer OL may be formed by thermal deposition (i.e., evaporation). Here, a portion of the organic material may be deposited in the groove portion HM to form an organic pattern OL-P. The second electrode E2 may be formed by depositing a conductive material. The deposition of the second electrode E2 may include a physical deposition process including thermal deposition and sputtering. Therefore, although not shown, a portion of the conductive material may be formed in the groove portion HM during the deposition process of the second electrode E2 to form a pattern.

[0216] The first inorganic layer 41 may be formed in the active area DA and the hole area PA. The first inorganic layer 41 may be formed by depositing an insulating material. For example, the first inorganic layer 41 may be formed by depositing an inorganic material or by chemical vapor deposition. Here, the first inorganic layer 41 may be formed along the inner surface of the groove portion HM.

[0217] Afterwards, if Fig.10h As shown in FIG. 4 , an organic layer 42 is formed in the active area DA. The organic layer 42 may be formed by applying a liquid organic material to the first inorganic layer 41 through a solution process such as a screen printing process or an inkjet process.

[0218] The organic layer 42 according to the present embodiment is formed by dropping a liquid organic material into the active area DA and controlling the diffusion of the dropped organic material. Here, the dropped organic material may diffuse from the active area DA toward the hole area PA in the direction of the arrow to contact the guide pattern GPT. The dropped organic material may fill at least a portion of the guide pattern GPT, or the diffusion path may be controlled by the guide pattern GPT so that the dropped organic material is uniformly diffused throughout the entire surface of the line area LA. Therefore, by further providing the guide pattern GPT, the area in which the organic layer 42 is formed may be stably designed.

[0219] Afterwards, if Fig.10i As shown in FIG. 1 , after forming the second inorganic layer 43, the module hole MH is formed to form the display panel 100. The second inorganic layer 43 may be formed by depositing an insulating material. For example, the second inorganic layer 43 may be formed by depositing an inorganic material on the organic layer 42 by chemical vapor deposition. The second inorganic layer 43 may be formed along the inner side of the groove portion HM to form a groove pattern GV. The second inorganic layer 43 may be formed to contact the first inorganic layer 41, and the organic layer 42 may be sealed by the first inorganic layer 41 and the second inorganic layer 43.

[0220] After that, a module hole MH is formed in the hole area PA. The module hole MH may be formed to pass through the display panel 100. The base layer 11, the auxiliary layer 12, the first circuit insulating layer 21, the second circuit insulating layer 22, the control layer OL, the second electrode E2, the first inorganic layer 41, and the second inorganic layer 43 disposed in the hole area PA may be penetrated by laser or drilling. Thus, a cross section 11-E of the base layer 11, a cross section 12-E of the auxiliary layer 12, a cross section 21-E of the first circuit insulating layer 21, a cross section 22-E of the second circuit insulating layer 22, a cross section OL-E of the control layer OL, a cross section E2-E of the second electrode E2, a cross section 41-E of the first inorganic layer 41, and a cross section 43-E of the second inorganic layer 43 may be formed, and an inner surface MH-IS of the module hole MH may be defined by the above cross sections.

[0221] Figures 11a to 11f 1 is a cross-sectional view showing a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11f Shown with Figure 5a hereinafter, reference will be made to Figures 11a to 11f Describe the present invention. Figures 1 to 10i The same components may be assigned the same figure numbers, and their detailed description will be omitted.

[0222] like Fig.11aAs shown in FIG. 1 , an initial insulating substrate 10-I1, an initial circuit insulating layer 20-I1 and an initial display insulating layer 30-I1 are formed. Since the initial insulating substrate 10-I1 and the initial circuit insulating layer 20-I1 correspond to the reference Fig.10a The opening OP exposing the first electrode E1 and the openings 31-OP and 32-OP exposing the initial hole area HA may be formed in the initial display insulating layer 30-I1. Fig.10b Different from the above, the guide pattern GPT is not formed in the initial display insulating layer 30-I1 (see Fig.10b ).

[0223] Afterwards, if Fig.11b As shown in FIG. 1 , the circuit insulating layer 20 is formed by forming an opening 20-OP in the initial circuit insulating layer 20-I1. The opening 20-OP of the initial circuit insulating layer 20-I1 may be formed in the initial hole area HA and corresponds to Fig.10c Therefore, the repeated description thereof will be omitted.

[0224] Afterwards, if Fig.11c As shown in FIG. 1 , a mask MSK1 is formed on the preliminary insulating substrate 10 - I1 . The mask MSK1 may be formed to overlap the aperture area PA and the active area DA, and may be formed by depositing / patterning an inorganic material. In the present embodiment, the mask MSK1 may be formed of a metal oxide.

[0225] The mask MSK1 may include a first opening portion OP-M1 formed in the preliminary hole area HA and a second opening portion OP-M2 formed in the line area LA. Since the first opening portion OP-M1 is a portion for forming the groove portion HM and corresponds to Fig.10d The opening portion OP-M shown in Fig.10d ), so a repeated description thereof will be omitted below. A second opening portion OP-M2 is provided on the initial display insulating layer 30-I1 to expose at least a portion of the top surface of the second initial display insulating layer 32-I1.

[0226] Afterwards, if Fig.11d As shown in the figure, the initial insulating substrate 10-I1 and the initial display insulating layer 30-I1 are etched by the mask MSK1 to form the insulating substrate 10 and the display insulating layer 30. Here, the groove portion HM and the guide pattern GPT can be formed. In this embodiment, the groove portion HM and the guide pattern GPT can be formed in the same process by one mask MSK1. The depth of the guide pattern GPT and the depth of the groove HM can be variously controlled by controlling the etching rate and etching time of the initial display insulating layer 30-I1.

[0227] Afterwards, if Fig.11e and Fig.11f As shown in FIG. 1 , after removing the mask MSK1, the light emitting element OD and the encapsulation layer 40 are formed, and then the module hole MH is formed to form the display panel 100. The detailed description thereof corresponds to the reference Figure 10g to Figure 10i those described above, therefore, duplicate descriptions will be omitted.

[0228] According to the present invention, the guide pattern GPT and the groove portion HM can be simultaneously formed in the same process. Therefore, since the guide pattern GPT is formed without a separate additional process, the process can be simplified, and the process cost and process time can be reduced to make it economical.

[0229] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present disclosure covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

[0230] Therefore, the actual protection scope of the present invention should be determined by the technical scope of the appended claims.

[0231] Industrial Applicability

[0232] In a display panel and a method for manufacturing a display panel, the improvement of process reliability can improve the quality of the display panel, make the manufacturing method more convenient, and be effective in mass production. Therefore, the present invention for improving the process reliability of a display panel and a method for manufacturing a display panel has high industrial applicability.

Claims

1. A display panel, comprising: a base substrate having a front surface and a rear surface and including a hole region, an effective region surrounding the hole region, and a peripheral region adjacent to the effective region, wherein a through hole passing through the front surface and the rear surface and a groove portion surrounding the through hole and recessed from the front surface are defined in the hole region; A circuit layer, comprising a first circuit insulating layer disposed on the front surface of the base substrate, a second circuit insulating layer disposed on the first circuit insulating layer, and a thin film transistor disposed on the front surface of the base substrate and disposed in the active area; A display layer, comprising a first display insulating layer disposed on the circuit layer, a second display insulating layer disposed on the first display insulating layer, and a light emitting element disposed in the effective area and connected to the thin film transistor; A guide pattern, disposed on the circuit layer and between the light emitting element and the groove portion; as well as an encapsulation layer covering the light emitting element and comprising a first inorganic layer disposed in the effective region and the hole region, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, wherein the organic layer covers at least a portion of the guide pattern, and The guide pattern has a shape of at least one of a concave pattern and a protruding pattern in a cross-sectional view.

2. The display panel according to claim 1, wherein: The guide pattern is a recessed pattern defined in at least one of the first display insulating layer and the second display insulating layer.

3. The display panel according to claim 2, wherein: The guide pattern passes through the second display insulating layer in a cross-section and is recessed from a top surface of the first display insulating layer.

4. The display panel according to claim 2, wherein: The guide pattern is defined in the second display insulating layer and is spaced apart from the first display insulating layer.

5. The display panel according to claim 2, wherein: The guide pattern comprises: a first guide pattern defined in the second display insulating layer and recessed from a top surface of the second display insulating layer; and a second guide pattern defined in the first display insulating layer and recessed from a top surface of the first display insulating layer, Wherein, when viewed on a plane, the first guide pattern and the second guide pattern are spaced apart from each other.

6. The display panel according to claim 1, wherein: The guide pattern is a protrusion pattern disposed on the second circuit insulating layer and spaced apart from at least one of the first display insulating layer and the second display insulating layer when viewed on a plane.

7. The display panel according to claim 6, wherein: The guide pattern includes a same material as at least one of the first display insulating layer and the second display insulating layer.

8. The display panel according to claim 1, wherein: The guide pattern includes a plurality of island patterns spaced apart from each other when viewed on a plane.

9. The display panel according to claim 8, wherein: The island patterns are radially arranged from the center of the through hole.

10. The display panel according to claim 8, wherein: The island patterns are randomly arranged.

11. The display panel according to claim 1, wherein: When viewed on a plane, the guide pattern has a closed line shape surrounding the groove portion.

12. The display panel according to claim 11, wherein: The closed line shape includes a circular shape, an elliptical shape, and a polygonal shape.

13. The display panel according to claim 1, wherein: The groove portion has an undercut shape in cross section.

14. The display panel according to claim 1, wherein: The groove portion comprises: a first groove portion adjacent to the through hole; and a second groove portion disposed between the first groove portion and the guide pattern to surround the first groove portion, wherein each of an inner surface of the first groove portion and an inner surface of the second groove portion is covered by the first inorganic layer.

15. The display panel according to claim 14, wherein: When viewed on a plane, the organic layer overlaps the second groove portion and is spaced apart from the first groove portion.

16. The display panel of claim 15, further comprising a filling pattern disposed at the first groove portion and spaced apart from the organic layer and sealed by the first inorganic layer and the second inorganic layer, in, The filling pattern includes the same material as that of the organic layer.

17. The display panel according to claim 14, wherein: When viewed on a plane, the organic layer overlaps the first and second groove portions.

18. The display panel according to claim 1, further comprising a dam portion provided between the groove portion and the through hole to surround the through hole, in, The first inorganic layer covers the dam portion.

19. An electronic device, comprising: a display panel having a through hole and a groove pattern defined therein, the groove pattern being adjacent to the through hole and configured to provide a predetermined recessed space; as well as an electronic module, overlapping the through hole when viewed on a plane, Wherein, the display panel comprises: a base substrate having the groove pattern defined therein; The circuit layer comprises a first circuit insulating layer disposed on the base substrate, a second circuit insulating layer disposed on the first circuit insulating layer, and a thin film transistor disposed in an effective area; A display layer, comprising a first display insulating layer disposed on the circuit layer, a second display insulating layer disposed on the first display insulating layer, and a light emitting element disposed in the effective area and connected to the thin film transistor; a concave pattern disposed between the groove pattern and the active area and defined in at least one of the first display insulating layer and the second display insulating layer; and an encapsulation layer covering the light emitting element and comprising a first inorganic layer disposed in the effective area and the hole area, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, Wherein, at least a portion of the concave pattern is filled with the organic layer.

20. The electronic device according to claim 19, wherein: The recessed pattern is recessed from a top surface of the second display insulation layer.

21. The electronic device according to claim 20, wherein: The concave pattern passes through the second display insulating layer and extends up to the first display insulating layer.

22. The electronic device according to claim 19, wherein: The recessed pattern is recessed from a top surface of the first display insulating layer and is spaced apart from the second display insulating layer when viewed on a plane.

23. The electronic device according to claim 19, wherein: The recessed pattern is provided in plurality, each of the plurality of recessed patterns has an island shape, and the plurality of recessed patterns are radially arranged from a center of the through hole.

24. The electronic device according to claim 19, wherein: The concave pattern is provided in plurality, each of the plurality of concave patterns has an island shape, and the plurality of concave patterns are randomly arranged.

25. The electronic device according to claim 24, wherein: The display panel further includes a dam portion disposed adjacent to the through hole, The groove pattern includes a first groove pattern and a second groove pattern, the first groove pattern being disposed between the through hole and the dam portion, the second groove pattern being disposed between the dam portion and the concave pattern to surround the first groove pattern, and The second groove pattern is filled with the organic layer.

26. The electronic device according to claim 19, wherein: The concave pattern has a closed line shape surrounding the through hole.

27. A method for manufacturing a display panel, the method comprising: forming a circuit layer on the front surface of the base substrate, the circuit layer comprising a first circuit insulating layer, a second circuit insulating layer and a thin film transistor, and when viewed on a plane, the base substrate is divided into a hole area and an effective area surrounding the hole area; forming a first initial display insulating layer and a second initial display insulating layer on the circuit layer; forming, at the base substrate, a groove portion recessed from the front surface of the base substrate; as well as patterning at least one of the first initial display insulating layer and the second initial display insulating layer to form a guide pattern, Wherein, the guide pattern is a recessed pattern defined in at least one of the first initial display insulating layer and the second initial display insulating layer, or a protruding pattern arranged on the second circuit insulating layer and spaced apart from at least one of the first initial display insulating layer and the second initial display insulating layer when viewed on a plane.

28. The method according to claim 27, wherein: The guide pattern and the groove portion are formed at the same time.

29. The method according to claim 28, further comprising forming a mask, the mask comprising a first opening portion exposing a portion of the hole region of the base substrate and a second opening portion exposing a portion of the hole region of the second initial display insulating layer, in, The groove portion is formed by removing a portion of a region exposed by the first opening portion, and The guide pattern is formed by removing a portion of a region exposed by the second opening portion.

30. The method of claim 27, wherein: After forming the first display insulating layer, forming a second display insulating layer, Forming the second display insulating layer includes: forming a first electrode connected to the thin film transistor on the first display insulating layer; forming an initial insulating layer covering the first electrode; and forming an opening at the initial insulating layer to expose at least a portion of the first electrode, and The guide pattern and the opening are formed at the same time.

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