Processing device and memory management method for processing device

Abstract

A device and method are disclosed. In the device, a memory management unit includes: a first cache unit, used to store multiple first source operands and a first write address; a second cache unit, used to store at least one pair of second source operands and a second destination address; a write cache module, used to judge the destination addresses of multiple storage instructions, so as to store multiple source operands corresponding to continuous destination addresses in the first cache unit, and store discontinuous destination addresses and source operands corresponding to discontinuous destination addresses in the second cache unit, and the first write address is the first address of the continuous destination address; a bus transmission module, used to transmit the multiple first source operands and the first write address in the first cache unit to the memory via the bus in a write burst transmission mode. The embodiment of the present invention establishes a burst transmission mode between the processor and the bus, which can reduce the occupation of the bus address bandwidth and accelerate the write efficiency of the memory.

Description

Technical Field

[0001] The present invention relates to the field of processor manufacturing, and more particularly to a processing device and a memory management method for the processing device. Background Art

[0002] In processor design, data is stored in memory. In the processor, the data width of the data (opcode) corresponding to the instruction is usually 8 / 16 / 32 bits. High-performance processors also include 64-bit data. The processor uses load instructions to move instruction data to the processor. After calculation, the result is stored in external storage through store instructions. Some typical applications also require continuous write operations to a continuous address of the memory, such as memory transfer, data generation of continuous addresses, etc. These write operations are written to the bus through continuous storage instructions, and finally written to the memory. These write operations are implemented using storage instructions, and each storage instruction can store up to 32 or 64 bits (the maximum data width of the processor) of data at a time.

[0003] For high-performance processors, the data width of the external bus is above 64 / 128 bits, and the above-mentioned write operation to consecutive addresses will only occupy half or even less of the bus data width each time. Generally speaking, the bus includes transmission delays such as handshake protocols, and continuous single write transmissions are not efficient for continuous write operations. Summary of the invention

[0004] In view of this, the present invention proposes a processing device and a memory management method for the processing device to solve the above problems.

[0005] To achieve this object, according to a first aspect of the present invention, an embodiment of the present invention provides a processing device, the processing device comprising a memory management unit coupled to a memory via a bus, the memory management unit comprising:

[0006] A first cache unit, used for storing a plurality of first source operands and a first write address;

[0007] A second cache unit, used to store at least one pair of a second source operand and a second destination address;

[0008] a write cache module, configured to judge the destination addresses of the plurality of storage instructions, so as to store the plurality of source operands corresponding to the continuous destination addresses into the first cache unit, and store the discontinuous destination addresses and the source operands corresponding to the discontinuous destination addresses into the second cache unit, wherein the first write address is the first address of the continuous destination addresses;

[0009] A bus transmission module is used to transmit multiple first source operands and the first write address in the first cache unit to the memory via the bus in a write burst transmission mode, and to transmit each pair of the second source operand and the second destination address in the second cache unit to the memory via the bus in other transmission modes.

[0010] In some embodiments, the first cache unit further stores indication data and identification data, the indication data being used to indicate whether the plurality of first source operands are valid, and the identification data being used to indicate a continuous manner of destination addresses corresponding to the plurality of first source operands.

[0011] In some embodiments, the bus transmission module includes:

[0012] a burst determination unit, configured to determine whether a write burst transfer mode can be started according to the indication data and the identification data, and to determine whether a destination address corresponding to the plurality of first source operands is an increasing continuous address or a decreasing continuous address;

[0013] A burst transfer unit is used to transfer the first write address and the multiple first source operands to the bus in a write burst transfer mode when the destination address corresponding to the multiple first source operands is an increasing continuous address; if the destination address corresponding to the multiple first source operands is a decreasing continuous address, then in a write burst transfer mode, send the first write address and an identifier representing the decreasing continuous address and the multiple first source operands to the bus.

[0014] In some embodiments, the bus is directly forwarded to the memory, and the memory performs different write operations according to the increasing continuous address or the decreasing continuous address.

[0015] In some embodiments, the bus adjusts the plurality of first source operands from decrementing consecutive addresses to increasing consecutive addresses, and sends the adjusted plurality of first source operands and the first write address to the memory.

[0016] In some embodiments, the multiple first source operands are combined into multiple write data, each write data has the same data length, and data transmission in a write burst transmission mode is performed using the write data as a unit.

[0017] In some embodiments, the data length of the write data is equal to the data bit width of the bus.

[0018] In some embodiments, the write burst transmission unit further comprises: when the data length of the write data is smaller than the data bit width of the bus, indicating the valid data transmitted to the bus through a cutoff mark.

[0019] In some embodiments, the bus transmission module performs data transmission in a write burst transmission mode in a manner where addresses and data are separated.

[0020] In some embodiments, it also includes: judging whether the bus transmission module is currently started according to the time requirement of the storage instruction corresponding to the first address.

[0021] In some embodiments, the write cache module further comprises: acquiring source operands and target addresses of the plurality of storage instructions from a cache inside an LSU component of the instruction pipeline structure.

[0022] In some embodiments, the processing device is a processor core or a processor, and the bus and the memory are located inside the processing device.

[0023] In some embodiments, the processing device is a processor core or a processor, and the bus and the memory are located outside the processing device.

[0024] In a second aspect, an embodiment of the present invention provides a memory management method for a processing device, comprising:

[0025] Loop to get the source operands and destination addresses of multiple storage instructions;

[0026] storing a plurality of first source operands corresponding to the continuous destination addresses and the first addresses of the continuous destination addresses in a first cache unit;

[0027] In the write burst transfer mode, a plurality of first source operands in the first cache unit and the first address are transferred to the memory via the bus.

[0028] In some embodiments, the first cache unit further stores indication data and identification data, the indication data being used to indicate whether the plurality of first source operands are valid, and the identification data being used to indicate a continuous manner of destination addresses corresponding to the plurality of first source operands.

[0029] In some embodiments, in the write burst transfer mode, transmitting the plurality of first source operands in the first cache unit and the first write address to the memory via the bus further comprises:

[0030] Determining whether a write burst transfer mode can be started according to the indication data and the identification data, and determining whether the destination addresses corresponding to the plurality of first source operands are increasing continuous addresses or decreasing continuous addresses;

[0031] When the destination addresses corresponding to the plurality of first source operands are increasing consecutive addresses, in a write burst transfer mode, transmitting the first address and the plurality of first source operands to the bus;

[0032] When the destination addresses corresponding to the multiple first source operands are decrementing continuous addresses, in a write burst transfer mode, the first address, an identifier indicating the decrementing continuous addresses, and the multiple first source operands are sent to the bus.

[0033] In some embodiments, the bus is directly forwarded to the memory, and the memory performs different write operations according to the increasing continuous address or the decreasing continuous address.

[0034] In some embodiments, the bus adjusts the plurality of first source operands from decrementing consecutive addresses to increasing consecutive addresses, and sends the adjusted plurality of first source operands and the first address to the memory.

[0035] In some embodiments, the multiple first source operands are combined into multiple write data, each write data has the same data length, and data transmission in a write burst transmission mode is performed using the write data as a unit.

[0036] In some embodiments, the data length of the write data is equal to the data bit width of the bus.

[0037] In some embodiments, the method further includes: when the data length of the write data is smaller than the data bit width of the bus, indicating valid data transmitted to the bus through a cutoff mark.

[0038] In some embodiments, it also includes: judging whether data transmission is currently started based on the time requirement of the storage instruction corresponding to the first address.

[0039] In a third aspect, an embodiment of the present invention provides a computer system, comprising any processing device as described above.

[0040] In a fourth aspect, an embodiment of the present invention provides a system on chip, comprising a processing device as described in any one of the above items.

[0041] Compared with the prior art, the embodiment of the present invention has the advantage that, for the source operands of multiple storage instructions, multiple first source operands corresponding to continuous destination addresses are stored, and the first address of the continuous destination addresses is used as the first write address. In the burst transmission mode, the multiple first source operands are transmitted with the first write address, thereby reducing the occupancy of the bus address bandwidth and accelerating the write efficiency of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present invention will become more apparent through the description of the embodiments of the present invention with reference to the following drawings, in which:

[0043] Figure 1is a schematic diagram of the structure of a computer system for implementing an embodiment of the present invention;

[0044] Figure 2 is a schematic diagram of the structure of a system on a chip for implementing an embodiment of the present invention;

[0045] Figure 3 is a block diagram of a processor for implementing an embodiment of the present invention;

[0046] Figure 4 is a structural diagram of a processor for implementing another embodiment of the present invention;

[0047] Figure 5a is a schematic diagram of an exemplary burst write transfer;

[0048] Figure 5b is a schematic diagram of another exemplary burst write transfer;

[0049] Figure 6 It is a flow chart of the method provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0051] The following terms are used in this article.

[0052] Bit width supported by the processor: Bit width refers to the data bandwidth of the processor to execute instructions at one time. Currently, the minimum bit width of the processor is 8 bits, and the maximum bit width includes 16 / 32 / 64 bits.

[0053] Bus data width: refers to the maximum data bandwidth that the external bus can transmit at one time.

[0054] Instruction pipeline, the instruction pipeline is to improve the efficiency of the processor to execute instructions, divide the operation of an instruction into multiple small steps, and each step is completed by a special circuit. The current mainstream instruction pipeline technologies include three-level, four-level, five-level, seven-level and super instruction pipelines, etc. For example, the five-level instruction pipeline in the textbook example includes the instruction fetch level, decoding level, execution level, memory access level and write-back level. In this article, the instruction fetch level, decoding level, execution level, memory access level and write-back level are also called instruction fetch unit, decoding unit, execution unit, memory access unit and write-back unit.

[0055] Pipeline structure, the combination of software and hardware that implements the instruction pipeline is called a pipeline structure.

[0056] Write burst transfer, also known as write burst, is a continuous transfer protocol in the bus protocol. Usually in the bus, the burst transfer protocol contains an address information and multiple data information, which means that multiple data information is stored in continuous addresses starting from this address, or continuous and aligned addresses. For example, in the continuous transfer protocol in the OCP protocol, the write address channel sends a write burst transfer, which specifies the data width as 128bit, the burst type as wrap, and the transfer length as 4, which means sending a write transfer of 4 128bit data, and the address is a 4*128bit aligned address. Then, on the write data channel, the bus will receive 4 128bit data. In this article, write burst transfer is sometimes referred to as write burst transfer mode.

[0057] Write data: one write burst transfer specifies one address information and multiple data information. In this article, one data information in one burst transfer is called write data.

[0058] Source operand refers to the data that the storage instruction needs to write.

[0059] The destination address refers to the storage location where the storage instruction needs to be written. The destination address can be a physical address or a virtual address.

[0060] Figure 1 is a schematic diagram of the structure of a processing system for implementing the present invention, wherein the processing system is, for example, a computer system. Figure 1 , system 100 is an example of a "central" system architecture. System 100 can be built based on various processor models currently on the market and is powered by WINDOWS TM Operating system version, UNIX operating system, Linux operating system, etc. Operating system drivers. In addition, the system 100 is generally implemented in a PC, a desktop, a notebook, or a server.

[0061] like Figure 1 As shown, system 100 includes processor 102. Processor 102 has data processing capabilities known in the art. It can be a processor of complex instruction set (CISC) architecture, reduced instruction set (RISC) architecture, very long instruction set (VLIW) architecture, or a processor that implements a combination of the above instruction sets, or any electronic device built for a specific purpose.

[0062] The processor 102 is coupled to the system bus 101, which can transmit data signals between the processor 102 and other components. The processor 102 may also include an internal memory 1022 and a processor core 1021 improved according to the technical solution provided in the embodiment of the present invention, and the specific details will be provided below.

[0063] The system 100 also includes a memory 104 and a graphics card 105. The memory 104 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other memory devices. The memory 104 may store instruction information and / or data information represented by data signals. The graphics card 105 includes a display driver for controlling the correct display of display signals on a display screen.

[0064] The graphics card 105 and the memory 104 are coupled to the system bus 101 via the memory controller hub 103. The processor 102 can communicate with the memory controller hub 103 via the system bus 101. The memory controller hub 103 provides a high-bandwidth memory access path 421 to the memory 104 for storing and reading instruction information and data information. At the same time, the memory controller hub 103 and the graphics card 105 transmit display signals based on the graphics card signal input and output interface 420. The graphics card signal input and output interface 420 is, for example, an interface type such as DVI, HDMI, etc.

[0065] The memory controller hub 103 not only transmits digital signals between the processor 102 , the memory 103 and the graphics card 105 , but also bridges digital signals between the system bus 101 and the memory 104 and the input / output control hub 106 .

[0066] The system 100 further includes an input / output control center 106, which is coupled to the memory controller center 103 via a dedicated hub interface bus 422, and some I / O devices are connected to the input / output control center 106 via a local I / 0 bus. The local I / 0 bus is used to couple peripheral devices to the input / output control center 106, and then to the memory controller center 103 and the system bus 101. The peripheral devices include, but are not limited to, the following devices: a hard disk 107, an optical drive 108, a sound card 109, a serial expansion port 110, an audio controller 111, a keyboard 112, a mouse 113, a GPIO interface 114, a flash memory 115, and a network card 116.

[0067] Of course, different computer systems have different structure diagrams according to different motherboards, operating systems and instruction set architectures. For example, many computer systems currently integrate the memory controller center 103 into the processor 102, so that the input / output control center 106 becomes a control center coupled to the processor 103.

[0068] Figure 2 2 is a schematic diagram of a system on chip 200 for implementing the present invention. As a system on chip, the system 200 can be produced and sold as an independent device, or combined with other components to form a new device for production and sale.

[0069] System 200 can be manufactured using various processor models currently on the market and can be powered by WINDOWS TM , UNIX, Linux and Android, RTOS and other operating systems. System 200 can be implemented in computer devices, handheld devices and embedded products. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs) and handheld PCs. Embedded products can include network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can execute one or more instructions.

[0070] refer to Figure 2 As shown, the system 200 includes a processor 202 , a static random access memory 205 , an LCD controller 204 , a flash memory 206 , and a bus bridge 207 coupled via a system bus 201 .

[0071] The processor 202 may be a complex instruction set (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction set (VLIW) microprocessor, a microprocessor implementing a combination of the above instruction sets, or any other processor device. The processor 202 also includes an internal memory 2022 and a processor core 221 improved according to the technical solution provided in an embodiment of the present invention, and its specific details will be provided below.

[0072] The static random access memory 205 and the flash memory 206 are used to store instruction information and / or data information represented by digital signals. For example, the static random access memory 205 can be used as a running space for various applications, creating heaps, stacks, storing intermediate data, etc. for various applications, and the flash memory 206 can store executable codes of various applications and executable codes of the operating system.

[0073] The system bus 201 is used to transmit digital signals between high-performance modules of the system 200 , such as transmitting digital signals between the processor 202 and static random access memory 205 , the processor 202 and LCD controller 204 , the processor 202 and flash memory 206 , and the processor 202 and bus bridge 207 .

[0074] The bus bridge 207 is used to bridge data transmission between the system bus and the peripheral bus. It achieves conversion from the system bus protocol to the peripheral bus protocol by latching the address, data and control signals from the system bus and providing secondary decoding to generate selection signals for peripheral devices.

[0075] The system 200 may also include various interfaces coupled to the peripheral bus. The various interfaces include, but are not limited to, the following interface types: Secure Digital High Capacity (SDHC), I2C bus, Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Universal Serial Bus (USB), General-purpose input / output (GPIO), and Bluetooth UART. Peripheral devices coupled to the interface are, for example, USB devices, memory cards, message transceivers, Bluetooth devices, etc.

[0076] It should be pointed out that with the increasing complexity of SoC design and the continuous improvement of processor processing power, on-chip bus technology is also constantly evolving. At present, there are two implementation schemes for on-chip bus. One is to use the internationally open and universal bus structure, such as the OCP (Open Core Protocol) bus protocol; the other is to independently develop on-chip bus according to specific fields. Therefore, although the bus structure including system bus, bus bridge and peripheral bus is shown in the figure, in the actual system-level chip manufacturing process, due to the constraints of economic benefits and technical routes, the choice of bus structure is diverse, which in turn affects the structure of on-chip bus.

[0077] In summary, it should also be pointed out that Figure 1 and Figure 2 The system shown is only used to illustrate some application scenarios of the embodiments of the present invention, but is not intended to limit the embodiments of the present invention. The present invention improves the existing processor or processor core, so it can theoretically be applied to systems with any processor architecture and instruction set architecture.

[0078] Figure 3 3 is a schematic diagram of the structure of a processor 300 according to an embodiment of the present invention. In the figure, arrows represent the coupling relationship between two or more units and the data transmission direction between the two.

[0079] refer to Figure 3As shown, the processor 300 includes a coupled instruction pipeline 310 and a memory management unit 320, wherein the instruction pipeline 310 and the memory management unit 320 may be included in the processor core. In this example, the instruction pipeline structure 310 may be an instruction pipeline structure of any level, for example, a four-level instruction pipeline including an instruction fetch unit, a decoding unit, a scheduling unit, and an execution unit may be used, or a standard five-level pipeline structure using a textbook example may be used to implement this embodiment, and the present invention is not limited to this.

[0080] For memory access instructions (store instructions and load instructions), the instruction pipeline structure uses the LSU component (Load / Store Unit) within it to process it, and stores the address and data in the cache inside the LSU component. When the memory access instruction is retired from the instruction pipeline structure, the data needs to be stored in the cache or memory inside or outside the processor core. Therefore, for storage instructions, the memory management unit 320 can read the source operand and destination address of each storage instruction from the cache inside the LSU component, or read the source operand and destination address of each storage instruction from other locations.

[0081] The memory management unit 320 may include a first cache unit 323, which is used to store multiple source operands corresponding to continuous destination addresses of the instruction and the first addresses of the continuous destination addresses. The first cache unit 323 can be implemented using an internal memory (cache, memory) or a register. As shown in the figure, the first cache unit 323 also stores indication data. The indication data is used to indicate whether the multiple source operands corresponding to the continuous destination addresses are valid. The minimum bit width currently supported by the processor is 8 bits, so the data bit width of any source operand is a multiple of 8 bits. The indication data and the identification data may include multiple indication bits, each indication bit is one bit, and each indication bit corresponds to a data bit width of 8 bits. To illustrate with an example. If the data bit width of a source operand is 32 bits, then there are 4 bits of indication bits in the indication data to indicate whether the first source operand is valid. If valid, the 4 bits of indication bits are all set to 1, if invalid, they are 0, and so on. The data bit width of the external bus is generally an integer multiple of the minimum bit width supported by the processor, for example, the data bit width of the external bus is 64 or 128 bits.

[0082] The memory management unit 320 may further include a second cache unit (not shown), which is used to store at least one pair of a second source operand and a second destination address. The second cache unit may also be implemented using an internal cache or register.

[0083] In this embodiment, the memory management unit 320 may apply for storage space for the first cache unit and / or the second cache unit at one time, or may apply for new storage space for the source operand and the destination address each time a storage instruction is obtained.

[0084] The memory management unit 320 also includes a logic unit (including logic implemented by software and / or hardware) for implementing the destination address judgment of multiple storage instructions and bus transmission according to the judgment result. The logic unit can be divided into a write cache module 321 and a bus transmission module 322 according to the function. The write cache module 321 is used to obtain the source operands and destination addresses of multiple storage instructions that need to be written to the bus from the instruction pipeline structure 310, for example, the source operands and destination addresses of the multiple storage instructions can be obtained from the cache inside the LSU component 311. The multiple storage instructions can come from the same instruction pipeline or from multiple instruction pipelines. The destination address of the earliest storage instruction can be stored as the first address in the first cache unit 323. The write cache module 321 judges the destination addresses of multiple storage instructions to store multiple source operands corresponding to the continuous destination addresses in the first cache unit 323, and stores the discontinuous destination addresses and the source operands corresponding to the discontinuous destination addresses in the second cache unit. Specifically, each time the write cache module 321 receives the source operand and destination address of a storage instruction, it determines whether the destination address falls within the address range (the address range is calculated by the first address + the size of multiple data units). If it hits, the source operand of the storage instruction is stored in the corresponding position of the first cache unit, and the identification bit in the identification data is set.

[0085] The bus transmission module 322 checks the indication data. If all bits of the indication data are 1, the source operand in the first cache unit 323 can be sent once or multiple times according to the bus transmission protocol. Take an example. Assuming that the size of the first cache unit is 128 bits, the indication data includes 16 (128 / 8) indication bits, and the 16 indication data are initialized to '0000000000000000'. Assuming that the first address is 10000, the address range of the first cache unit should be [10000, 10015]. Then, when a 32-bit write operation with an address of 10004 is sent, the write cache module 321 finds that the address falls in the address range of [10004, 10007], and stores the data of the write operation at this location, and modifies the 16-bit indication data to '0000000011110000', where the value 1 indicates that the data at the address is valid data. When the bus transmission module 322 checks that all the indication bits are 1, it sends multiple source operands in the first cache unit 323 to the external bus 324. The external bus 324 can be Figure 1The bus 101 in Figure 2 It should be understood that, corresponding to different bus types, it is necessary to specify the values ​​of relevant parameters and send data according to the corresponding bus protocol specifications.

[0086] In some embodiments, the first cache unit 323 also stores identification data. The identification data is used to indicate the continuity of the continuous destination address, including increasing continuity and decreasing continuity. For example, the identification data can use a 2-bit identification bit corresponding to a source operand. When the identification bit is '01', it indicates that the address is increasing and continuous. When the identification bit is '11', it indicates that the address is decreasing and continuous. In the write cache module 321, when the destination address of a storage instruction is obtained, it needs to be checked for bidirectional continuity. If it is increasing and continuous, it is marked as '01', otherwise it is marked as '11'.

[0087] In some embodiments, the bus transmission module 322 can be further divided into a burst judgment unit 3221, a normal transmission unit 3222 and a burst transmission unit 3223. When the source operand of the earliest storage instruction needs to be written to the external bus, the burst judgment unit 3221 checks the identification data and the indication data in the first cache unit to determine whether a write burst transmission can be initiated. If yes, the burst transmission unit 3223 is used to send multiple source operands to the external bus 324 in the burst transmission mode. The judgment mechanism is that, first, the indication data must all be set to '1', which means that the corresponding data are all valid data; secondly, whether the identification data is unified, that is, the identification bits are all '01' or all '11'. Only when both conditions are met can the burst transmission unit 3223 be used for write burst transmission. Take an example. If there is a 64-bit source operand in the first cache unit, and a write burst transmission is performed with 32 bits as write data, the length of the burst transmission is 2, and 2 64-bit data will be transmitted in sequence on the write data channel of the bus. At this time, the data width of the bus is 128 bits, which is equivalent to that the bus data bandwidth is not fully occupied, so it is necessary to use a cutoff mark to specify which data is valid data. Of course, in this example, the ordinary transmission unit 3222 can also be used to write 128 bits of write data to the bus. It should be understood that the specifications of the burst transmission mode under different bus protocols are different, so various applications need to be adjusted according to actual conditions. The ordinary transmission unit 3222 uses a transmission mode other than the write burst transmission mode to send the source operand and destination address in the second cache unit. For one or more pairs of source operands and destination addresses in the second cache unit, the ordinary transmission unit 3223 can initiate data transmission without waiting for the judgment result of the burst judgment unit 3221.

[0088] In this embodiment, a burst transmission mode is established between the processor and the bus, which can reduce the occupation of the bus address bandwidth and accelerate the writing efficiency of the memory.

[0089] As a preferred embodiment, in order to make full use of the data bit width of the external bus, the source operand can also be merged with the data bit width of the external bus as the write data, and then the write burst transfer mode is used to write the data. Take an example. If the data bit width of the external bus is 128 bits, then 128 bits are used as a write data. If there are 4 such write data, the length of the burst transfer is 4, which means that a write burst data transmission of 4 128 bits is sent, then on the write data channel, the bus will receive 4 128 bits in sequence. The number of write data and the burst transfer type in the burst transfer mode can be freely set. Therefore, this implementation can not only take advantage of the burst transfer mode, but also make full use of the bus transmission bandwidth data bit width of the external bus, and make the bus transmission break through the limitation of the maximum bit width supported by the processor.

[0090] Figure 4 is a structural diagram of a processor for implementing another embodiment of the present invention. Figure 4 The processor 400 in the embodiment includes, in addition to the coupled instruction pipeline 310 and the memory management unit 320, an internal bus 410 and an internal memory (not shown) coupled to the processor 400 via the internal bus 410. Optionally, the instruction pipeline 310, the memory management unit 320, the internal bus 410 and the internal memory may all be located in the processor core, or the instruction pipeline 310 and the memory management unit 320 are located in the processor core, while the internal bus 410 and the internal memory are located in the processor. Since in the present invention, the write burst transfer mode needs to distinguish between incremental continuous or decremental continuous write operations, it is possible to indicate on the data specification of the bus whether the current write burst transfer is incremental continuous or decremental continuous.

[0091] Figure 5a is a schematic diagram of an exemplary burst write transfer. Figure 5a As shown, the burst transmission unit 3223 and the external bus 324 use different transmission channels to transmit control signals 503, write data 502 and return information 501. The control signal 503 includes a write address 5031, a write length (4 in this example) 5032 and other control signals. The write data 502 includes four write data, which are sent to the external bus 324 (which can also be Figure 4During the burst write transmission process, the corresponding port of the external bus 324 (or the internal bus 410) is controlled to only receive the write data and control signal of the burst transmission unit 3223 in sequence, until the four-length write data is received, and the external bus 324 returns the return information 501 to the burst transmission unit 3223.

[0092] Figure 5b is another exemplary burst write transfer diagram. and Figure 5b The difference is that Figure 5a By default, the addresses of each write data of the write data 502 are ascending and continuous, but in this example, the data unit 3223 specifies in the control signal 503 that the addresses of each write data of the write data 502 are descending and continuous, that is, the flag bit '2' in the figure indicates descending and continuous. If it is ascending and continuous, the external bus 324 (or the internal bus 410) can directly send each write data and the write address 5031 to the memory, and the memory writes each write data to the write address 5031 and a continuous space thereafter according to the internal addressing logic. If it is descending and continuous, the external bus 324 (or the internal bus 410) also needs to convert the write address 5031 into the first address of a piece of ascending and continuous space, and then send each write data and the first address of the ascending and continuous space to the memory, and the memory writes each write data to the ascending and continuous space according to the internal addressing logic. If it is decreasing continuity, the external bus 324 (or the internal bus 410) can also send the decreasing continuity mark to the memory, and the memory converts the write address 5031 into the first address of a piece of increasing continuous space, and then writes each write data into the piece of increasing continuous space.

[0093] Figure 6 It is a flow chart of the method provided by the embodiment of the present invention. Figure 6 The method shown can be performed by any electronic device including the processing core or processor of the above-mentioned embodiment. The electronic device is, for example, a computer, a notebook, a cellular phone, an Internet protocol device, a digital camera, a personal digital assistant (PDA), and a handheld PC. Embedded products can include devices such as network computers (NetPCs), set-top boxes, network hubs, and wide area network (WAN) switches. The method includes the following steps.

[0094] In step S601, the source operand and destination address of the store instruction are obtained.

[0095] In step S602, a first cache unit is established. The size of the cache unit can be predetermined, and the storage space corresponding to the cache unit can be set multiple times, for example, a storage space for a source operand and / or a destination address is added each time when needed. And the cache unit may not be a continuous storage space. Of course, a second cache unit can also be established at the same time to cache discontinuous destination addresses and source operands.

[0096] In step S603, the destination address of the first storage instruction is used as the first address.

[0097] In step S604, it is determined whether the destination address of each storage instruction falls within the address range. The address range of the existing cache units is calculated, and if the destination address of a storage instruction is adjacent to the existing cache unit, step S605 is executed.

[0098] In step S605, the source operand of each storage instruction is stored in the first cache unit, and corresponding indication data and identification data are set accordingly.

[0099] In step S606, it is determined whether the source operand of the first storage instruction needs to be written to the bus. In some embodiments, according to the time requirement of the first storage instruction, it is determined whether the source operand of the first storage instruction needs to be written to the bus. If not, it jumps to step S601 for execution, otherwise it executes S607.

[0100] In step S607, it is determined whether a write burst transfer mode can be initiated. That is, it is determined whether a number of source operands are valid and continuous according to the indication data and the identification data. If both conditions are met, step S608 is executed.

[0101] In step S608, a write burst transfer mode is initiated to transfer data.

[0102] In the burst transmission mode of this embodiment, multiple source operands are transmitted as one data block, which can reduce the handshake delay on the address, thereby improving the write transmission efficiency.

[0103] Furthermore, multiple source operands are combined into write data with a data length equal to the data bit width of the bus, and the multiple write data are transmitted as one data block through the burst transmission mode to further improve the transmission efficiency.

[0104] For the present invention, the above-described processing units, processing systems, and electronic devices may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present invention is not limited thereto. Although various aspects of the present invention may be illustrated and described as block diagrams, flow charts, or using some other graphical representation to illustrate and describe various aspects of the present invention, it is well understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, software, dedicated circuits or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof. If involved, the circuit design of the present invention may be implemented in various components such as integrated circuit modules.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A processing device, the processing device comprising a memory management unit coupled to a memory via a bus, the memory management unit comprising: A first cache unit, used to store a plurality of first source operands and a first write address; A second cache unit, used to store at least one pair of a second source operand and a second destination address; a write cache module, configured to judge the destination addresses of the plurality of storage instructions, store the first addresses of the continuous destination addresses and the plurality of source operands corresponding to the continuous destination addresses as the first write addresses and the plurality of first source operands respectively in the first cache unit, and store the discontinuous destination addresses and the source operands corresponding to the discontinuous destination addresses as the second source operands and the second destination addresses in pairs in the second cache unit; A bus transmission module is used to transmit multiple first source operands and the first write address in the first cache unit to the memory via the bus in a write burst transmission mode, and to transmit each pair of the second source operand and the second destination address in the second cache unit to the memory via the bus in other transmission modes.

2. According to the processing device according to claim 1, the first cache unit also stores indication data and identification data, the indication data is used to indicate whether the multiple first source operands are valid, and the identification data is used to indicate the continuous manner of the destination addresses corresponding to the multiple first source operands.

3. The processing device according to claim 2, wherein the bus transmission module comprises: a burst determination unit, configured to determine whether a write burst transfer mode can be started according to the indication data and the identification data, and to determine whether a destination address corresponding to the plurality of first source operands is an increasing continuous address or a decreasing continuous address; A burst transfer unit is used to transfer the first write address and the multiple first source operands to the bus in a write burst transfer mode when the destination address corresponding to the multiple first source operands is an increasing continuous address; if the destination address corresponding to the multiple first source operands is a decreasing continuous address, then in a write burst transfer mode, send the first write address and an identifier representing the decreasing continuous address and the multiple first source operands to the bus.

4. The processing device according to claim 3, wherein the bus is directly forwarded to the memory, and the memory performs different write operations according to increasing continuous addresses or decreasing continuous addresses. 5 . The processing device according to claim 3 , wherein the bus adjusts the plurality of first source operands from decrementing consecutive addresses to increasing consecutive addresses, and sends the adjusted plurality of first source operands and the first write address to the memory. 6 . The processing device according to claim 1 , wherein the plurality of first source operands are combined into a plurality of write data, each of which has the same data length, and data transmission in a write burst transmission mode is performed in units of write data. 7 . The processing device according to claim 6 , wherein the data length of the write data is equal to the data bit width of the bus.

8. The processing device according to claim 6, wherein the write burst transmission unit further comprises: When the data length of the write data is smaller than the data bit width of the bus, the valid data transmitted to the bus is indicated by a cutoff mark. 9 . The processing device according to claim 1 , wherein the bus transmission module performs data transmission in a write burst transmission mode in a manner of separating addresses and data.

10. The processing device according to claim 1, further comprising: According to the time requirement of the storage instruction corresponding to the first address, it is determined whether the bus transmission module is currently started.

11. The processing device according to claim 1, wherein the write cache module further comprises: The source operands and target addresses of the plurality of storage instructions are obtained from a cache of an LSU component of the instruction pipeline structure. 12 . The processing device according to claim 1 , wherein the processing device is a processor core or a processor, and the bus and the memory are located inside the processing device. 13 . The processing device according to claim 1 , wherein the processing device is a processor core or a processor, and the bus and the memory are located outside the processing device.

14. A memory management method for a processing device, comprising: Loop to get the source operands and destination addresses of multiple storage instructions; storing a plurality of first source operands corresponding to the continuous destination addresses and the first addresses of the continuous destination addresses in a first cache unit in the processing device; storing the discontinuous destination addresses and source operands corresponding to the discontinuous destination addresses as pairs of second source operands and second destination addresses in a second cache unit in the processing device; In a write burst transfer mode, transmitting a plurality of first source operands and the first address in the first cache unit to a memory via a bus; In other transmission modes, each pair of the second source operand and the second destination address in the second cache is transmitted to the memory via the bus in sequence.

15. According to the memory management method of claim 14, the first cache unit also stores indication data and identification data, the indication data is used to indicate whether the multiple first source operands are valid, and the identification data is used to indicate the continuous manner of the destination addresses corresponding to the multiple first source operands.

16. The memory management method according to claim 15, wherein in the write burst transfer mode, transmitting the plurality of first source operands in the first cache unit and the first address to the memory via the bus further comprises: Determining whether a write burst transfer mode can be started according to the indication data and the identification data, and determining whether the destination addresses corresponding to the plurality of first source operands are increasing continuous addresses or decreasing continuous addresses; When the destination addresses corresponding to the plurality of first source operands are increasing consecutive addresses, in a write burst transfer mode, transmitting the first address and the plurality of first source operands to the bus; When the destination addresses corresponding to the multiple first source operands are decrementing continuous addresses, in a write burst transfer mode, the first address, an identifier indicating the decrementing continuous addresses, and the multiple first source operands are sent to the bus.

17. The memory management method according to claim 16, wherein the bus is directly forwarded to the memory, and the memory performs different write operations according to increasing continuous addresses or decreasing continuous addresses.

18. The memory management method according to claim 17, wherein the bus adjusts the plurality of first source operands from decrementing continuous addresses to increasing continuous addresses, and sends the adjusted plurality of first source operands and the first address to the memory.

19. The memory management method according to claim 14, wherein the plurality of first source operands are combined into a plurality of write data, each of which has the same data length, and data transmission in a write burst transmission mode is performed in units of write data.

20. The memory management method according to claim 19, wherein the data length of the write data is equal to the data bit width of the bus.

21. The memory management method according to claim 19, further comprising: When the data length of the write data is smaller than the data bit width of the bus, the valid data transmitted to the bus is indicated by a cutoff mark.

22. The memory management method according to claim 14, further comprising: According to the time requirement of the storage instruction corresponding to the first address, it is determined whether data transmission is currently started.

23. A computer system comprising the processing device according to any one of claims 1 to 13.

24. A system on chip, comprising the processing device according to any one of claims 1 to 13.

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