Method and system for accelerating implementation of complex sequence cross-correlation based on FFT algorithm on FPGA

Abstract

The present invention discloses an accelerated implementation method and system of complex sequence cross-correlation based on FFT algorithm on FPGA, the method comprising the following steps: FFT operation step, using FFT algorithm to convert two complex sequences to be cross-correlated from time domain to frequency domain respectively; conjugate point multiplication operation step, performing conjugate point multiplication operation on two complex sequences that have completed the conversion from time domain to frequency domain in frequency domain; IFFT operation step, using IFFT algorithm to transform the conjugate point multiplication operation result from frequency domain to time domain to obtain a time domain complex sequence; energy calculation step, calculating the energy of each point in the time domain complex sequence obtained by IFFT operation step, and outputting the energy result sequence; judgment step, searching for the maximum energy value obtained in the energy calculation step, the position of the point of the maximum energy value is the position of the maximum correlation point of the two complex sequences. The present invention can greatly reduce the number of multiplication operations, and truly achieve low latency, high efficiency and easy convergence of timing.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and in particular to a method and system for accelerating implementation of complex sequence cross-correlation based on FFT algorithm on FPGA. Background Art

[0002] In the field of signal processing, there are analog signal processing and digital signal processing according to the type of signal being processed. Digital signal processing is a discipline that studies how to represent signals with digital or symbolic sequences and how to process these sequences. Compared with the field of analog signal processing, digital signal processing has the advantages of high precision, high reliability, strong flexibility, convenience for large-scale integration, convenience for encryption processing, and low-frequency signal processing. Due to the characteristics of digital signals themselves and the application of high-speed digital computers and microprocessors, some digital signal processing algorithms have emerged.

[0003] FPGA (Field-Programmable Gate Array) is a field-programmable gate array, which is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. Circuit design is carried out in hardware description language (Verilog or VHDL), which can be quickly burned to FPGA for testing after simple synthesis and layout, and complete the rapid prototyping of products. All logic units of FPGA are driven by clocks, and all circuit behaviors are executed in parallel, which makes FPGA-based algorithms (hardware acceleration) the mainstream.

[0004] In the prior art, similar patent technologies are currently available, such as the patent name: A method for implementing cross-correlation operations based on FPGA, with a publication number of 108089839A, which discloses a method for implementing cross-correlation operations based on FPGA, which has the following two main features: 1. The operation method collects data through an AD sampling module, converts analog signals into digital signals, and then uses the rich hardware resources of FPGA to implement cross-correlation operations of two signals using hardware circuits; 2. This method has higher speed and efficiency than the traditional method of taking out a single data from the RAM address of FPGA for multiplication and accumulation operations, and can make full use of the characteristics of FPGA parallel operations to reduce operation time.

[0005] In the above-mentioned open patent application, the design architecture is as follows Figure 1 As shown in the figure, based on the FPGA hardware platform, two real sequences are obtained after AD acquisition. The system can only process the cross-correlation of the two real sequences, and the operation is directly carried out in the time domain. Specifically, according to the type of sequence, it is divided into real sequence and complex sequence:

[0006] The cross-correlation function of two real discrete time series x(n) and y(n) is defined as:

[0007]

[0008] Define x(n) as a local short sequence, n = 0, 1, ..., N-1, and the length of the short sequence is N;

[0009] Define y(n) as the long sequence to be tested, n = 0, 1, ..., M-1, the length of the long sequence is M;

[0010] The real domain calculation structure of the real sequence x(n) and y(n) is as follows Figure 2 As shown, to complete a cross-correlation calculation of real sequences x(n) and y(n), the number of multiplications required is: N*(MN).

[0011] The cross-correlation function of two complex discrete time series a(n) and y(n) is defined as:

[0012]

[0013] Where a(n) = R a (n)+jI a (n); b(n) = R b (n)+jI b (n)

[0014] Define a(n) as a local short complex sequence, n = 0, 1, ..., N-1, and the short sequence length is N;

[0015] Define b(n) as the long complex sequence to be tested, n = 0, 1, ..., M-1, the length of the long sequence is M;

[0016] Complex sequence related calculation structure such as Figure 3 , Figure 4 As shown, Figure 3 is the real part result, expressed by the formula: R = R a R b +I a I b , Figure 4 The result is a void, expressed by the formula: I = I a R b -R a I b ;

[0017] Calculate the result of complex sequence cross-correlation r ab (τ)=R+jI, the number of multiplications required to complete the cross-correlation calculation of the complex sequences a(n) and b(n) is: 4*N*(MN).

[0018] Through the above calculation process, it can be found that the existing time-domain direct calculation of the cross-correlation of two sequences requires a large number of multiplication operations, occupies a large number of multiplier resources, causes a large system delay, and has poor timing convergence. Therefore, a method that can save multiplier resources and optimize timing is urgently needed to improve the performance of FPGA in realizing cross-correlation. Summary of the invention

[0019] The purpose of the present invention is to provide a method and system for accelerating the implementation of complex sequence cross-correlation on FPGA based on FFT algorithm, so as to solve the problem that the existing implementation of complex sequence cross-correlation occupies a large number of multiplication operations, resulting in a large system delay, poor timing convergence effect, and a great impact on the performance of the entire FPGA system.

[0020] To achieve the above object, the technical solution of the present invention is an accelerated implementation method of complex sequence cross-correlation based on FFT algorithm on FPGA, comprising the following steps:

[0021] FFT operation step, using FFT algorithm to convert two complex sequences to be cross-correlated from time domain to frequency domain;

[0022] A conjugate point multiplication operation step is to perform a conjugate point multiplication operation in the frequency domain on the two complex sequences that have completed the transformation from the time domain to the frequency domain;

[0023] IFFT operation step, using IFFT algorithm to transform the conjugate point multiplication operation result from frequency domain to time domain to obtain a time domain complex sequence;

[0024] The energy calculation step calculates the energy of each point in the time domain complex sequence obtained in the IFFT operation step and outputs an energy result sequence;

[0025] In the decision step, the maximum energy value obtained in the energy calculation step is searched out, and the position of the point of the maximum energy value is the position of the point where the correlation between the two complex sequences is the maximum.

[0026] Furthermore, as an optimal technical solution, it also includes a zero-padding processing step. When the lengths of the two complex sequences are not equal, the zero-padding processing step is used to first perform zero-padding processing on the shorter of the two complex sequences to make the lengths of the two complex sequences equal. After completing the zero-padding processing, FFT operation is performed.

[0027] Furthermore, as a preferred technical solution, in the FFT operation step and the IFFT operation step, the IP core built into the FPGA is used to implement the FFT / IFFT operation.

[0028] Furthermore, as a preferred technical solution, in the FFT operation step, two FFT units are generated by using the CoreGenerator tool built into the FPGA to implement FFT operations on two complex sequences.

[0029] Furthermore, as a preferred technical solution, in the FFT operation step and the IFFT operation step, FPGARTL coding is used to implement FFT / IFFT operations.

[0030] The accelerated implementation system of complex sequence cross-correlation based on FFT algorithm on FPGA includes:

[0031] An FFT operation unit, using an FFT algorithm, is used to convert two complex sequences to be cross-correlated from the time domain to the frequency domain respectively;

[0032] A conjugate point multiplication operation unit is used to perform a conjugate point multiplication operation in the frequency domain on two complex sequences that have completed the conversion from the time domain to the frequency domain;

[0033] An IFFT operation unit, using an IFFT algorithm, is used to transform the conjugate point multiplication operation result from the frequency domain to the time domain to obtain a time domain complex sequence;

[0034] An energy calculation unit, used to calculate the energy of each point in the time domain complex sequence obtained by the IFFT operation step, and output an energy result sequence;

[0035] The decision unit is used to search for the maximum energy value obtained in the energy calculation step. The position of the point of the maximum energy value is the position of the maximum correlation point between the two complex sequences.

[0036] Furthermore, as an optimal technical solution, it also includes a zero-padding processing unit. When the lengths of the two complex sequences are not equal, the zero-padding processing unit first performs zero-padding processing on the shorter of the two complex sequences to make the lengths of the two complex sequences equal. After completing the zero-padding processing, FFT operation is performed.

[0037] Furthermore, as a preferred technical solution, the FFT operation unit and the IFFT operation unit are from an IP core hardware accelerator built into the FPGA to implement FFT / IFFT operations.

[0038] Furthermore, as a preferred technical solution, the FFT operation unit is generated by a Core Generator tool to implement FFT operations on two complex sequences.

[0039] Furthermore, as a preferred technical solution, the FFT operation unit and the IFFT operation unit implement FFT / IFFT operations through FPGA RTL coding.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] (1) The present invention first converts the time domain signal to the frequency domain by using the FFT algorithm, then performs a conjugate point multiplication operation in the frequency domain, and then uses the IFFT algorithm to move the operation result from the frequency domain to the time domain, so as to quickly obtain the complex sequence cross-correlation result. Compared with the existing traditional direct time domain correlation operation, the number of multiplication operations is greatly reduced, and low latency, high efficiency and easy timing convergence are truly achieved. For FPGA hardware, the occupation of multiplier resources is greatly reduced, the FPGA timing is optimized, and hardware resources are saved. The present invention well solves the problem of excessive multiplication operations generated in the existing complex sequence cross-correlation operation process, and can enable the hardware of the FPGA system to perform at its best performance.

[0042] (2) The present invention can be well applied to the radio signal correlation capture process and can greatly improve the system performance, making the single FPGA system have more powerful performance.

[0043] (3) The present invention can simultaneously support the cross-correlation processing of real sequences and complex sequences, and also has the characteristics of low latency, high efficiency, and easy time sequence convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A diagram of the architecture of a method for implementing two-way real sequence cross-correlation for an existing patent;

[0045] Figure 2 It is a real domain calculation structure diagram of real sequence cross-correlation;

[0046] Figure 3 It is a real domain calculation structure diagram of complex sequence cross-correlation based on real part;

[0047] Figure 4 It is a real domain calculation structure diagram of complex sequence cross-correlation based on imaginary part;

[0048] Figure 5 is a flow chart of the method of the present invention;

[0049] Figure 6 It is a structural composition diagram of the present invention;

[0050] Figure 7 This is a structural diagram of the present invention when implementing FFT / IFFT based on FPGA IP core;

[0051] Figure 8 This is a structural diagram of the present invention when implementing FFT / IFFT based on FPGA RTL. DETAILED DESCRIPTION

[0052] The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0053] Example

[0054] like Figure 5 As shown, the accelerated implementation method of complex sequence cross-correlation based on the FFT algorithm on the FPGA described in this embodiment includes the following steps:

[0055] FFT operation step, using FFT algorithm to convert two complex sequences to be cross-correlated from time domain to frequency domain;

[0056] A conjugate point multiplication operation step is to perform a conjugate point multiplication operation in the frequency domain on the two complex sequences that have completed the transformation from the time domain to the frequency domain;

[0057] IFFT operation step, using IFFT algorithm to transform the conjugate point multiplication operation result from frequency domain to time domain to obtain a time domain complex sequence;

[0058] The energy calculation step calculates the energy of each point in the time domain complex sequence obtained in the IFFT operation step and outputs an energy result sequence;

[0059] In the decision step, the maximum energy value obtained in the energy calculation step is searched out, and the position of the point of the maximum energy value is the position of the point where the correlation between the two complex sequences is the maximum.

[0060] The implementation process of the present invention is described in detail below with reference to specific examples.

[0061] Assume that complex sequence a(n) and complex sequence b(n) are two complex sequences to be cross-correlated, the length of complex sequence a(n) is N, and the length of complex sequence b(n) is M. When N>M, it is necessary to perform zero padding processing on the complex sequence b(n), supplementing NM zeros. Conversely, when N<M, it is necessary to perform zero padding processing on the complex sequence a(n), supplementing MN zeros.

[0062] After completing the zero padding process, the two complex sequences are subjected to FFT operation to obtain sequences A(k) and B(1) respectively. The expressions of sequences A(k) and B(1) are as follows:

[0063] A(k)=R A (k)+jI A (k)

[0064] B(l)=R B (l)+jI B (l).

[0065] Perform conjugate point multiplication on sequences A(k) and B(l) to obtain the complex sequence D(m). The expression of the complex sequence D(m) is as follows:

[0066] D(m)=A(m).*B(m)=R A(m)*R B (m)-I A (m)I B (m)+j(R A (m)*I B (m)+R B (m)*I A (m))

[0067] After completing the conjugate point multiplication operation, perform IFFT operation on the complex sequence D(m) to transform the complex sequence D(m) from the frequency domain to the time domain, and output the time domain complex sequence d(n), which is expressed as follows:

[0068] d(n)=R D (n)+jI D (n)

[0069] The energy of each point in the time domain complex sequence d(n) is calculated and the energy result sequence E(n) is output. The expression of E(n) is as follows:

[0070]

[0071] Finally, the search for the maximum energy point is completed. The position of the maximum energy point is the position of the point with the maximum correlation between a(n) and b(n).

[0072] Energy calculation can be implemented through the DSP unit in the FPGA, and judgment can be implemented using two registers, one register is used to store the maximum energy value, such as register flip_flop, and the other register is used to store the position corresponding to the maximum value point.

[0073] The following is a demonstration of the above method, as follows:

[0074] First, the cross-correlation function of the real discrete time series x(n) and y(n) is defined as:

[0075]

[0076] It can be proved that r xy The discrete Fourier transform of (τ) is:

[0077] R xy (k) = X * (k)Y(k); 0≤k≤N-1

[0078] Among them: X(k)=DFT[x(n)], Y(k)=DFT[y(n)], R xy (k) = DFT[r xy (τ)]

[0079] Proof: Substitute the inverse discrete Fourier transform of x(n) and y(n) into the definition of the cross-correlation function

[0080]

[0081] Since x(n) is a real sequence, x(n) = x * (n), get

[0082]

[0083] because

[0084]

[0085] Therefore

[0086]

[0087] The proof is complete.

[0088] The cross-correlation function of complex discrete time series a(n) and b(n) is defined as

[0089]

[0090] According to the properties of DFT, time domain convolution is equivalent to frequency domain multiplication. ab The discrete Fourier transform of (τ) is

[0091] R ab (k) = A * (k)B(k); 0≤k≤N-1

[0092] Where: A(k) = DFT[a(n)], B(k) = DFT[b(n)], R ab (k) = DFT[r ab (τ)]

[0093] like Figure 6 As shown, based on the above method, this embodiment further discloses an accelerated implementation system of complex sequence cross-correlation based on FFT algorithm on FPGA, including:

[0094] An FFT operation unit, using an FFT algorithm, is used to convert two complex sequences to be cross-correlated from the time domain to the frequency domain respectively;

[0095] A conjugate point multiplication unit is used to perform conjugate point multiplication in the frequency domain on two complex sequences that have completed the transformation from the time domain to the frequency domain;

[0096] An IFFT operation unit, using an IFFT algorithm, is used to transform the conjugate point multiplication operation result from the frequency domain to the time domain to obtain a time domain complex sequence;

[0097] The energy calculation unit is used to calculate the energy of each point in the time domain complex sequence obtained by the IFFT operation step. The energy calculation unit can be implemented by using the DSP unit in the FPGA.

[0098] The decision unit is used to search for the maximum energy value obtained in the energy calculation step. The position of the energy maximum point is the position of the maximum correlation point of the two complex sequences. The decision unit can be implemented using two registers, one register is used to store the maximum energy value, such as register flip_flop, and the other register is used to store the position corresponding to the maximum value point.

[0099] On the basis of the above structure, this embodiment further includes a zero-padding processing unit. When the lengths of the two complex sequences are not equal, the zero-padding processing unit first performs zero-padding processing on the shorter of the two complex sequences to make the lengths of the two complex sequences equal. After the zero-padding processing is completed, the FFT operation is performed.

[0100] like Figure 7 As shown, the FFT operation unit and IFFT operation unit of this embodiment come from the IP core hardware accelerator built into the FPGA to implement FFT / IFFT operations. The FPGA has a built-in dedicated FFT / IFFT IP core hardware accelerator. The IPcore does not occupy additional FPGA logic resources, and the timing has been optimized before leaving the factory, and will not cause timing impact on the user's design logic. Specifically, two M-point FFT units can be generated through the Core Generator tool to complete the FFT operation of the complex sequence a(n) and b(n) sequence. In addition, it should be noted that the full name of IP core is Intelligence Property Core, which means intellectual property core. IP Core refers to the logic function block that can be used to generate ASIC and PLD.

[0101] like Figure 8 As shown, the embodiment can also use FPGA RTL coding to implement FFT / IFFT operations, generate FFT / IFFT units through FPGA RTL, and complete hardware acceleration on FPGA. RTL stands for Register Transfer Level, which means register transfer level, and is used to design circuits using hardware description language.

[0102] It can be seen from the above method and structure that when realizing complex sequence correlation, the present invention no longer performs calculations in the time domain, but first converts the time domain signal to the frequency domain using the FFT algorithm, then performs a conjugate point multiplication operation in the frequency domain, and then uses the IFFT algorithm to move the calculation result from the frequency domain to the time domain to quickly obtain the cross-correlation result, that is, completes the fast calculation of cross-correlation in the frequency domain.

[0103] The existing traditional cross-correlation algorithm completes the cross-correlation operation between a short sequence a(n) of length N and a long sequence b(n) of length M, and the number of multiplications required is N*4*(MN).

[0104] Based on the method described in the present invention, the amount of calculation is calculated using the radix 2 / radix 4 FFT algorithm, as follows:

[0105] The number of multiplication operations required to calculate the FFT / IFFT of N points using the radix 2 FFT algorithm is: The entire operation requires two N-point FFTs, one N-point conjugate multiplication operation, and one N-point IFFT operation. The number of multiplication operations required for the entire process is:

[0106] The number of multiplications required to calculate the FFT / IFFT of N points using the radix-4 FFT algorithm is: Similarly, the number of multiplication operations required for the entire process can be calculated as:

[0107] Taking the cross-correlation of a 1024-point long complex sequence and a 256-point short complex sequence as an example, the direct time-domain cross-correlation of the traditional method requires 786,432 multiplications, while the method provided by the present invention only requires 17,920, which is about 2% of the number required for direct time-domain cross-correlation. This greatly reduces the number of multiplication operations, optimizes the FPGA timing, and truly achieves low latency, high efficiency, and easy timing convergence. At the same time, it can also save hardware resources so that the hardware can perform at its best performance. With the development of FPGA technology, the parallel processing characteristics of the FPGA full circuit make the application of algorithms a reality, and by performing RTL code design and simulation as shown in the invention scheme, it can ensure that the circuit behavior is completed in accordance with the algorithm description. In addition, if the present invention is applied to the radio signal correlation capture process, it greatly improves the system performance, making the single FPGA system have more powerful performance.

[0108] In addition, when the imaginary part of the complex sequence is set to 0, the present invention can also complete the cross-correlation processing of the real sequence. Therefore, the present invention can simultaneously support the cross-correlation processing of real sequences and complex sequences, and also has the characteristics of low latency, high efficiency and easy timing convergence.

[0109] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. An accelerated implementation method of complex sequence cross-correlation based on FFT algorithm on FPGA, characterized in that: The following steps are involved: FFT operation step, using FFT algorithm to convert two complex sequences to be cross-correlated from time domain to frequency domain; A conjugate point multiplication operation step is to perform a conjugate point multiplication operation in the frequency domain on the two complex sequences that have completed the transformation from the time domain to the frequency domain; IFFT operation step, using IFFT algorithm to transform the conjugate point multiplication operation result from frequency domain to time domain to obtain a time domain complex sequence; The energy calculation step calculates the energy of each point in the time domain complex sequence obtained in the IFFT operation step and outputs an energy result sequence; The decision step is to search for the maximum energy value obtained in the energy calculation step. The location of the point with the maximum energy value is the location of the point with the maximum correlation between the two complex sequences. In the FFT operation step and the IFFT operation step, the IP core built into the FPGA is used to implement the FFT / IFFT operation; In the FFT operation step, two FFT units are generated by using the Core Generator tool built into the FPGA to implement the FFT operation of two complex sequences.

2. The method for accelerating the implementation of complex sequence cross-correlation based on FFT algorithm on FPGA according to claim 1, characterized in that: The method further includes a zero-padding processing step. When the lengths of the two complex sequences are not equal, the zero-padding processing step is used to firstly perform zero-padding processing on the shorter of the two complex sequences to make the lengths of the two complex sequences equal. After the zero-padding processing is completed, the FFT operation is performed.

3. The method for accelerating the implementation of complex sequence cross-correlation based on FFT algorithm on FPGA according to claim 1, characterized in that: In the FFT operation step and the IFFT operation step, FPGA RTL coding is used to implement FFT / IFFT operation.

4. The accelerated implementation system of complex sequence cross-correlation based on FFT algorithm on FPGA is characterized by: include: An FFT operation unit, using an FFT algorithm, is used to convert two complex sequences to be cross-correlated from the time domain to the frequency domain respectively; A conjugate point multiplication operation unit is used to perform a conjugate point multiplication operation in the frequency domain on two complex sequences that have completed the conversion from the time domain to the frequency domain; An IFFT operation unit, using an IFFT algorithm, is used to transform the conjugate point multiplication operation result from the frequency domain to the time domain to obtain a time domain complex sequence; An energy calculation unit, used to calculate the energy of each point in the time domain complex sequence obtained by the IFFT operation step, and output an energy result sequence; A decision unit is used to search for the maximum energy value obtained in the energy calculation step, and the position of the point of the maximum energy value is the position of the maximum correlation point between the two complex sequences; The FFT operation unit and the IFFT operation unit are from the IP core hardware accelerator built into the FPGA, and are used to implement FFT / IFFT operations; The FFT operation unit is generated by a Core Generator tool and is used to implement FFT operations of two complex sequences.

5. The accelerated implementation system of complex sequence cross-correlation based on FFT algorithm on FPGA according to claim 4, characterized in that: It also includes a zero-padding processing unit. When the lengths of the two complex sequences are not equal, the zero-padding processing unit first performs zero-padding processing on the shorter of the two complex sequences to make the lengths of the two complex sequences equal. After completing the zero-padding processing, FFT operation is performed.

6. The accelerated implementation system of complex sequence cross-correlation based on FFT algorithm on FPGA according to claim 5, characterized in that: The FFT operation unit and the IFFT operation unit implement FFT / IFFT operations through FPGA RTL coding.

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