A structure and method of multi-layer epitaxial super junction structure VDMOS

Abstract

The present invention provides a structure of a multi-layer epitaxial super junction VDMOS and a method thereof, comprising a drain, a substrate is arranged above the drain, an n-type drift region is arranged above the substrate, a p-type block is arranged inside the n-type drift region, a p-type well is arranged above the p-type block, an n+ type source region and a p+ type short circuit region are arranged inside the p-type well, a gate oxide layer is arranged on the top of the p-type well, a lateral p-type block perpendicular to the direction of a strip polycrystalline layer is arranged in the n-type drift region, a p-type block region of a main pressure-bearing layer is perpendicular to the extension direction of the p-type well, so that the length of the p-type block is no longer a factor limiting the size of a unit cell, and the size of a unit cell is completely determined by the length of the interval between the polycrystalline layers, and at the same time, the advancement process steps after the first etching, the second etching, and the third etching of the original process are integrated into after the third etching, and the three advancements of the original manufacturing process are integrated into one advancement, which greatly saves process time and cost.

Description

Technical Field

[0001] The present invention relates to the technical field of VDMOS, and in particular to a structure of a multi-layer epitaxial super junction structure VDMOS and a method thereof. Background Art

[0002] At present, my country's new power electronic devices mainly include VDMOS and IGBT devices. In high-voltage and high-current application scenarios, the conventional VDMOS has a large on-resistance, which leads to a significant increase in conduction loss. The superjunction structure VDMOS has a unique charge balance structure, which can greatly reduce the on-resistance while ensuring the voltage, thereby improving the conduction loss. The multi-layer epitaxial superjunction VDMOS process is easier to implement and has a stable process than the deep trench superjunction structure, and is sought after by major manufacturers. How to reduce the unit cell size and process cost has become the direction of progress in multi-layer epitaxial superjunction technology. Summary of the invention

[0003] The embodiment of the present invention provides a structure of a multi-layer epitaxial super junction structure VDMOS and a method thereof. By setting a lateral p-type block perpendicular to the direction of a strip polycrystalline layer in an n-type drift region, the p-type block region of the main pressure-bearing layer is perpendicular to the extension direction of the p-type well, so that the length of the p-type block is no longer a factor limiting the size of a unit cell. The size of the unit cell is completely determined by the length of the interval between the polycrystalline layers. At the same time, the advancement process steps after the first etching, the second etching, and the third etching of the original process are integrated into after the third etching, and the three advancements of the original manufacturing process are integrated into one advancement, which greatly saves process time and cost.

[0004] In view of the above problems, the technical solution proposed by the present invention is:

[0005] A multi-layer epitaxial super junction structure VDMOS structure comprises a drain, a substrate is arranged above the drain, an n-type drift region is arranged above the substrate, a p-type block is arranged inside the n-type drift region, a p-type well is arranged above the p-type block, an n+ type source region and a p+ type short circuit region are arranged inside the p-type well, a gate oxide layer is arranged on the top of the p-type well, a gate polycrystalline layer is arranged above the gate oxide layer, a source oxide layer is arranged above the gate polycrystalline layer, and a source metal is arranged above the source oxide layer.

[0006] In order to better implement the technical solution of the present invention, the following technical measures are also adopted.

[0007] Furthermore, the n-type drift region is formed through five epitaxial processes.

[0008] Furthermore, the number of the p-type blocks is at least greater than one, and the p-type blocks are uniformly arranged vertically inside the n-type drift region.

[0009] Furthermore, the n-type drift region is generated on the substrate surface by chemical vapor deposition.

[0010] A multi-layer epitaxial super junction structure VDMOS method, comprising the following steps:

[0011] S1, setting the doping region for the first time, growing an n-type drift region on the substrate surface by chemical vapor deposition;

[0012] S2, first photolithography, photolithography a first layer of p-type block injection window on the top of the n-type drift region through a photolithography process; after ion implantation into the n-type drift region, a first layer of p-type block is formed; after removing the p-type block injection window, ion implantation is performed into the n-type drift region to form a first layer of n-type block;

[0013] S3, setting the doping region for the second time, growing the n-type drift region on the surface of the substrate by chemical vapor deposition; performing photolithography for the second time, photolithography a second layer of p-type block injection window on the top of the n-type drift region by photolithography; injecting into the n-type drift region by ion implantation to form a second layer of p-type block; removing the p-type block injection window, injecting into the n-type drift region by ion implantation to form a second layer of n-type block;

[0014] S4, setting a doping region for the third time, growing an n-type drift region on the surface of the substrate by chemical vapor deposition, performing photolithography for the third time, photolithography a third layer of p-type block injection window on the top of the n-type drift region by photolithography; after injecting into the n-type drift region by ion implantation, forming a third layer of p-type block; after removing the p-type block injection window, injecting into the n-type drift region by ion implantation, forming a third layer of n-type block;

[0015] S5, setting a doping region for the fourth time, growing an n-type drift region on the surface of the substrate by chemical vapor deposition, performing photolithography for the fourth time, photolithography a fourth layer of p-type block injection window on the top of the n-type drift region by photolithography; injecting into the n-type drift region by ion implantation to form a fourth layer of p-type block; removing the p-type block injection window, injecting into the n-type drift region by ion implantation to form a fourth layer of n-type block;

[0016] S6, setting a doping region for the fifth time, growing an n-type drift region on the substrate surface by chemical vapor deposition;

[0017] S7, the first etching, high temperature oxidation growth 12000A initial oxide layer, etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation;

[0018] S8, the second etching, etching the n-type injection window on the top of the n-type drift region through the etching process; n-type ion implantation, high temperature 1100 ° C growth gate oxide layer, chemical vapor deposition polycrystalline layer;

[0019] S9, a third etching, etching a p-type well injection window on the polycrystalline layer through an etching process, and injecting p-type ions;

[0020] S10, high temperature advancement, 1150°C high temperature advancement, the p-type block is connected to the p-type guard ring and the p-type well;

[0021] S11, the fourth etching, through the etching process, etching out the n+ type source injection window, n+ ion implantation, chemical vapor deposition oxide layer;

[0022] S12, the fifth etching, etching out the source contact hole through the etching process, implanting p+ ions, annealing at 875°C in a nitrogen atmosphere for 30 minutes; depositing Ti+TiN, and low-temperature rapid annealing;

[0023] S13, setting a contact window, removing the back side of the substrate and setting a metal material layer to form a drain; setting a source metal and a source oxide layer on the top of the completed structure to form a source and a gate respectively.

[0024] Furthermore, only one high-temperature push is required after the first etching, the second etching, and the third etching are completed.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] 1. When the n-type drift region and the p-type block are subjected to the reverse voltage from the source to the drain, they deplete each other due to the charge balance principle, forming a space charge region to bear the reverse voltage, thereby reducing the resistivity of the n-type drift region and the substrate 2. The lower the resistivity of the n-type drift region and the substrate, the smaller the on-resistance is when it is in the on state, reducing the conduction loss.

[0027] 2. By setting a lateral p-type block perpendicular to the direction of the strip polycrystalline layer in the n-type drift region, the p-type block area of ​​the main pressure-bearing layer is perpendicular to the extension direction of the p-type well, so that the length of the p-type block is no longer a factor limiting the size of the unit cell. The size of the unit cell is completely determined by the length of the interval between the polycrystalline layer and the polycrystalline layer. At the same time, the advancement process steps after the first etching, the second etching, and the third etching of the original process are integrated into one advancement after the third etching, which greatly saves process time and cost.

[0028] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1This is a schematic diagram of a first structure of step S1 disclosed in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a first structure of step S2 disclosed in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of a first structure of step S3 disclosed in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of a first structure of step S4 disclosed in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of a first structure of step S5 disclosed in an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of a first structure of step S6 disclosed in an embodiment of the present invention;

[0035] Figure 7 This is a schematic diagram of a first structure of step S7 disclosed in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of a first structure of step S8 disclosed in an embodiment of the present invention;

[0037] Fig. 9 This is a schematic diagram of a first structure of step S9 disclosed in an embodiment of the present invention;

[0038] Fig.10 This is a schematic diagram of a first structure of step S10 disclosed in an embodiment of the present invention;

[0039] Fig.11 This is a schematic diagram of a first structure of step S11 disclosed in an embodiment of the present invention;

[0040] Fig.12 This is a schematic diagram of a first structure of step S12 disclosed in an embodiment of the present invention;

[0041] Fig.13 This is a schematic diagram of a first structure of step S13 disclosed in an embodiment of the present invention;

[0042] Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure;

[0043] Fig.15 The present invention discloses a method flow chart of a multi-layer epitaxial superjunction structure VDMOS according to an embodiment of the present invention.

[0044] Figure numerals: 1-drain; 2-substrate; 3-n-type buffer; 4-p-type block; 5-p-type well; 6-gate oxide layer; 7-gate polycrystalline layer; 8-source oxide layer; 9-source metal; 10-n+ type source region; 11-p+ type short circuit region. Specific embodiments

[0045] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0046] Refer to the attached Figure 1-14 As shown, a structure of a multi-layer epitaxial super junction structure VDMOS includes a drain 1, a substrate 2 is arranged above the drain 1, an n-type drift region 3 is arranged above the substrate 2, the n-type drift region 3 is formed by five epitaxial processes, the n-type drift region 3 is generated on the surface of the substrate 2 by chemical vapor deposition, a p-type block 4 is arranged inside the n-type drift region 3, the number of the p-type blocks 4 is at least greater than one, and they are uniformly arranged inside the n-type drift region 3 in the longitudinal direction, a p-type well 5 is arranged above the p-type block 4, an n+ type source region 10 and a p+ type short-circuit region 11 are arranged inside the p-type well 5, a gate oxide layer 6 is arranged on the top of the p-type well 5, a gate polycrystalline layer 7 is arranged above the gate oxide layer 6, a source oxide layer 8 is arranged above the gate polycrystalline layer 7, and a source metal 9 is provided above the source oxide layer 8.

[0047] The embodiment of the present invention is also implemented through the following technical solutions.

[0048] Refer to the attached Figure 1-15 As shown, the present invention also proposes a method for multi-layer epitaxial super junction structure VDMOS, comprising the following steps:

[0049] S1, setting the doping region for the first time, growing an n-type drift region on the surface of the substrate 2 by chemical vapor deposition;

[0050] S2, first photolithography, photolithography to form a first layer of p-type block 4 injection window on the top of the n-type drift region through a photolithography process; after being injected into the n-type drift region 3 through an ion implantation method, a first layer of p-type block 4 is formed; after removing the injection window of the p-type block 4, an ion implantation method is used to implant into the n-type drift region 3 to form a first layer of n-type block;

[0051] S3, setting the doping region for the second time, growing the n-type drift region on the surface of the substrate 2 by chemical vapor deposition, performing photolithography for the second time, photolithography a second layer of p-type block 4 injection window on the top of the n-type drift region by photolithography; after injecting into the n-type drift region 3 by ion implantation, forming the second layer of p-type block 4; after removing the injection window of the p-type block 4, injecting into the n-type drift region 3 by ion implantation, forming the second layer of n-type block;

[0052] S4, setting the doping region for the third time, growing the n-type drift region on the surface of the substrate 2 by chemical vapor deposition, performing photolithography for the third time, photolithography a third layer of p-type block 4 injection window on the top of the n-type drift region by photolithography; after injecting into the n-type drift region 3 by ion implantation, forming the third layer of p-type block 4; after removing the injection window of the p-type block 4, injecting into the n-type drift region 3 by ion implantation, forming the third layer of n-type block;

[0053] S5, setting the doping region for the fourth time, growing the n-type drift region on the surface of the substrate 2 by chemical vapor deposition, performing photolithography for the fourth time, photolithography a fourth layer of p-type block 4 injection window on the top of the n-type drift region by photolithography; after injecting into the n-type drift region 3 by ion implantation, forming the fourth layer of p-type block 4; after removing the injection window of the p-type block 4, injecting into the n-type drift region 3 by ion implantation, forming the fourth layer of n-type block;

[0054] S6, setting a doping region for the fifth time, growing an n-type drift region on the surface of the substrate 2 by chemical vapor deposition;

[0055] S7, the first etching, high temperature oxidation growth 12000A initial oxide layer, etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation;

[0056] S8, the second etching, etching the n-type injection window on the top of the n-type drift region through the etching process; n-type ion implantation, high temperature 1100 ° C growth gate oxide layer, chemical vapor deposition polycrystalline layer;

[0057] S9, a third etching, etching a p-type well 5 injection window on the polycrystalline layer through an etching process, and implanting p-type ions;

[0058] S10, high temperature advancement, 1150°C high temperature advancement, the p-type block 4 is connected to the p-type guard ring and the p-type well 5, and only one high temperature advancement is required after the first etching, the second etching, and the third etching are completed;

[0059] S11, the fourth etching, through the etching process, etching out the n+ type source injection window, n+ ion implantation, chemical vapor deposition oxide layer;

[0060] S12, the fifth etching, etching out the source contact hole through the etching process, implanting p+ ions, annealing at 875°C in a nitrogen atmosphere for 30 minutes; depositing Ti+TiN, and low-temperature rapid annealing;

[0061] S13, setting a contact window, removing the back side of the substrate 2 and setting a metal material layer to form a drain 1; setting a source metal 9 and a source oxide layer 8 on the top of the completed structure to form a source and a gate respectively.

[0062] Specifically, when the n-type drift region 3 and the p-type block 4 are subjected to the reverse voltage from the source to the drain 1, they deplete each other due to the charge balance principle, forming a space charge region to bear the reverse voltage, thereby reducing the resistivity of the n-type drift region 3 and the substrate 2. The lower the resistivity of the n-type drift region 3 and the substrate 2, the smaller the on-resistance is when they are in the on state, and the conduction loss is reduced. By setting a lateral p-type block 4 perpendicular to the direction of the strip polycrystalline layer in the n-type drift region 3, the main pressure-bearing layer p-type block 4 area is perpendicular to the extension direction of the p-type well 5, so that the length of the p-type block 4 is no longer a factor limiting the size of the unit cell. The size of the unit cell is completely determined by the length of the interval between the polycrystalline layer and the polycrystalline layer. At the same time, the advancement process steps after the first etching, the second etching, and the third etching of the original process are integrated into after the third etching, and the three advancements of the original manufacturing process are integrated into one advancement, which greatly saves process time and cost.

[0063] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A multi-layer epitaxial superjunction VDMOS structure, characterized in that: A device comprising a drain, a substrate is disposed above the drain, an n-type drift region is disposed above the substrate, a p-type block is disposed inside the n-type drift region, a p-type well is disposed above the p-type block, an n+ type source region and a p+ type short circuit region are disposed inside the p-type well, a gate oxide layer is disposed on the top of the p-type well, a gate polycrystalline layer is disposed above the gate oxide layer, a source oxide layer is disposed above the gate polycrystalline layer, and a source metal is disposed above the source oxide layer; A method for forming a multi-layer epitaxial super junction structure VDMOS comprises the following steps: S1, setting the doping region for the first time, growing an n-type drift region on the substrate surface by chemical vapor deposition; S2, first photolithography, photolithography a first layer of p-type block injection window on the top of the n-type drift region through a photolithography process; after ion implantation into the n-type drift region, a first layer of p-type block is formed; after removing the p-type block injection window, ion implantation is performed into the n-type drift region to form a first layer of n-type block; S3, setting the doping region for the second time, growing the n-type drift region on the surface of the substrate by chemical vapor deposition; performing photolithography for the second time, photolithography a second layer of p-type block injection window on the top of the n-type drift region by photolithography; injecting into the n-type drift region by ion implantation to form a second layer of p-type block; removing the p-type block injection window, injecting into the n-type drift region by ion implantation to form a second layer of n-type block; S4, setting a doping region for the third time, growing an n-type drift region on the surface of the substrate by chemical vapor deposition, performing photolithography for the third time, photolithography a third layer of p-type block injection window on the top of the n-type drift region by photolithography; after injecting into the n-type drift region by ion implantation, forming a third layer of p-type block; after removing the p-type block injection window, injecting into the n-type drift region by ion implantation, forming a third layer of n-type block; S5, setting a doping region for the fourth time, growing an n-type drift region on the surface of the substrate by chemical vapor deposition, performing photolithography for the fourth time, photolithography a fourth layer of p-type block injection window on the top of the n-type drift region by photolithography; injecting into the n-type drift region by ion implantation to form a fourth layer of p-type block; removing the p-type block injection window, injecting into the n-type drift region by ion implantation to form a fourth layer of n-type block; S6, setting a doping region for the fifth time, growing an n-type drift region on the substrate surface by chemical vapor deposition; S7, the first etching, high temperature oxidation growth 12000A initial oxide layer, etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation; S8, the second etching, etching the n-type injection window on the top of the n-type drift region through the etching process; n-type ion implantation, high temperature 1100 ° C growth gate oxide layer, chemical vapor deposition polycrystalline layer; S9, a third etching, etching a p-type well injection window on the polycrystalline layer through an etching process, and injecting p-type ions; S10, high temperature advancement, 1150°C high temperature advancement, the p-type block is connected to the p-type guard ring and the p-type well; S11, the fourth etching, through the etching process, etching out the n+ type source injection window, n+ ion implantation, chemical vapor deposition oxide layer; S12, the fifth etching, etching out the source contact hole through the etching process, p+ ion implantation, annealing at 875°C in a nitrogen atmosphere for 30 minutes; depositing Ti+TiN, and low-temperature rapid annealing; S13, setting a contact window, removing the back side of the substrate and setting a metal material layer to form a drain; setting a source metal and a source oxide layer on the top of the completed structure to form a source and a gate respectively.

2. The structure of a multi-layer epitaxial super junction structure VDMOS according to claim 1, characterized in that: The n-type drift region is formed by five epitaxial processes.

3. The structure of a multi-layer epitaxial super junction structure VDMOS according to claim 1, characterized in that: The number of the p-type blocks is at least greater than one, and the p-type blocks are uniformly arranged inside the n-type drift region in the longitudinal direction.

4. The structure of a multi-layer epitaxial superjunction VDMOS according to claim 1, characterized in that: The n-type drift region is generated on the substrate surface by chemical vapor deposition.

5. The structure of a multi-layer epitaxial super junction structure VDMOS according to claim 1, characterized in that: After the first etching, the second etching and the third etching are completed, only one high-temperature push is required.

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