A two-dimensional semiconductor transistor structure with controllable performance and preparation method thereof

Abstract

The present invention belongs to the field of semiconductor device technology, specifically a two-dimensional semiconductor transistor structure with controllable performance and a preparation method thereof. The present invention includes a substrate, a two-dimensional semiconductor material located on the substrate, a source-drain metal electrode, an oxide dielectric layer, and a laminated metal gate located on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer, and the laminated metal gate is a double-layer metal gate structure of a bottom active metal and a top inert metal. The present invention utilizes the solid-phase diffusion reaction that occurs when the bottom active metal directly contacts the oxide dielectric layer I to form a double-layer dielectric layer, and by controlling the thickness of the bottom active metal, the carrier concentration of the two-dimensional semiconductor material is precisely controlled by the electric dipole effect. The present invention can adjust the threshold voltage of the two-dimensional semiconductor field effect transistor, improve the switching ratio and on-state current of the device, and has broad application prospects in the manufacture of large-scale digital integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and specifically relates to a two-dimensional semiconductor transistor structure with controllable performance and a preparation method thereof. Background Art

[0002] Since the first discovery of graphene, two-dimensional semiconductor materials have attracted widespread attention due to their special layered structure and outstanding electrical properties. Two-dimensional semiconductor materials have a large bandgap width range, which can not only overcome the short channel effect and quantum effect, maintain a good switching frequency, but also improve and enhance the performance of many existing electronic components. Currently, the two-dimensional semiconductor materials prepared by mechanical exfoliation or chemical vapor deposition mainly include MoS2, MoTe2, WSe2, WS2, h-BN and black phosphorus. Its good electrical and optoelectronic properties are conducive to the preparation of high-performance logic devices, sensors and memories, and are used in the manufacture of large-area cascade logic circuits.

[0003] Traditional semiconductor materials use ion doping methods to dope carriers and regulate electrical properties. However, due to the atomic-level channel thickness and stable crystal structure of two-dimensional semiconductor materials, ion doping can easily cause lattice damage to two-dimensional semiconductor materials, introduce interface states and defect states, and is not conducive to improving device performance. Summary of the invention

[0004] The purpose of the present invention is to provide a two-dimensional semiconductor transistor structure with controllable performance and a preparation method thereof, so as to solve the prior art problem of difficulty in carrier doping in two-dimensional semiconductor materials mentioned in the background technology.

[0005] The performance-controllable two-dimensional semiconductor transistor structure provided by the present invention comprises a substrate, a two-dimensional semiconductor material located on the substrate, a source-drain metal electrode, an oxide dielectric layer and a stacked metal gate located on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer, comprising a dielectric layer I and a dielectric layer II, the stacked metal gate is a double-layer metal gate structure of a bottom active metal and a top inert metal, and the dielectric layer II is formed by a solid-phase diffusion reaction between the dielectric layer I and the bottom active metal.

[0006] In the present invention:

[0007] The substrate is any one of a glass substrate, a sapphire substrate, a quartz substrate, a silicon substrate or a flexible substrate.

[0008] The dielectric layer I is an oxide dielectric layer with a high dielectric constant: any one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide or tantalum oxide.

[0009] The bottom active metal grid is an active metal that is easy to oxidize: any one of aluminum, magnesium, zinc, iron or titanium; the top inert metal grid is an inert metal: any one of gold, platinum, silver or copper.

[0010] The thickness of the bottom active metal is precisely controlled according to the required transistor performance requirements, and the thickness of the active metal ranges from 0.1 nm to 5 nm; the thickness of the top inert metal is greater than 5 nm.

[0011] The thickness of the dielectric layer II is in the range of 0.1 nm to 5 nm.

[0012] The method for preparing a two-dimensional semiconductor transistor structure with controllable performance provided by the present invention comprises the following specific steps:

[0013] (1) Preparation of two-dimensional semiconductor materials on the substrate surface;

[0014] (2) defining source and drain electrode regions on the two-dimensional semiconductor material through a masking layer, and performing source and drain metal deposition to prepare source and drain metal electrodes;

[0015] (3) Using a masking layer to define the channel region and etching away the two-dimensional semiconductor material outside the channel;

[0016] (4) In-situ deposition of a dielectric layer I on the surface of the two-dimensional semiconductor material;

[0017] (5) A masking layer is used to define a gate electrode region on the surface of dielectric layer I. Under high vacuum conditions, the bottom active metal is first deposited, and the top inert metal is immediately deposited without destroying the high vacuum state to prepare a stacked gate structure;

[0018] (6) After the device is fabricated, low-temperature annealing is performed in an inert gas environment to promote solid-phase diffusion reaction between the underlying active metal and dielectric layer I;

[0019] (7) The device obtained in the above steps is placed in an inert gas environment for 7-15 days to allow the bottom active metal to undergo a solid phase diffusion reaction with the dielectric layer I, and the bottom active metal is oxidized to form the dielectric layer II.

[0020] In step (1) of the present invention, the preparation method of the two-dimensional semiconductor material includes "bottom-up" chemical vapor deposition, physical vapor deposition or atomic layer deposition, and "bottom-up" micromechanical stripping, ion intercalation stripping or ultrasonic stripping.

[0021] In step (2), step (3) or step (5) of the present invention, the masking layer is a photoresist or a mask.

[0022] Preferably, the masking layer is patterned by using a photolithography process to pattern the photoresist by exposure, development and the like; or by using a mask to pattern the mask containing the electrode pattern closely against the surface of the two-dimensional semiconductor material.

[0023] In step (2) or step (5) of the present invention, the metal electrode deposition method is a vacuum evaporation or sputtering coating method.

[0024] In step (3) of the present invention, the channel etching method is dry etching commonly used in the art, such as plasma etching, reactive ion etching or ion sputtering etching.

[0025] In step (4) of the present invention, the dielectric layer I is an oxide dielectric layer with a high dielectric constant, such as hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide or tantalum oxide; the growth method of the dielectric layer I is atomic layer deposition, chemical vapor deposition or physical vapor deposition.

[0026] In step (5) of the present invention, the bottom active metal gate is an active metal that is easily oxidized, such as aluminum, magnesium, zinc, iron or titanium; and the top inert metal gate is an inert metal, such as gold, platinum, silver or copper.

[0027] Preferably, the thickness of the bottom active metal is precisely controlled according to the desired transistor performance requirements, and the thickness of the active metal ranges from 0.1 nm to 5 nm; the thickness of the top inert metal is greater than 5 nm.

[0028] In step (6) or step (7) of the present invention, the inert gas is argon, xenon, helium or neon.

[0029] In step (6) of the present invention, the low-temperature annealing is annealing at a temperature range of 50°C to 80°C for 10 minutes to 6 hours.

[0030] In step (7) of the present invention, the dielectric layer II is formed by: a solid phase diffusion reaction occurs when the bottom active metal is in direct contact with the dielectric layer I, and metal atoms in the bottom active metal and oxygen atoms in the dielectric layer I are combined through solid phase diffusion to form an oxide, namely, the dielectric layer II. The thickness of the dielectric layer II ranges from 0.1 nm to 5 nm.

[0031] The two-dimensional semiconductor transistor structure designed by the present invention has the following advantages and effects compared with the prior art: a double-layer dielectric layer is formed by the solid-phase diffusion reaction between the bottom active metal and the oxide dielectric layer I in direct contact, and the thickness of the bottom active metal is controlled to control the number of oxygen atoms in the oxide dielectric layer I consumed by its oxidation reaction and the degree of the electric dipole effect subsequently generated by the oxygen vacancies, so that the carrier concentration of the two-dimensional semiconductor material is precisely regulated by the electric dipole effect. Compared with the traditional ion doping method, the electric dipole effect generated by the solid-phase diffusion reaction between the active metal and the oxide dielectric layer adopted by the present invention can reduce the lattice damage caused by doping; at the same time, the present invention can precisely regulate the carrier doping concentration of the two-dimensional semiconductor material by controlling the thickness of the active metal and covering it with an inert metal, thereby solving the problem that the electrical performance of the two-dimensional semiconductor field effect transistor is difficult to adjust. The present invention can adjust the threshold voltage of the two-dimensional semiconductor field effect transistor, improve the switching ratio and on-state current of the device, and has broad application prospects in the manufacture of large-scale digital integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of the semiconductor device and the stacked gate of the present invention, wherein (a) is a top view of the transistor, and (b) is a side view of the transistor.

[0033] Figure 2 It is a schematic diagram of the electric dipole effect induced by the oxide dielectric layer II formed by the solid phase diffusion reaction between the bottom active metal and the dielectric layer I and the oxygen vacancies generated in the dielectric layer I in the present invention.

[0034] The numbers in the figure are: 1 is the substrate, 2 is the two-dimensional semiconductor material, 3 is the source and drain metal electrodes, 4 is the dielectric layer I, 5 is the bottom active metal, 6 is the top inert metal, 7 is the electric dipole, and 8 is the dielectric layer II. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar materials or methods with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art will appreciate the applicability of other processes and / or the use of other materials.

[0036] An embodiment of the present invention provides a two-dimensional semiconductor transistor structure with controllable performance, such as Figure 1As shown, the laminated metal gate includes a substrate 1, a two-dimensional semiconductor material 2 located on the substrate, a source-drain metal electrode 3, a dielectric layer 14, a bottom active metal 5, and a top inert metal 6. The dielectric layer 14 is an oxide dielectric layer with a high dielectric constant, and the laminated metal gate is a double-layer metal gate structure of a bottom active metal 5 and a top inert metal 6.

[0037] Figure 2 FIG. 4 shows the electric dipole effect induced by the oxide dielectric layer II8 formed by the solid phase diffusion reaction between the bottom active metal gate 5 and the dielectric layer I4 and the oxygen vacancies generated in the dielectric layer I4 in the present invention.

[0038] like Figure 1 The device structure shown in FIG. 1 is prepared in the following specific steps:

[0039] First, prepare a two-dimensional semiconductor material 2 on the surface of a substrate 1. The substrate 1 is a commonly used substrate in the art, such as a sapphire substrate, a quartz substrate, a silicon substrate, a glass substrate or any one of flexible substrates; the preparation method of the two-dimensional semiconductor material 2 is a "bottom-up" chemical vapor deposition, physical vapor deposition or atomic layer deposition method, as well as a "bottom-up" micromechanical stripping method, ion intercalation stripping method or ultrasonic stripping method. As a specific example, in this embodiment, sapphire is selected as the substrate 1, and the two-dimensional semiconductor material 2 is prepared by chemical vapor deposition. The two-dimensional semiconductor material 2 selected in this embodiment is molybdenum disulfide.

[0040] Secondly, define the structure of the source-drain metal electrode 3. The source-drain electrode region is defined on the two-dimensional semiconductor material 2 by a masking layer, and the masking layer is a photoresist or a mask. The masking layer is patterned by using a photolithography process, and the photoresist is patterned by means of exposure, development, etc.; or a mask is used to pattern the mask containing the electrode pattern close to the surface of the two-dimensional semiconductor material 2. Then, the source-drain metal electrode 3 is prepared by vacuum evaporation or sputtering. As a specific example, in this embodiment, a photolithography process is selected, and a photoresist is used as a masking layer. The pattern of the source-drain region is obtained on the surface of the molybdenum disulfide of the two-dimensional semiconductor material 2 by exposure and development, and the source-drain metal electrode 3 is prepared by electron beam evaporation coating method, and the source-drain metal electrode 3 is a gold electrode with a thickness of 35 nm.

[0041] Then, define the channel pattern of the two-dimensional semiconductor material 2. Use a masking layer to define a channel region on the two-dimensional semiconductor material 2, and etch away the two-dimensional semiconductor material 2 outside the channel. The etching method is a dry etching commonly used in the art, such as plasma etching, reactive ion etching or ion sputtering etching. As a specific example, in this embodiment, inductively coupled plasma etching is used to etch the molybdenum disulfide of the two-dimensional semiconductor material 2 outside the channel.

[0042] Next, a dielectric layer I4 is in-situ deposited on the surface of the two-dimensional semiconductor material 2. The dielectric layer I4 is an oxide dielectric layer with a high dielectric constant, such as any one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide or tantalum oxide; the dielectric layer I4 is grown by atomic layer deposition, chemical vapor deposition or physical vapor deposition. As a specific example, in this embodiment, the dielectric layer I4 is prepared by atomic layer deposition, and the dielectric layer I4 selected in this embodiment is hafnium oxide.

[0043] A stacked gate structure of a bottom active metal 5 and a top inert metal 6 with controllable thickness is deposited on the surface of the dielectric layer I4. The preparation method of the stacked gate structure is: using a masking layer to define the gate electrode area; under high vacuum conditions, vacuum evaporation or sputtering coating is used to deposit the bottom active metal 5, and the bottom active metal 5 is any one of aluminum, magnesium, zinc, iron or titanium; then, without destroying the high vacuum, vacuum evaporation or sputtering coating is continued to be used to deposit the top inert metal 6, and the top inert metal 6 is any one of gold, platinum, silver or copper. The thickness of the bottom active metal is precisely controlled according to the required transistor performance requirements, and the thickness of the active metal ranges from 0.1 nm to 5 nm; the thickness of the top inert metal is greater than 5 nm. As a specific example, in this embodiment, a photolithography process is used to define the gate electrode area, and at 1×10 -5 Under the high vacuum condition of 1×10 Pa, the bottom active metal 5 is deposited by electron beam evaporation coating method. The bottom active metal 5 selected in this embodiment is aluminum with a thickness of 2 nm, and its thickness can be accurately adjusted according to the carrier doping requirements of the transistor; then, without destroying the high vacuum, the target material in the cavity is automatically replaced with an inert metal target material through the mechanical control system inside the electron beam evaporation device. -5 Under the high vacuum condition of 1.577 Å, the top layer of inert metal 6 is prepared by electron beam evaporation coating method. In this embodiment, the top layer of inert metal 6 selected is gold with a thickness of 35 nm.

[0044] Subsequently, the device is placed in an inert gas environment for low-temperature annealing to promote solid-phase diffusion reaction between the bottom active metal 5 and the dielectric layer I4. The inert gas is any one of argon, xenon, helium, and neon, and the low-temperature annealing is annealing at a temperature range of 50°C to 80°C for 10 minutes to 6 hours. As a specific example, in this embodiment, the prepared device is placed in argon and annealed at 60°C for 1 hour.

[0045] Finally, the device obtained in the above steps is placed in an inert gas environment for 7-15 days to allow the bottom active metal 5 to undergo a solid phase diffusion reaction with the dielectric layer I4, and the bottom active metal 5 is oxidized to form a dielectric layer II8. The inert gas is any one of argon, xenon, helium, and neon; the method for forming the dielectric layer II8 is as follows: when the bottom active metal 5 is in direct contact with the dielectric layer I4, a solid phase diffusion reaction occurs, and the metal atoms in the bottom active metal 5 and the oxygen atoms in the dielectric layer I4 are combined through solid phase diffusion to form an oxide, i.e., the dielectric layer II8; the thickness of the dielectric layer II8 ranges from 0.1 nm to 5 nm. As a specific example, in this embodiment, the prepared device is placed in argon gas and allowed to stand for 10 days to form an aluminum oxide dielectric layer with a thickness of 2 nm.

[0046] The above describes in detail the performance-controllable two-dimensional semiconductor transistor structure and its preparation method of the present invention, but the present invention is not limited to the above examples. Various improvements and deformations can of course be made without departing from the scope of the present invention.

Claims

1. A method for preparing a two-dimensional semiconductor transistor structure with controllable performance, the two-dimensional semiconductor transistor structure comprising a substrate, a two-dimensional semiconductor material located on the substrate, a source-drain metal electrode, an oxide dielectric layer, and a laminated metal gate located on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer, comprising a dielectric layer I and a dielectric layer II; the laminated metal gate is a double-layer metal gate structure of a bottom active metal and a top inert metal, and the dielectric layer II is formed by a solid phase diffusion reaction between the dielectric layer I and the bottom active metal; It is characterized in that The specific steps are as follows: (1) Preparation of two-dimensional semiconductor materials on the substrate surface; (2) defining source and drain electrode regions on the two-dimensional semiconductor material through a masking layer, and performing source and drain metal deposition to prepare source and drain metal electrodes; (3) Using a masking layer to define the channel region and etching away the two-dimensional semiconductor material outside the channel; (4) In-situ deposition of a dielectric layer I on the surface of the two-dimensional semiconductor material; (5) A masking layer is used to define a gate electrode region on the surface of dielectric layer I. Under high vacuum conditions, the bottom active metal is first deposited, and the top inert metal is immediately deposited without destroying the high vacuum state to prepare a stacked gate structure. (6) After the device is fabricated, low-temperature annealing is performed in an inert gas environment to promote solid-phase diffusion reaction between the underlying active metal and dielectric layer I; (7) The device obtained in the above steps is placed in an inert gas environment for 7-15 days to allow the bottom active metal to undergo a solid phase diffusion reaction with the dielectric layer I, and the bottom active metal is oxidized to form the dielectric layer II.

2. The preparation method according to claim 1, characterized in that: The substrate is any one of a glass substrate, a sapphire substrate, a quartz substrate, a silicon substrate or a flexible substrate.

3. The preparation method according to claim 1, characterized in that: The dielectric layer I material is one of the following oxides with high dielectric constant: hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide or tantalum oxide; The bottom active metal gate material is one of the following active metals that are easily oxidized: aluminum, magnesium, zinc, iron or titanium; the top inert metal gate material is one of the following inert metals: gold, platinum, silver or copper.

4. The preparation method according to claim 1, characterized in that: The thickness of the bottom active metal is precisely controlled according to the required transistor performance requirements, and the thickness of the active metal ranges from 0.1 nm to 5 nm; The thickness of the top layer of inert metal is greater than 5 nm; The thickness of the dielectric layer II is in the range of 0.1 nm to 5 nm.

5. The preparation method according to claim 1, characterized in that: The masking layer in step (2), step (3) or step (5) is a photoresist or a mask.

6. The preparation method according to claim 1, characterized in that: The inert gas in step (6) or step (7) is any one of argon, xenon, helium or neon.

7. The preparation method according to claim 1, characterized in that The low temperature annealing in step (6) is performed at 50°C to 80°C, and the annealing time is 10 minutes to 6 hours.

8. The preparation method according to claim 1, characterized in that: The method for forming the dielectric layer II in step (7) is as follows: a solid phase diffusion reaction occurs when the underlying active metal is in direct contact with the dielectric layer I, and the metal atoms in the underlying active metal and the oxygen atoms in the dielectric layer I are combined through solid phase diffusion to form an oxide, namely the dielectric layer II.

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