Non-causal circuit partitioning method and gate-level circuit parallel simulation method

Abstract

The present invention proposes a method for non-causal circuit partitioning and a method for gate-level circuit parallel simulation, the method for non-causal circuit partitioning comprises: step S1: converting the gate-level circuit into a directed graph, and using a structure to save data; step S2: searching the set V of output nodes with external output from the structure; step S3: performing reverse processing on all directed edges in the directed graph, and exploring nodes in the set V in turn; step S4: initially dividing the directed graph into a plurality of primary units according to the exploration result; step S5: merging the primary units that meet the merging requirements in the initial partitioning to form secondary units, and outputting all the primary units that cannot be merged in the end, and saving the secondary units and all the primary units that cannot be merged in the form of a structure. Compared with the prior art, the present invention can divide circuits without dependencies in digital circuits, and independently run simulations, thereby improving simulation efficiency.

Description

Technical Field

[0001] The invention relates to EDA circuit parallel simulation, in particular to a non-causal circuit partitioning method and a gate-level circuit parallel simulation method. Background Art

[0002] With the rapid development of modern integrated circuit manufacturing technology, ultra-large-scale integrated circuits have tens of millions or even hundreds of millions of gate circuits. In EDA circuit design, in order to accelerate the speed of ultra-large-scale integrated circuit simulation, the use of parallel simulation is an effective way to improve simulation accuracy and shorten the simulation cycle. In order to efficiently parallelize the simulation, the circuit must be reasonably divided before simulation. Traditional circuit division is a causal division method, and there is a dependency relationship between the causal division circuit blocks. However, circuits without dependencies in the circuit cannot be divided well, which does not have a good effect on improving the simulation efficiency.

[0003] Therefore, how to design a non-causal circuit partitioning method for partitioning circuits without dependencies in the circuit and a gate-level circuit parallel simulation method is a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0004] In view of the technical problem in the prior art that circuits without dependencies cannot be partitioned, the present invention proposes a method for partitioning non-causal circuits and a method for parallel simulation of gate-level circuits.

[0005] The technical solution of the present invention is to propose a method for non-causal circuit partitioning, comprising: step S1: converting a gate-level circuit into a directed graph and using a structure to store data;

[0006] Step S2: Find the set V of output nodes that have output to the outside from the structure;

[0007] Step S3: reversely process all directed edges in the directed graph and explore the nodes in the set V in turn;

[0008] Step S4: initially dividing the directed graph into a plurality of primary units according to the exploration results;

[0009] Step S5: merge the primary units that meet the merging requirements in the initial division to form secondary units, and output all the primary units that cannot be merged in the end, and save the secondary units and all the primary units that cannot be merged in the form of a structure.

[0010] Further, the gate-level circuit is converted into a directed graph including:

[0011] A node in the directed graph represents a gate-level circuit, and a directed edge (a, b) between nodes represents that the output of gate-level circuit a is connected to the output of gate-level circuit b.

[0012] Further, let the structure be G, which includes at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost;

[0013] The G.name stores the name of each node of the directed graph;

[0014] The G.matrix stores the adjacency matrix of the directed graph;

[0015] The G.input.name stores the name of the external input to the directed graph;

[0016] The G.input.matrix is ​​a matrix that stores external input information of the directed graph;

[0017] The G.output.name stores the name of the output of the directed graph to the outside;

[0018] The G.output.matrix is ​​a matrix that stores the information of the directed graph to the external output;

[0019] The G.cost stores the cost of each node in the directed graph.

[0020] Further, searching the set V of output nodes having output to the outside from the structure includes:

[0021] According to the G.output.matrix, the output nodes in the directed graph that have output to the outside are obtained and recorded as a set V.

[0022] Further, the initially dividing the directed graph into a plurality of primary units according to the exploration results includes:

[0023] Perform depth-first exploration from the output nodes in the set V in turn, store all the nodes obtained from each search, and divide each exploration into a primary unit. The i-th primary unit is counted as M{i}.

[0024] Furthermore, the merging requirement is that the minimum number of identical nodes a required for merging any two units is less than or equal to the actual number of identical nodes b.

[0025] Furthermore, the step S5 further includes:

[0026] Step S51: inputting primary unit s1, primary unit s2 and similarity ratio per;

[0027] Step S52: Calculate the minimum number of identical nodes a required for merging the primary unit s1 and the primary unit s2, and the number of identical nodes b between the primary unit s1 and the primary unit s2;

[0028] Step S53: Compare the sizes of a and b, and determine whether they meet the merging requirements. If so, perform the merging operation.

[0029] Furthermore, after entering the merge operation, the following steps are also included:

[0030] Step S54: determine whether the similarity ratio per of the primary unit s1 and the primary unit s2 meets the preset requirement, if yes, merge the primary unit s1 and the primary unit s2, if no, proceed to step S55;

[0031] Step S55: sequentially determine the similarity between the primary unit s1 and all other units, and perform a merging operation when the similarity reaches a preset requirement;

[0032] Step S56: reselecting the primary units, comparing all the uncompared primary units in turn, and outputting the primary units that cannot be merged, until all the primary units cannot be merged.

[0033] Further, the reselecting the primary unit and sequentially comparing all the uncompared primary units comprises:

[0034] Suppose the total number of units is S, the previous detection unit is the i-th unit, reselect the i+1-th unit and compare it with the remaining uncompared units until the reselected unit number i+1 is equal to the total number of units S.

[0035] The present invention also proposes a gate-level circuit parallel simulation method, wherein the gate-level circuit parallel simulation method uses the above-mentioned non-causal circuit partitioning method to partition the circuit.

[0036] Compared with the prior art, the present invention has at least the following beneficial effects:

[0037] It can realize non-causal partitioning of gate-level circuits. The results of circuit partitioning have no dependencies and can be simulated independently and in parallel. At the same time, by controlling the size of the threshold per, the strictness of the merge can be controlled, thereby controlling the number of blocks of the circuit partitioning results, which is highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 It is the overall flow chart of the present invention;

[0040] Figure 2 The flowchart of the algorithm for determining whether two primary units meet the merging requirements after the initial division of the present invention;

[0041] Figure 3 The present invention is a flowchart of an algorithm for merging initial partitioning results. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0044] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0045] Due to the complex structure of integrated circuits, in order to speed up the simulation of ultra-large-scale integrated circuits, parallel simulation is an effective way to improve simulation accuracy and shorten the simulation cycle. In order to perform efficient parallel simulation, it is often necessary to reasonably divide the circuit before simulation. Traditional circuit division is causal division, and circuits without dependencies cannot be divided well. The idea of ​​the present invention is to propose a method for non-causal circuit division, which divides the circuit into multiple independent units and performs independent simulation to improve simulation efficiency.

[0046] See also Figure 1 ,The present invention proposes a method for non-causal circuit partitioning, including step S1: converting a gate-level circuit into a directed graph and using a structure to store data;

[0047] Step S2: Find the set V of output nodes that have output to the outside from the structure;

[0048] Step S3: reversely process all directed edges in the directed graph and explore the nodes in the set V in turn;

[0049] Step S4: initially dividing the directed graph into a plurality of primary units according to the exploration results;

[0050] Step S5: merge the primary units that meet the merging requirements in the initial division to form secondary units, and output all the primary units that cannot be merged in the end, and save the secondary units and all the primary units that cannot be merged in the form of a structure.

[0051] In the directed graph G(V,E), V={, ,…, } is a set of nodes, E={ , ,…, } is the set of edges. To indicate the existence of a directed edge, from vertex Point to the vertex , the resulting matrix D = D (G) = is the adjacency matrix of the directed graph G. In digital circuits, there are often multiple gate-level circuits, adjacent gate-level circuits are connected, and the output of gate-level circuit a is connected to the input of gate-level circuit b. Therefore, the digital circuit can be abstracted as a directed graph. Each node in the directed graph can represent a gate-level circuit. The directed edge (a, b) between the nodes represents that the output of gate circuit a is connected to the input of gate circuit b. The adjacency matrix of the directed graph is Able to represent the connection relationship between various parts in a digital circuit.

[0052] The prior art mostly adopts causal division. In the causal division, there is a dependency relationship between two blocks of the circuit. The output of the first block may be the input of the second block. However, the part of the circuit without dependency relationship cannot be divided well. The non-causal division method of the present invention divides two modules in the circuit without dependency relationship.

[0053] The step S1 of using a structure to save data includes: assuming that the structure is G, dividing it into at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost;

[0054] Among them, G.name stores the names of each node in the directed graph;

[0055] G.matrix stores the adjacency matrix of the directed graph;

[0056] G.input.name stores the name of the external input to the directed graph;

[0057] G.input.matrix is ​​a matrix that stores external input information for the directed graph;

[0058] G.output.name stores the name of the directed graph's external output;

[0059] G.output.matrix is ​​a matrix that stores the information of the directed graph's external output;

[0060] G.cost stores the cost of each node in the directed graph.

[0061] After saving the data in the form of a structure, the information of the digital circuit can be quickly obtained through the structure. For example, when you need to obtain the information of the external output of the directed graph, you can directly search through G.output.matrix. When you need to obtain the external input information of the directed graph, you can directly search through G.input.matrix, which is more convenient and quick.

[0062] After saving the data in the form of a structure, the circuit is preliminarily divided. In this application, all directed graphs in the directed graph are reversely processed, and the external output nodes are traced back from the directed graph until the initial input node. All nodes obtained from each exploration are stored, and all nodes explored each time are divided into a primary unit, and the i-th primary unit is counted as M{i}.

[0063] The number of primary units obtained after the initial division is consistent with the number of output nodes of the directed graph for external output. By backtracking the nodes of the directed graph for external output, all nodes that affect the node can be found. If the input nodes of the directed graph are explored, the nodes that affect the output of a certain node cannot be determined. For example, the output ends of gate-level circuits a1 and a2 are connected to the input ends of gate-level circuit a3, and the output end of gate-level circuit a3 is connected to the input end of gate-level circuit a4. Here, the gate-level circuits that affect gate-level circuit a4 are a1, a2, and a3. If the exploration is carried out in the forward direction, starting from gate-level circuit a1 to the end point a4, only gate-level circuits a1, a3, and a4 will be explored in the middle, and the influence of gate-level circuit a2 on gate-level circuit a3 will be ignored. After backtracking exploration, all gate-level circuits a1, a2, a3, and a4 can be explored.

[0064] After the gate-level circuit is reversely processed, we can start from the output node of the original directed graph for external output, explore each node once, and preliminarily divide it into a primary unit. After the final exploration is completed, the number of primary units obtained is consistent with the number of nodes of the directed graph for external output.

[0065] When exploring, you must first find all the output nodes for external output in the directed graph. The node is found through the structure. The structure G.output.matrix stores the information of the directed graph's external output, so that the output nodes of the directed graph for external output can be determined. The number of nodes is S, and the primary units obtained after the initial division are also S. After exploration, all nodes that have an impact on the output nodes are recorded, counted as Mi{i}, that is, primary units. For example, if the first node with external output is 1, then the set of nodes that have an impact on it is counted as M{1}, and the second node with external output is 2. Then the set of nodes that have an impact on it is counted as M{2}, and so on, to calculate the set of S nodes that have an impact on the external output nodes.

[0066] In digital circuits, there is often a situation where the output of a gate-level circuit is connected to the input of multiple gate-level circuits, or the input of a gate-level circuit is connected to the outputs of multiple gate-level circuits, such as the output of gate-level circuit a1 is connected to the input of gate-level circuit a2, the output of gate-level circuit a2 is connected to the input of gate-level circuit a3, the output of gate-level circuit a3 is connected to the input of gate-level circuit a4, the output of gate-level circuit a4 is respectively connected to the input of gate-level circuit a5 and gate-level circuit a6, and then output through gate-level circuit a5 and gate-level circuit a6. After reverse exploration, it will be divided into 2 primary units, namely gate-level circuit a1, gate-level circuit a2, gate-level circuit a3, gate-level circuit a4 and gate-level circuit a5; gate-level circuit a1, gate-level circuit a2, gate-level circuit a3, gate-level circuit a4 and gate-level circuit a6. It can be seen that only gate-level circuit a5 and gate-level circuit a6 are different in the two primary units, and the rest are exactly the same. If they are simulated separately, two almost repeated simulations will be performed. Therefore, in the present invention, it is necessary to merge the two primary units with higher similarity.

[0067] Here, we take any two primary units, counted as S1 and S2, the number of nodes that are the same in primary unit S1 and primary unit S2 is b, and the minimum number of nodes that are the same as the primary unit S1 and primary unit S2 required to merge is a. If a≤b, it can be determined that primary unit S1 and primary unit S2 can be merged, meeting the merging requirement.

[0068] See also Figure 2 , which is a flowchart of an algorithm program for determining whether two primary units meet the merging requirements after the initial division, and is used to determine whether two primary units can be merged. Specifically, it includes: Step S51: inputting primary unit s1, primary unit s2 and similarity ratio per;

[0069] Step S52: Calculate the minimum number of identical nodes a required for merging the primary unit s1 and the primary unit s2, and the number of identical nodes b between the primary unit s1 and the primary unit s2;

[0070] Step S53: Compare the sizes of a and b, and determine whether they meet the merging requirements. If so, perform the merging operation.

[0071] Here, the similarity ratio per is between 0 and 1, which represents the similarity of the two units. The higher the similarity, the more nodes the two primary units have in common. The output results are 0 and 1. When b≥a, the output result is 1, indicating that they can be merged. When a≥b, it is determined that they cannot be merged.

[0072] See also Figure 3 , which is a flowchart of the algorithm program for merging the initial partition results of the present invention. Figure 2 After determining that it can be merged, Figure 3 The algorithm performs the merging operation, which includes:

[0073] Step S54: determine whether the similarity ratio per of the primary unit s1 and the primary unit s2 meets the preset requirement, if yes, enter the merging operation, if no, enter step S55;

[0074] Step S55: sequentially determine the similarity between the primary unit s1 and all other units, and perform a merging operation when the similarity reaches a preset requirement;

[0075] Step S56: reselecting the primary units, comparing all the uncompared primary units in turn, and outputting the primary units that cannot be merged, until all the units cannot be merged.

[0076] As shown in the figure, at the beginning, the enable signal is set to 1, and then it is judged whether the enable signal is 1. When the enable signal is 0, it is determined that it does not need to be merged. When the enable signal is 1, it is determined that it needs to be merged. Figure 2 After the process in the above, it is determined that the two primary units can be merged, so here we enter Figure 3 After the process, the initial enable signal is set to 1, it is determined that it can be merged and enters the merging cycle.

[0077] Figure 3The dotted part in the middle is the merging action. The two primary units are i and j respectively. First, let i be 1 and j be i+1=2. The similarity of M{1} and M{2} is judged. If the similarity is 1, they are merged and output, and en=1 is set. Since en=1, when it re-enters the signal frame to determine whether the enable signal en is 1, it will be re-determined to be 1 and enter the loop. At this time, i=i+1 is set. Since the previous primary unit has already performed the merge operation, after i=i+1 is set here, re-judgment and merging will start from the next primary unit. If it is judged that the similarity between M{i} and M{j} is not 1, judge whether j is equal to S at this time. If j=S at this time, it can be determined that the current i-th primary unit and other primary units have been judged, output M{i}, and let i=i+1 to judge the next primary unit; if j is not equal to S at this time, let j=j+1, and judge the similarity between the next primary unit and the i-th primary unit, until the similarity is 1 and can be merged or j=S, and all units identical to i have been judged.

[0078] Assume that the total number of units is 5, the initial value of i is 1, and j is i+1=2. Judge the similarity between M{1} and M{2}. If the similarity is not 1, set j=j+1 and judge the similarity between M{1} and M{3} until two similarities are 1 and merge. Or, when the output result j=5, complete the judgment of M{1} and M{2}, M{3}, M{4}, and M{5}, and output M{1} to determine that it does not need to be merged. At this time, set i=i+1 and start judging from M{2} and compare it with M{3}, M{4}, and M{5}. By analogy, the similarity between any two units among the five primary units can be compared and merged.

[0079] pass Figure 3 After the program is completed, no two units in the final output can be merged, that is, there is no dependency between any two units in the gate-level circuit, and they can be simulated independently. The units in the output result here include secondary units and primary units. The secondary unit is the unit obtained by merging the primary units. In the final result, primary units and primary units, primary units and secondary units, and secondary units and secondary units cannot be merged.

[0080] Among them, in this embodiment, the preset requirement for similarity is 1, and the threshold of the similarity per can be adjusted according to the actual situation, such as setting it to 0.6, and changing the intermediate judgment of whether the similarity of M{i} and M{j} is equal to 1 to whether it is greater than or equal to 0.6. When it is greater than or equal to 0.6, it is merged, and the strictness of the merge can be changed according to actual needs.

[0081] Compared with the prior art, the present invention can realize non-causal partitioning of gate-level circuits. The results of circuit partitioning have no dependencies and can be simulated completely independently and in parallel. At the same time, by controlling the size of the threshold per, the strictness of the merge can be controlled, thereby controlling the number of blocks of the circuit partitioning results. Practice has proved that the practicability is very high.

[0082] The present invention also proposes a method for parallel simulation of gate-level circuits, which adopts the above-mentioned method for dividing non-causal circuits in parallel simulation of gate-level circuits, wherein multiple units that cannot be merged obtained after non-causal division are independently simulated in parallel.

[0083] The above are only partial or preferred embodiments of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for non-causal circuit partitioning, characterized in that: include: Step S1: Convert the gate-level circuit into a directed graph and use a structure to save the data; Step S2: Find the set V of output nodes that have output to the outside from the structure; Step S3: reversely process all directed edges in the directed graph and explore the nodes in the set V in turn; Step S4: initially dividing the directed graph into a plurality of primary units according to the exploration results; Step S5: merging the primary units that meet the merging requirements in the initial division to form secondary units, and outputting all the primary units that cannot be merged in the end, and saving the secondary units and all the primary units that cannot be merged in the form of a structure; The step S5 further comprises: Step S51: input primary unit s1, primary unit s2 and similarity ratio per; Step S52: Calculate the minimum number of identical nodes a required for merging the primary unit s1 and the primary unit s2, and the number of identical nodes b between the primary unit s1 and the primary unit s2; Step S53: Compare the sizes of a and b, and determine whether they meet the merging requirements. If so, perform the merging operation.

2. The method for non-causal circuit partitioning according to claim 1, characterized in that: The gate-level circuit is converted into a directed graph comprising: A node in the directed graph represents a gate-level circuit, and a directed edge (a, b) between nodes represents that the output of gate-level circuit a is connected to the output of gate-level circuit b.

3. The method for non-causal circuit partitioning according to claim 1, characterized in that The structure is G, which includes at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost; The G.name stores the name of each node of the directed graph; The G.matrix stores the adjacency matrix of the directed graph; The G.input.name stores the name of the external input to the directed graph; The G.input.matrix is ​​a matrix that stores external input information of the directed graph; The G.output.name stores the name of the output of the directed graph to the outside; The G.output.matrix is ​​a matrix that stores the information of the directed graph to the external output; The G.cost stores the cost of each node in the directed graph.

4. The method for non-causal circuit partitioning according to claim 3, characterized in that: The step of searching the set V of output nodes having output to the outside from the structure includes: According to the G.output.matrix, the output nodes in the directed graph that have output to the outside are obtained and recorded as a set V.

5. The method for non-causal circuit partitioning according to claim 1, characterized in that: The initially dividing the directed graph into a plurality of primary units according to the exploration results comprises: Perform depth-first exploration from the output nodes in the set V in turn, store all the nodes obtained from each exploration, and divide each exploration into a primary unit. The i-th primary unit is counted as M{i}.

6. The method for non-causal circuit partitioning according to claim 1, characterized in that: The merging requirement is that the minimum number of identical nodes a required for merging any two units is less than or equal to the actual number of identical nodes b.

7. The method for non-causal circuit partitioning according to claim 1, characterized in that: After entering the merge operation, it also includes: Step S54: determine whether the similarity ratio per of the primary unit s1 and the primary unit s2 meets the preset requirement, if yes, merge the primary unit s1 and the primary unit s2, if no, proceed to step S55; Step S55: sequentially determine the similarity between the primary unit s1 and all other units, and merge them when the similarity reaches a preset requirement; Step S56: reselecting the primary units, comparing all the uncompared primary units in turn, and outputting the primary units that cannot be merged, until all the units cannot be merged.

8. The method for non-causal circuit partitioning according to claim 7, characterized in that: The reselecting of the primary unit and comparing all the uncompared primary units in turn include: Assume that the total number of units is S, the primary unit detected last time is the i-th primary unit, reselect the i+1-th primary unit and compare it with the remaining uncompared primary units until the reselected unit number i+1 is equal to the total number of units S.

9. A method for parallel simulation of gate-level circuits, characterized in that: The gate-level circuit parallel simulation method is divided by using the non-causal circuit partitioning method as described in any one of claims 1 to 8.

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