IC die to IC die interconnect using error correction code and data path interleaving

Abstract

A multi-chip module includes a first integrated circuit (IC) die and a second IC die. The first IC die includes an array of first bonding pads, a plurality of first code group circuits, and a first interleaved interconnection between the plurality of first code group circuits and the array of the first bonding pads, the first interleaved interconnection including a first interleaving pattern, the first interleaving pattern causing data from different code group circuits to couple to adjacent first bonding pads. The second IC die includes an array of second bonding pads electrically coupled to the array of the first bonding pads, a plurality of second code group circuits, and a second interleaved interconnection between the plurality of second code group circuits and the array of the second bonding pads, the second interleaved interconnection including a second interleaving pattern, the second interleaving pattern causing data from different code groups to couple to adjacent second bonding pads.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 730,048, filed on September 12, 2018, entitled “IC Die To IC Die Interconnect Using Error Correcting Code And Data Path Interleaving,” which is incorporated herein by reference as if its contents were reproduced herein in their entirety. Technical Field

[0003] The present application relates to integrated circuit (IC) technology, and more particularly to communication between IC dies of a multi-chip module. Background Art

[0004] Integrated circuit (IC) technology has made great progress in the past fifty years. ICs are now common and found in electronic devices, machines, vehicles, appliances, and many other devices. Large processing ICs now include billions of transistors, while memory ICs include hundreds of billions of transistors. The density of transistors on an IC can reach 100 million transistors per square millimeter. However, the processing power of a single IC may not be sufficient to meet the required processing needs. Therefore, ICs can be bonded together so that two (or more) ICs are tightly coupled and provide greater processing power.

[0005] Die to die (D2D) interconnection between ICs is achieved by interconnecting bonding pads ("pads") on interlayer ICs to create multi-chip modules. The bonding pads of one IC are electrically coupled to the bonding pads of another IC by welding. However, welding requires that the bonding pads be spaced apart with sufficient spacing so that the solder does not seep between the bonding pads and short-circuit the bonding pads to each other. A newer technology does not use solder but directly bonds the copper bonding pads of one IC to the copper bonding pads of another IC. Compared with the old technology using solder, this newer technology supports smaller spacing between adjacent bonding pads. In either embodiment, when adjacent bonding pads are short-circuited due to solder or bonding pad failure or open-circuited due to defects such as depressions caused by particles or polishing, the data transmitted between the ICs is destroyed.

[0006] One existing approach to overcome the problems caused by bond pad shorts / opens is to use two or more redundant bond pads for at least some of the data. However, as the bond pads used for redundancy are doubled, the silicon area of ​​the bond pad array increases in proportion to the redundancy, resulting in high silicon area costs, additional power consumption from high capacitive loads, and increased heating. Doubling of bond pads and connections is not preferred. Summary of the invention

[0007] According to a first embodiment of the present invention, a multi-chip module includes a first integrated circuit (IC) die and a second IC die. The first IC die has an array of first bonding pads, a plurality of first code group circuits, and a first interleaved interconnection between the plurality of first code group circuits and the array of the first bonding pads. The first interleaved interconnection includes a first interleaved pattern, the first interleaved pattern causing data from different code group circuits to be coupled to adjacent first bonding pads. The second IC die has an array of second bonding pads electrically coupled to the array of the first bonding pads, a plurality of second code group circuits, and a second interleaved interconnection between the plurality of second code group circuits and the array of the second bonding pads, the second interleaved interconnection including a second interleaved pattern, the second interleaved pattern causing data from different code groups to be coupled to adjacent second bonding pads.

[0008] The multi-chip module provides important benefits and advantages over existing structures / devices. By encoding data for transmission to different ICs and by interleaving the data after encoding, the first embodiment can correct one or more adjacent bond pad shorts, detect two or more adjacent bond pad shorts, and correct two or more bond pad opens (even if adjacent to each other). The level of correction and detection of bond pad shorts and bond pad opens depends on the error correcting code (ECC) used by the code group circuit and the interleaving employed. Therefore, the first embodiment (and subsequent embodiments) utilizes reduced decoding and bond pad redundancy to protect data transmitted between IC dies in the multi-chip module.

[0009] The present invention provides various aspects that can be used with one or more of the described embodiments. These aspects can be combined with each other individually, doubly or in their entirety. According to a first aspect of the first embodiment, each of the plurality of first code group circuits directly corresponds to a corresponding second code group circuit. According to a second aspect of the first embodiment, the first interleaving interconnection interleaves data of at least two different first code group circuits, and the second interleaving interconnection interleaves data of at least two different corresponding second code group circuits.

[0010] According to a third aspect of the first embodiment, the array of the first bonding pads is organized into rows and columns, and the array of the second bonding pads is organized into rows and columns. In this aspect, for each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits, and for each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits.

[0011] According to the fourth aspect of the first embodiment, each of the plurality of first code group circuits is used to correct a single first bonding pad short circuit / open circuit and detect two first bonding pad short circuits / open circuits. In addition, according to the adopted ECC and the interleaving pattern, a larger number of short circuits and open circuits can be detected and corrected.

[0012] According to a fifth aspect of the first embodiment, the first interleaving interconnect interleaves data of four different first code group circuits, and the second interleaving interconnect interleaves data of four different second code group circuits, the four different second code group circuits corresponding to the four different first code group circuits. In this fifth aspect, for each row of first bonding pads, the first interleaving interconnect can establish a four-way interleaving pattern corresponding to the four different first code group circuits, and for each column of first bonding pads, the first interleaving interconnect can establish a four-way interleaving pattern corresponding to the four different first code group circuits.

[0013] A second embodiment of the present invention is directed to a method of maintaining communication between a first IC die and a second IC die of a multi-chip module. The method includes: the first IC die generating data for transmission to the second IC die, the first IC die encoding the data to generate first encoded data in a plurality of code groups, and the first IC die distributing the first encoded data to an array of first bonding pads via a first interleaving interconnect having a first interleaving pattern, the first interleaving pattern causing the encoded data to be coupled to the array of the first bonding pads such that bits of each code group are coupled to non-adjacent first bonding pads. In addition, the method includes: the second IC die receiving the encoded data via an array of second bonding pads electrically coupled to the array of the first bonding pads and via a second interleaving interconnect having a second interleaving pattern corresponding to the first interleaving pattern, and the second IC die decoding the encoded data to generate decoded data.

[0014] The second embodiment also includes multiple aspects that can be applied alone or in combination. According to a first aspect of the second embodiment, encoding the data to produce the encoded data includes using a plurality of first code group circuits of the first IC die, and decoding the encoded data to produce the decoded data includes using a plurality of second code group circuits of the second IC die, the plurality of second code group circuits directly corresponding to the plurality of first code group circuits. In this first aspect, the first interconnect can interleave data of at least two different first code group circuits, and the second interconnect can interleave data of at least two different corresponding second code group circuits.

[0015] According to a second aspect of the second embodiment, the array of the first bonding pads is organized into rows and columns, and the array of the second bonding pads is organized into rows and columns. In this second aspect, for each row of first bonding pads, adjacent first bonding pads may correspond to different first code group circuits of a plurality of first code group circuits, and for each column of first bonding pads, adjacent first bonding pads may correspond to different first code group circuits of a plurality of first code group circuits.

[0016] According to a third aspect of the second embodiment, the plurality of first code group circuits are each used to correct a single first bonding pad short / open and detect two first bonding pad shorts / opens.

[0017] According to a fourth aspect of the second embodiment, the first interleaving interconnection interleaves data of four different first code group circuits among the plurality of first code group circuits, and the second interleaving interconnection interleaves data of four different second code group circuits among the plurality of second code group circuits, the four different second code group circuits respectively corresponding to the four different first code group circuits. According to the fourth aspect, for each row of first bonding pads, a four-way interleaving pattern corresponding to the four different first code group circuits is established, and for each column of first bonding pads, a four-way interleaving pattern corresponding to the four different first code group circuits is established. In the fourth aspect, the plurality of first code group circuits can be used to correct at least two first bonding pad shorts / opens and detect at least three first bonding pad shorts / opens.

[0018] A third embodiment is directed to a method of maintaining communication between a first IC die and an external device. The method includes: the first IC die generates data for transmission to the external device, the first IC die encodes the data to generate first encoded data in a plurality of code groups, and the first IC die couples the first encoded data to an array of first bonding pads via a first interleaving interconnect having a first interleaving pattern, the first interleaving pattern causing the first encoded data to couple to the array of the first bonding pads so that bits of each code group are coupled to non-adjacent first bonding pads and causing the encoded data to be received by a second IC die. The method of the third embodiment also includes: the first IC die receives second encoded data from the external device die via the array of the first bonding pads and via the first interleaving interconnect, and the first IC die decodes the second encoded data to generate second decoded data.

[0019] The third embodiment includes various aspects that can be applied alone or in combination. According to a first aspect of the third embodiment, encoding the data to generate the first encoded data includes using a plurality of first code group circuits of the first IC die, and decoding the second encoded data to generate the second decoded data uses the plurality of first code group circuits. In this aspect, the first interconnect interleaves data of at least two different first code group circuits.

[0020] According to the second aspect of the third embodiment, the array of the first bonding pads is organized into rows and columns. In addition, for each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits in the plurality of first code group circuits, and for each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits in the plurality of first code group circuits.

[0021] By interleaving adjacent pads from different code groups, we will correct adjacent pad failures without increasing the area of ​​the bond pad array. These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] For a more thorough understanding of the present invention, reference is now made to the following brief description taken in conjunction with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0023] Figure 1 is a cross-sectional side view illustrating a portion of a multi-chip module having a first IC die and a second IC die constructed in accordance with the described embodiments.

[0024] Figure 2The invention is a method for illustrating a method of providing a bonding pad short circuit and a bonding pad open circuit according to the embodiment. Figure 1 A cross-sectional side view of a multi-chip module.

[0025] Figure 3 is based on Figure 1 The first aspect of the embodiment of Figure 1 Schematic top view of a portion of a first IC die.

[0026] Figure 4 is based on Figure 1 The second aspect of the embodiment of Figure 1 Schematic top view of a portion of a first IC die.

[0027] Figure 5 is a block diagram illustrating a code group circuit constructed in accordance with an embodiment of the present invention.

[0028] Fig. 6A is a flow chart illustrating the operation of a multi-chip module according to an embodiment of the present invention.

[0029] Figure 6B is a flow chart illustrating the operation of a first IC die of a multi-chip module according to an embodiment of the present invention.

[0030] Figure 7 is a flow chart illustrating the operation of a first IC die of a multi-chip module according to an embodiment of the present invention.

[0031] Figure 8 is a flow chart illustrating the operation of the second IC die of a multi-chip module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] First, it should be understood that although illustrative implementations of one or more embodiments are provided below, the disclosed systems and / or methods may be implemented using any number of techniques, whether currently known or in existence. The present invention should in no way be limited to the illustrative implementations, drawings, and techniques described below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0033] Figure 11 is a cross-sectional side view of a portion of a multi-chip module having a first integrated circuit (IC) die 102 and a second IC die 112 constructed according to the described embodiments. The first IC die 102 includes a plurality of processing systems 111A-111N, and the plurality of processing systems 111A-111N are coupled to each other via a communication interface 110. The communication I / F 110 may be a NoC (or a portion of a NoC) and may maintain all or part of the inter-IC die communications for the IC die 102. Figure 1 The first IC die 102 may include additional IC die communication interfaces compared to those illustrated in the embodiment 100 .

[0034] The second IC die 112 includes a plurality of processing systems 124A-124N that are coupled to each other via a communication interface 122. The communication I / F 122 may be a NoC and may maintain all or part of the inter-IC die communications for the second IC die 112. Figure 1 The second IC die 112 may include additional IC die communication interfaces compared to the IC die communication interfaces shown in the embodiment 100. The processing circuits 124A-124N may perform similar or complementary functions to the plurality of processing circuits 111A-111N of the first IC die 102.

[0035] Each of the first IC die 102 and the second IC die 112 can be a system on a chip (SoC), which includes multiple processing systems, such as 111A-111N and 124A-124N, that perform respective functions and have respective structures, such as general-purpose processors, communication processors (cellular, WiFi, Bluetooth, etc.), network interface processors, image processors, audio processors, graphics processors, arithmetic unit processors, confidentiality processors, security processors, and human interaction processors, memory controllers, and computer bus interface processors in other processing structures. SoCs are generally smaller, cheaper, and consume less power than devices including separate processing systems. It is understood that the first IC die 102 and the second IC die 112 may also have additional structures. The first IC die 102 and the second IC die 112 may be formed from a semiconductor substrate in a manufacturing process.

[0036] The first IC die 102 and the second IC die 112 include structures that allow them to communicate with each other effectively and without / with few communication errors. To meet these communication requirements, the first IC die 102 also includes an array of first bonding pads 104, a plurality of first code group circuits 106A-106N, and a first interleaved interconnect 108 between the plurality of first code group circuits 106A-106N and the array of first bonding pads 104. The first interleaved interconnect 108 includes a first interleaved pattern that couples data from different code group circuits 106A-106N to adjacent first bonding pads of the array of first bonding pads 104. The plurality of first code group circuits 106A-106N are mutually coupled to the plurality of processing circuits 111A-111N via at least one communication I / F 110.

[0037] The second IC die 112 also includes an array of second bonding pads 114, which are electrically coupled to the array of first bonding pads 104. The second IC die 112 also includes a plurality of second code group circuits 116A-116N, and a second interleaved interconnect 118 between the plurality of second code group circuits 116A-116N and the array of second bonding pads 114. The second interleaved interconnect 118 includes a second interleaving pattern, which causes data from different code groups to be coupled to adjacent second bonding pads 114. The plurality of second code group circuits 116A-116N are mutually coupled to the plurality of processing circuits 124A-124N via at least one communication I / F 122.

[0038] The array of first bonding pads 104 can be coupled to the array of second bonding pads 114 via copper bonding pad bonding 120, which supports a reduced spacing of the first bonding pads 104 and the second bonding pads 114. Conventional copper bonding pad to copper bonding pad bonding techniques can be employed to bond the first bonding pads 104 to the second bonding pads 114. In an alternative configuration, solder balls can be used to bond the first bonding pads 104 to the second bonding pads 114. Note that for illustrative purposes, a gap is shown between the first IC die 102 and the second IC die 112 to demonstrate bonding therebetween. In some embodiments, the silicon surfaces of the first IC die 102 and the second IC die 112 directly abut each other, such that the array of first bonding pads 104 directly abuts the array of second bonding pads 114.

[0039] Although in Figure 1102 and 112, but the principles described herein can be applied to sandwich structures having three or more IC dies. For example, an IC die can be sandwiched between two IC dies, and the adjacent IC dies are mutually coupled through electrically coupled corresponding bonding pads. Therefore, the IC die sandwiched between the two IC dies will have bonding pads on both of its planar surfaces to maintain communication therebetween. In addition, although not shown in Figure 1 1 , but the first IC die 102 and / or the second IC die may have additional bonding pads (not shown) that maintain coupling of the multi-chip module to external devices.

[0040] exist Figure 1 In the multi-chip module 100, each of the plurality of first code group circuits 106A-106N directly corresponds to a corresponding second code group circuit 116A-116N, i.e., the first code group circuit 106A corresponds to the second code group circuit 116A, the first code group circuit 106B corresponds to the second code group circuit 116B, and the first code group circuit 106C corresponds to the second code group circuit 116C, etc. As will be referred to herein FIG. 6A to FIG. 8 As further described, in IC die-to-die communications maintained according to the present invention, data between a first IC die 102 and a second IC die 112 is encoded by, for example, a first code group circuit 106A of the first IC die 102 and coupled to the corresponding first bonding pad 104 via a first interleaved interconnect 108. The data is then coupled to a second bonding pad 114, and the data is coupled from the second bonding pad 114 to a second code group circuit 116B of the second IC die 112 via a second interleaved interconnect 118. The second code group circuit 116 of the second IC die 112 decodes the encoded data to generate data for transmission to the second IC die 112. Using the encoding / interleaving / decoding of the present invention, at least some bond pad shorts / opens can be overcome. The ability of the first IC die 102 and the second IC die 112 to detect and correct errors caused by bond pad shorts / opens is based on the coding redundancy and interleaving pattern employed.

[0041] In one specific example, the first interleaving interconnect 108 interleaves data of at least two different first code group circuits, and the second interleaving interconnect 118 interleaves data of at least two different corresponding second code group circuits. In this example, each of the plurality of first code group circuits 106A-106B and the plurality of second code group circuits 116A-116B can be used to correct a single adjacent bond pad short circuit, detect two or more adjacent bond pad short circuits, and correct two or more bond pad opens using a type of error correcting code (ECC). In another specific example, the first interleaving interconnect 108 interleaves data of four different first code group circuits, such as 104A-104D, and the second interleaving interconnect 118 interleaves data of four different second code group circuits, the four different second code group circuits corresponding to the four different first code group circuits. Depending on the encoding used, in this example, the first code group circuits 106A-106D and the plurality of second code group circuits 116A-116D are capable of using one type of ECC to correct at least two first bond pad 104 shorts / opens and detect at least three first bond pad 104 shorts / opens. Of course, a greater number of bond pad opens / shorts may be corrected and detected using a higher error correction capability of a different ECC using more redundant bits. The tradeoff between smaller and larger ECCs is based on the number of bond pads and the encoding / decoding load.

[0042] If it will Figure 3 and Figure 4 As further described in , the array of first bonding pads 104 is organized into rows and columns, and the array of second bonding pads 114 is organized into rows and columns. In one aspect of the structure, for each row of first bonding pads 104, adjacent first bonding pads 104 correspond to different first code group circuits 106A-106N, and for each column of first bonding pads 104, adjacent first bonding pads 104 correspond to different first code group circuits 106A-106N. When the first interleaving interconnect 108 interleaves data of four different first code group circuits 106A-106D, the second interleaving interconnect 118 interleaves data of four different second code group circuits 116A-116D, and the four different second code group circuits 116A-116D correspond to the four different first code group circuits 106A-106D. In this case, for each row of first bonding pads 104, the first interleaving interconnect 108 establishes a four-way interleaving pattern corresponding to four different first code group circuits 106A-106D, and for each column of first bonding pads 104, the first interleaving interconnect 108 establishes a four-way interleaving pattern corresponding to four different second code group circuits 116A-116D.

[0043] Figure 2The invention is a method for illustrating a method of providing a bonding pad short circuit and a bonding pad open circuit according to the embodiment. Figure 1 A cross-sectional side view of a multi-chip module. Figure 1 Compared with the example 100, Figure 2 The example 200 includes a bonding pad short 202 that shorts the adjacent first bonding pad 104 and the adjacent second bonding pad 114. In addition, a bonding pad open is shown, where the bonding pads 104 and 114 cannot be electrically coupled. Figure 1 The described encoding / interleaving / decoding structure overcomes adjacent bond pad shorts and / or single bond pad opens to maintain a data link between the first IC die 102 and the second IC die 112 . FIG. 6A to FIG. 8 Operations supporting this correction process will be described.Depending on the interleaving level and ECC used by the first code group circuits 106A-106D and the plurality of second code group circuits 116A-116D, embodiments of the present invention have the ability to correct two or more adjacent bond pad failures and detect three or more bond pad failures.

[0044] Figure 3 is based on Figure 1 The first aspect of the embodiment of Figure 1 A schematic top view of a portion 300 of a first IC die. Figure 3 In the portion 300, a portion 302 of the array of first bonding pads 104 is organized into rows and columns, wherein the bonding pads 104 are denoted as 104IJ, where I represents a row and J represents a column. Figure 3 In the portion 300 of FIG. 1 , the illustrated portion of the first interleaving interconnect 108 interleaves data from at least two different first code group circuits, such as 106A and 106B. Figure 3 In the portion 300, for each row of first bonding pads 104, adjacent first bonding pads 104 correspond to different first code group circuits 106A or 106B, and for each column of first bonding pads 104, adjacent first bonding pads 104 correspond to different first code group circuits 106A or 106B.

[0045] exist Figure 3In the portion 300, each of the plurality of first code group circuits 106A-106B is used to correct a single adjacent bonding pad short 306 or 308, correct a plurality of bonding pad opens, and detect a short between two adjacent first bonding pads 104 using one ECC. The bonding pad short 306 shorts the data of two different first code group circuits 106A and 106B, and the bonding pad short 308 shorts the data of two different first code group circuits 106A and 106B. Based on the encoding used by the first code group circuits 106A and 106B and 116A and 116B, the data transmitted between the first IC die 102 and the second IC die 112 is correct even if the data associated with the two bonding pads 10415 and 10416 (or 10425 and 10435) are shorted. Using different ECCs, Figure 3 The portion 300 may correct more than one adjacent bond pad short, detect more than two adjacent bond pad shorts, and correct at least two bond pad opens.

[0046] Although in Figure 3 Components of the second IC die 112 are not shown, but the second IC die 112 includes components that are complementary to the components of the first IC die 102. The array of second bonding pads 114 (not shown) is also organized into rows and columns and is complementary to the array 302 of first bonding pads 104. In addition, Figure 4 The examples shown in FIG. 1 may extend across the entire extension of the array of first bonding pads 104 and the array of second bonding pads 114 and to other code group circuits.

[0047] Figure 4 is based on Figure 1 The second aspect of the embodiment of Figure 1 1 is a schematic top view of a portion 400 of a first IC die. A portion 402 of the array of first bonding pads 104 is organized into rows and columns, where the bonding pads are denoted 104IJ, where I represents a row and J represents a column. Although components of the second IC die 112 are not shown in FIG. Figure 4 , but there is a similar structure of the second IC die 112 that complements the components of the first IC die 102 shown.

[0048] exist Figure 4In the portion 400 of FIG. 4 , the first interleaving interconnect 108 interleaves data of four different first code group circuits 106A-106D, and the second interleaving interconnect 118 interleaves data of four different second code group circuits 116A-116D, the four different second code group circuits 116A-116D corresponding to the four different first code group circuits 106A-106D. In this case, for each row of first bonding pads 104, the first interleaving interconnect 108 establishes a four-way interleaving pattern corresponding to the four different first code group circuits 106A-106D, and for each column of first bonding pads 104, the first interleaving interconnect 108 establishes a four-way interleaving pattern corresponding to the four different first code group circuits 106A-106D. Figure 4 The portion 400 can correct at least two adjacent first bonding pads 104 using the first ECC, for example, a short circuit 404 between the first bonding pads 10414 and 10415 and a short circuit 406 between the first bonding pads 10415 and 10416. Similarly, Figure 4 The portion 400 is capable of correcting at least two adjacent first bonding pads 104 shorts in a column using a first ECC, for example, a short 408 between first bonding pads 10426 and 10436 and a short 410 between first bonding pads 10436 and 10446. The portion 400 is also capable of detecting more than two adjacent first bonding pads 104 shorts and indicating this to the control circuitry of the first IC die 102 using the first ECC. The use of a different, more robust ECC enables correction of more than two adjacent bonding pad shorts / opens and detection of more than three adjacent bonding pad shorts. Detection and correction of bond pad opens is maintained in a similar manner.

[0049] Figure 5 1 is a block diagram illustrating a code group circuit constructed in accordance with an embodiment of the present invention. Code group circuit 500 may be one of first code group circuits 106A-106N formed in first IC die 102, or may be formed in Figure 1 The first code group circuit 500 is formed in the first IC die 102 and includes an IC data interface 502 that receives data (M bits) for transmission from the first IC die 102 to the second IC die 112. An output data buffer 504 buffers the data, a data encoder 506 encodes the data according to a programmed ECC technique, and an encoded data buffer 508 buffers the encoded data. An interconnect I / F 510 is coupled to an interleaved interconnect that couples the encoded data to corresponding bonding pads. Note that the interconnect I / F 510 maintains a single bidirectional data path. In different embodiments, the paths for transmitting and receiving data are separate.

[0050] For data received from different IC dies, interconnect I / F 510 receives encoded data from different IC dies through bonding pads and interleaved interconnects coupled thereto. Encoded data buffer 512 buffers the encoded data, encoded data decoder 514 decodes the encoded data to produce decoded data, and decoded data buffer 516 buffers the decoded data. IC decoded data I / F 518 provides decoded data to the inside of the IC die for further use. Note that the data and decoded data have a width of M bits, while the encoded data has a width of N bits, where N is greater than M by a decoding factor. Various decoding techniques can be used to perform the encoding / decoding functions, such as Hamming codes and other simple block codes. There is a tradeoff between the complexity of the decoding technique used and the ability of the decoding technique to detect / correct errors caused by short / open bonding pads.

[0051] Fig. 6A is a flow chart illustrating the operation of a multi-chip module according to an embodiment of the present invention. Fig. 6A Operation 600 begins with a first IC die generating data for transmission to a second IC die (step 602). Operation 600 continues with the first IC die encoding the data to generate encoded data in a plurality of code groups (step 604). Next, operation 600 continues with the first IC die distributing the encoded data to an array of first bonding pads via a first interleaving interconnect having a first interleaving pattern that couples the encoded data to the array of first bonding pads such that bits of each code group are coupled to non-adjacent first bonding pads (step 606).

[0052] Next, operation 600 includes receiving the encoded data by the second IC die through an array of second bonding pads electrically coupled to the array of first bonding pads and through a second interleaving interconnect having a second interleaving pattern corresponding to the first interleaving pattern (step 608). Operation 600 ends with the second IC die decoding the encoded data to produce decoded data (step 610).

[0053] Fig. 6A The operation 600 of can adopt a specific structure. According to a first aspect of the embodiment of FIG. 6, encoding data to generate encoded data includes using a plurality of first code group circuits of a first IC die, and decoding the encoded data to generate decoded data uses a plurality of second code group circuits of a second IC die that directly corresponds to the plurality of first code group circuits. In this aspect, the first interconnect interleaves data of at least two different first code group circuits, and the second interconnect interleaves data of at least two different corresponding second code group circuits.

[0054] According to a first aspect of the structure, the array of first bonding pads may be organized into rows and columns, and the array of second bonding pads may be organized into rows and columns. In the first aspect of the structure, for each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of a plurality of first code group circuits, and for each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of a plurality of first code group circuits. In this aspect, the plurality of first code group circuits are each used to correct a single first bonding pad short / open circuit and detect two first bonding pad short / open circuits.

[0055] According to a second aspect of the structure, the first interleaving interconnection interleaves data of four different first code group circuits among the plurality of first code group circuits, and the second interleaving interconnection interleaves data of four different second code group circuits among the plurality of second code group circuits, the four different second code group circuits respectively corresponding to the four different first code group circuits. In this second aspect of the structure, for each row of first bonding pads, a four-way interleaving pattern corresponding to the four different first code group circuits is established, and for each column of first bonding pads, a four-way interleaving pattern corresponding to the four different first code group circuits is established. In this case, the plurality of first code group circuits are used to correct at least two first bonding pad shorts, detect at least three first bonding pad shorts, and correct at least three bonding pad opens.

[0056] Figure 6B is a flow chart illustrating the operation of a first IC die in communication with an external device according to an embodiment of the present invention. The external device may be a second IC die of a multi-chip module, a different IC die, or another device in communication with the first IC die. Figure 6B Operation 650 of the embodiment begins with a first IC die generating data for transmission to an external device (step 652). Operation 650 continues with the first IC die encoding the data to generate encoded data in a plurality of code groups (step 654). Next, operation 650 continues with the first IC die distributing the encoded data to an array of first bonding pads via a first interleaving interconnect having a first interleaving pattern, the first interleaving pattern coupling the encoded data to the array of first bonding pads such that bits of each code group are coupled to non-adjacent first bonding pads (step 656).

[0057] Next, operation 650 includes the first IC die receiving second encoded data from an external device through the array of first bonding pads and through the first interleaved interconnect having the first interleaved pattern (step 658). Operation 650 ends with the first IC die decoding the second encoded data to generate second decoded data (step 660). Figure 6B Operation 650 includes reference to Fig. 6A The aspects described are the same / similar in every respect.

[0058] Figure 7 is a flow chart illustrating the operation of a first IC die of a multi-chip module according to an embodiment of the present invention. Figure 7 Operation 700 and Fig. 6A and Figure 6B Operation and Figures 1 to 5 The operation 700 begins with a first code group circuit of a first IC die receiving data to be transmitted to a second IC die (step 702). The first code group circuit then buffers the data (step 704). The first code group circuit then encodes the data to produce encoded data (step 706). Next, the first code group circuit buffers the encoded data (step 708). Finally, the first code group circuit transmits the encoded data to the second IC die via a first interleaved interconnect and an array of first bonding pads (step 710).

[0059] Figure 8 is a flow chart illustrating the operation of the second IC die of a multi-chip module according to an embodiment of the present invention. Figure 8 Operation 800 with Figure 7 Operation 800 is complementary to operation 700 of the present invention, but from the perspective of a second IC die that is receiving data from a first IC die. Operation 800 begins with a second code group circuit of the second IC die receiving encoded data from a first IC die via an array of second bond pads and a second interleaved interconnect (step 802). Operation 800 continues with a second code group circuit of the second IC die buffering the encoded data (step 804), and the second code group circuit decoding the encoded data to produce decoded data (806). The second code group circuit then buffers the decoded data (step 808), and forwards the decoded data for use by the second IC die (step 810).

[0060] By interleaving adjacent pads from different code groups, we will correct adjacent pad faults without increasing the area of ​​the bonding pad array. Although the present invention provides a plurality of specific embodiments, it should be understood that the disclosed systems and methods may also be embodied in a variety of other specific forms without departing from the spirit or scope of the present invention. The examples of the present invention should be considered illustrative rather than restrictive, and the present disclosure is not limited to the details given herein. For example, various elements or components may be combined or merged in another system, or certain features may be omitted or not implemented.

[0061] In addition, without departing from the scope of the present invention, the techniques, systems, subsystems and methods described and illustrated as discrete or separate in various embodiments may be combined or integrated with other systems, modules, techniques or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may also be indirectly coupled or communicated via an interface, device or intermediate component, either electrically, mechanically or otherwise. Other changes, substitutions, and alternative examples will be apparent to those skilled in the art, and these changes, substitutions, and alternative examples do not depart from the spirit and scope disclosed herein.

Claims

1. A multi-chip module, characterized in that: include: The first IC die has: an array of first bond pads; a plurality of first code group circuits; as well as a first interleaved interconnection between the plurality of first code group circuits and the array of first bonding pads, the first interleaved interconnection comprising a first interleaving pattern, the first interleaving pattern causing data from different code group circuits to couple to adjacent first bonding pads; as well as The second IC die has: an array of second bond pads electrically coupled to the array of first bond pads; a plurality of second code group circuits; as well as A second interleaved interconnection between the plurality of second code group circuits and the array of second bonding pads includes a second interleaved pattern, the second interleaved pattern causing data from different code group circuits to couple to adjacent second bonding pads.

2. The multi-chip module according to claim 1, characterized in that: Each first code group circuit of the plurality of first code group circuits directly corresponds to a corresponding second code group circuit.

3. The multi-chip module according to claim 1, characterized in that: The first interleaving interconnect interleaves data of at least two different first code group circuits; and The second interleaving interconnect interleaves data of at least two different corresponding second code group circuits.

4. The multi-chip module according to claim 1, wherein: The array of first bond pads is organized into rows and columns; and The array of second bond pads is organized into rows and columns.

5. The multi-chip module according to claim 1, wherein: For each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits; and For each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits.

6. The multi-chip module according to claim 1, characterized in that: Each of the plurality of first code group circuits is used to correct a single first bonding pad short / open circuit and detect two first bonding pad short / open circuits.

7. The multi-chip module according to claim 1, characterized in that: The first interleaving interconnect interleaves data of four different first code group circuits; and The second interleaving interconnect interleaves data of four different second code group circuits corresponding to the four different first code group circuits.

8. The multi-chip module according to claim 1, characterized in that: For each row of first bond pads, the first interleaved interconnect establishes a four-way interleaved pattern corresponding to the four different first code group circuits; as well as For each column of first bond pads, the first interleaved interconnect establishes a four-way interleaved pattern corresponding to the four different first code group circuits.

9. The multi-chip module according to any one of claims 1 to 8, characterized in that: The plurality of first code group circuits are used to correct at least two first bonding pad short circuits / open circuits and detect at least three first bonding pad short circuits / open circuits.

10. A method for maintaining communication between a first IC die and a second IC die of a multi-chip module, characterized in that: The method comprises: The first IC die generates data for transmission to the second IC die; The first IC die encodes the data to generate first encoded data in a plurality of code groups; the first IC die distributing the first encoded data to an array of first bonding pads via a first interleaving interconnect having a first interleaving pattern, the first interleaving pattern causing the encoded data to couple to the array of first bonding pads such that bits of each code group are coupled to non-adjacent first bonding pads; the second IC die receiving the encoded data through an array of second bond pads electrically coupled to the array of first bond pads and through a second interleaved interconnect having a second interleaving pattern corresponding to the first interleaving pattern; and The second IC die decodes the encoded data to generate decoded data.

11. The method according to claim 10, characterized in that: encoding the data to produce encoded data includes using a plurality of first code group circuits of the first IC die; and Decoding the encoded data to generate the decoded data uses a plurality of second code group circuits of the second IC die, the plurality of second code group circuits directly corresponding to the plurality of first code group circuits.

12. The method according to claim 10, characterized in that: The first interleaving interconnect interleaves data of at least two different first code group circuits; and The second interleaving interconnect interleaves data of at least two different corresponding second code group circuits.

13. The method according to claim 10, characterized in that: The array of first bond pads is organized into rows and columns; and The array of second bond pads is organized into rows and columns.

14. The method according to claim 10, characterized in that: For each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of the plurality of first code group circuits; and For each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of the plurality of first code group circuits.

15. The method according to claim 11, characterized in that The plurality of first code group circuits are each used to correct a single first bonding pad short / open circuit and detect two first bonding pad short / open circuits.

16. The method according to claim 10, characterized in that: The first interleaving interconnect interleaves data of four different first code group circuits among the plurality of first code group circuits; and The second interleaving interconnect interleaves data of four different second code group circuits among the plurality of second code group circuits, the four different second code group circuits respectively corresponding to the four different first code group circuits.

17. The method according to claim 16, characterized in that: For each row of first bond pads, establishing a four-way interleaving pattern corresponding to the four different first code group circuits; and For each column of first bond pads, a four-way interleaving pattern corresponding to the four different first code group circuits is established.

18. The method according to any one of claims 11, 12, 14, 15, 16 or 17, characterized in that The plurality of first code group circuits are used to correct at least two first bonding pad short circuits / open circuits and detect at least three first bonding pad short circuits / open circuits.

19. A method for maintaining communication between an IC die and an external device, characterized in that: The method comprises: The first IC die generates data for transmission to the external device; The first IC die encodes the data to generate first encoded data in a plurality of code groups; the first IC die coupling the first encoded data to an array of first bonding pads via a first interleaved interconnect having a first interleaved pattern, the first interleaved pattern causing the first encoded data to be coupled to the array of first bonding pads such that bits of each code group are coupled to non-adjacent first bonding pads and causing the encoded data to be for receipt by a second IC die; The first IC die receives second encoded data from the external device through the first array of bond pads and through the first interleaved interconnect; and The first IC die decodes the second encoded data to generate second decoded data.

20. The method according to claim 19, characterized in that: encoding the data to produce the first encoded data includes using a plurality of first code group circuits of the first IC die; and Decoding the second encoded data to produce the second decoded data includes using the plurality of first code group circuits.

21. The method according to claim 19, characterized in that The first interleaving interconnect interleaves data of at least two different first code group circuits.

22. The method according to claim 19, characterized in that The array of first bond pads is organized into rows and columns.

23. The method according to any one of claims 19 to 22, characterized in that: For each row of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of the plurality of first code group circuits; as well as For each column of first bonding pads, adjacent first bonding pads correspond to different first code group circuits of the plurality of first code group circuits.

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