A power-saving and area-saving soft-start circuit for LDO

Abstract

The present invention discloses a power-saving and area-saving soft-start circuit for LDO, comprising a first current source, a second current source, a first MOS tube, a second MOS tube, a third MOS tube and a capacitor; one end of the first current source, the drain of the first MOS tube, and the gate of the second MOS tube are connected to a first node; one end of the second current source, the drain of the second MOS tube, the gate of the third MOS tube and one end of the capacitor are electrically connected to a second node; the other end of the capacitor, the source of the first MOS tube and the source of the second MOS tube are all grounded; the gate of the first MOS tube receives a start signal EA_ST; the source and drain of the third MOS tube are electrically connected to the source and drain of the fourth MOS tube respectively; the fourth MOS tube is located in the error amplifier of the LDO, and the gate of the fourth MOS tube is led out as the positive input end of the error amplifier to receive a reference voltage signal. The present invention does not need to use a complex control circuit, and can achieve the function of output soft start by using fewer components.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and in particular to a power-saving and area-saving soft-start circuit applied to an LDO (Low Dropout regulator). Background Art

[0002] LDO is a linear regulator that uses a transistor or field effect transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. A general LDO regulator will generate a large current when the external power is first added, and the instantaneous output to the load will cause the so-called "peak current" to be generated, which may cause damage due to reduced tolerance of the components and cause startup overshoot. At this time, the voltage at the LDO output changes with time as shown below: Figure 1 shown. Summary of the invention

[0003] Purpose of the invention: To overcome the problems in the prior art, the present invention aims to provide a power-saving and area-saving soft-start circuit for LDO. On the other hand, the present invention provides an LDO including the soft-start circuit.

[0004] Technical solution: On the one hand, the present invention discloses a power-saving and area-saving soft-start circuit for LDO. The soft-start circuit includes: a first current source, a second current source, a first MOS tube, a second MOS tube, a third MOS tube and a capacitor; one end of the first current source, the drain of the first MOS tube, and the gate of the second MOS tube are connected to the first node; one end of the second current source, the drain of the second MOS tube, the gate of the third MOS tube and one end of the capacitor are electrically connected to the second node; the other end of the capacitor, the source of the first MOS tube and the source of the second MOS tube are all grounded; the gate of the first MOS tube receives the start signal EA_ST; the source and drain of the third MOS tube are electrically connected to the source and drain of the fourth MOS tube respectively; the fourth MOS tube is located in the error amplifier of the LDO, and the gate of the fourth MOS tube is led out as the positive input end of the error amplifier to receive the reference voltage signal.

[0005] Furthermore, the first MOS tube and the second MOS tube are both NMOS tubes; and the third MOS tube and the fourth MOS tube are both PMOS tubes.

[0006] Further, the first current source and the second current source each include two PMOS tubes connected in series, and the gates of the two PMOS tubes connected in series receive the first bias voltage and the second bias voltage respectively; among the two PMOS tubes connected in series included in the first current source and the second current source, the source of the PMOS tube far away from the first MOS tube and the second MOS tube is electrically connected to the external power supply.

[0007] Furthermore, the start signal and the reference voltage signal both come from a bandgap reference voltage circuit.

[0008] On the other hand, the present invention discloses an LDO including the above-mentioned soft start circuit. The LDO also includes an error amplifier, a frequency compensation circuit, a power tube, a first feedback resistor and a second feedback resistor; the output end of the error amplifier is electrically connected to the gate of the power tube via the frequency compensation circuit; the source of the power tube is connected to an external power supply, and the drain is connected to ground via the first feedback resistor and the second feedback resistor connected in series; the negative input end of the error amplifier is electrically connected to the connection point of the first feedback resistor and the second feedback resistor.

[0009] Further, the error amplifier includes: the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the third current source; the source electrodes of the fourth MOS tube and the fifth MOS tube are electrically connected to the third current source; the drain electrode of the fourth MOS tube is electrically connected to the drain electrode and the gate electrode of the sixth MOS tube and the gate electrode of the seventh MOS tube; the drain electrode of the fifth MOS tube is electrically connected to the drain electrode of the seventh MOS tube; the sources of the sixth MOS tube and the seventh MOS tube are both grounded; the gate electrode of the fifth MOS tube is led out as the negative input terminal of the error amplifier.

[0010] Further, the fourth MOS tube and the fifth MOS tube are both PMOS tubes; the sixth MOS tube and the seventh MOS tube are both NMOS tubes; and the power tube is a P-type power tube.

[0011] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0012] (1) No complex control circuit is required. Only three MOS tubes M1 to M3, two current sources I1 and I2, and one capacitor MCST are needed to achieve the function of output soft start (i.e., suppressing startup overshoot). Therefore, fewer circuit components are used, which can save area for the entire chip and reduce power consumption.

[0013] (2) Suitable for various LDO circuits with good compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1This is a graph showing the relationship between the output voltage of the LDO and time when the existing LDO has a startup overshoot;

[0015] Figure 2 is a schematic structural diagram of an LDO including a soft start circuit in one embodiment of the present invention;

[0016] Figure 3 1 is a graph showing the relationship between the output voltage of an LDO and time in one embodiment of the present invention. DETAILED DESCRIPTION

[0017] This embodiment will introduce an LDO including a soft start circuit that saves power and area. The specific circuit diagram is as follows: Figure 2 shown.

[0018] like Figure 2 , the LDO includes a soft start circuit, an error amplifier, a frequency compensation circuit, a power tube MPO, a first feedback resistor RF1 and a second feedback resistor RF2. The soft start circuit is connected to the error amplifier. The output end of the error amplifier is electrically connected to the gate of the power tube MPO via the frequency compensation circuit. The source of the power tube MPO is connected to the external power supply VCC, and the drain is connected to the ground GND via the first feedback resistor RF1 and the second feedback resistor RF2 connected in series. The negative input end of the error amplifier is electrically connected to the connection point of the first feedback resistor RF1 and the second feedback resistor RF2. The power tube is a P-type power tube.

[0019] The following is a detailed introduction to the soft start circuit.

[0020] The soft start circuit includes: a first current source I1, a second current source I2, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a capacitor MCST. One end of the first current source I1, the drain of the first MOS tube M1, and the gate of the second MOS tube M2 are connected to the first node. One end of the second current source I2, the drain of the second MOS tube M2, the gate of the third MOS tube M3 and one end of the capacitor MCST are electrically connected to the second node. The other end of the capacitor MCST, the source of the first MOS tube M1 and the source of the second MOS tube M2 are all grounded GND. The gate of the first MOS tube M1 receives the start signal EA_ST. Among them, the first MOS tube and the second MOS tube are both PMOS tubes; the third MOS tube and the fourth MOS tube are both NMOS tubes.

[0021] The first current source I1 includes two PMOS transistors P11 and P12 connected in series, and the second current source I2 includes two PMOS transistors P21 and P22 connected in series. The gates of P11 and P21 receive the first bias voltage VB1, respectively, and the gates of P12 and P22 receive the second bias voltage VB2, respectively. The source of P11 away from the first MOS transistor M1 and the source of P21 away from the second MOS transistor M2 are electrically connected to the external power supply VCC.

[0022] The error amplifier includes: a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and a third current source I3. The sources of the fourth MOS tube M4 and the fifth MOS tube M5 are electrically connected to the third current source I3. The drain of the fourth MOS tube M4 is electrically connected to the drain and gate of the sixth MOS tube M6 and the gate of the seventh MOS tube M7. The drain of the fifth MOS tube M5 is electrically connected to the drain of the seventh MOS tube M7. The sources of the sixth MOS tube M6 and the seventh MOS tube M7 are both grounded. The gate of the fourth MOS tube M4 is led out as the positive input terminal of the error amplifier to receive the reference voltage signal Vref. The gate of the fifth MOS tube M5 is led out as the negative input terminal of the error amplifier to be electrically connected to the connection point of the first feedback resistor RF1 and the second feedback resistor RF2. Among them, the fourth MOS tube M4 and the fifth MOS tube M5 are both PMOS tubes. The sixth MOS tube M6 and the seventh MOS tube M7 are both NMOS tubes. The third current source I3 is similar to the first and second current sources, and also includes two PMOS transistors P31 and P32 connected in series. The gates of P31 and P32 are connected to the first bias voltage VB1 and the second bias voltage VB2, respectively.

[0023] When the soft start circuit is connected to the error amplifier, the source and drain of the third MOS tube M3 in the soft start circuit are electrically connected to the source and drain of the fourth MOS tube M4, respectively. The start signal EA_ST received by the soft start circuit and the reference voltage signal Vref received by the error amplifier are both from the bandgap reference voltage circuit. The bandgap reference voltage circuit is a prior art, which can be roughly simplified to a current source and a plurality of resistors connected in series with the current source. EA_ST and Vref are respectively drawn from different resistor connection points. Usually, the voltage corresponding to EA_ST is greater than the voltage corresponding to Vref, because in this embodiment, EA_ST is connected to the gate of the NMOS tube M1, and Vref is connected to the gate of the PMOS tube M4.

[0024] The frequency compensation circuit can adopt existing technology, which is generally available in LDO and will not be introduced in detail here.

[0025] Working principle: When the external power supply VCC is initially powered on quickly, the start signal EA_ST is initially 0, the potential of the EA_SD point at the gate of the second MOS tube M2 is 1, M2 is turned on, so that the gate potential of the third MOS tube M3 is 0. It can be known that when the external power supply VCC is powered on quickly, M3 is fully turned on, and the fourth MOS tube M4 is short-circuited, so that the gate input of the power tube MPO is high level, causing MPO to be completely closed. Therefore, when the external initial power supply VCC is powered on quickly, the output VOUT of the LDO is 0. After a short period of time, EA_ST is changed to 1, so that the potential of the EA_SD point at the gate of M2 becomes 0, and M2 is turned off. At this time, the small current generated by the second current source I2 will slowly charge the MOS capacitor MCST, so that the gate voltage of the third MOS tube M3 will slowly reach the VCC potential and M3 will be completely turned off. The gate potential of the power tube MPO will also slowly drop from VCC to the normal potential of actual operation, so that the power tube MPO is slowly turned on, and the output VOUT of the LDO is slowly increased to achieve the function of output voltage soft start, such as Figure 3 shown.

[0026] contrast Figure 1 and Figure 3 It can be seen that the above embodiment of the present invention can realize the function of output soft start (i.e., suppressing start-up overshoot). At the same time, because the above embodiment only needs to use three MOS tubes M1-M3, two current sources I1 and I2 and one capacitor MCST, it does not need to use a complex control circuit, so the circuit elements used are small, which can save area for the entire chip and reduce power consumption.

[0027] In addition to the above embodiments, the present invention may also have other implementation modes. Any technical solutions formed by equivalent replacement or equivalent transformation shall fall within the protection scope required by the present invention.

Claims

1. A power-saving and area-saving soft-start circuit for LDO, characterized in that: include: A first current source, a second current source, a first MOS tube, a second MOS tube, a third MOS tube and a capacitor; one end of the first current source, the drain of the first MOS tube, and the gate of the second MOS tube are connected to the first node; one end of the second current source, the drain of the second MOS tube, the gate of the third MOS tube and one end of the capacitor are electrically connected to the second node; the other end of the capacitor, the source of the first MOS tube and the source of the second MOS tube are all grounded; the gate of the first MOS tube receives a start signal EA_ST; the source and drain of the third MOS tube are electrically connected to the source and drain of the fourth MOS tube respectively; the fourth MOS tube is located in the error amplifier of the LDO, and the gate of the fourth MOS tube is led out as The first MOS tube and the second MOS tube are both NMOS tubes; the third MOS tube and the fourth MOS tube are both PMOS tubes; the first current source and the second current source each include two PMOS tubes connected in series, and the gates of the two PMOS tubes connected in series receive the first bias voltage and the second bias voltage respectively; of the two PMOS tubes connected in series included in the first current source and the second current source, the source of the PMOS tube far away from the first MOS tube and the second MOS tube is electrically connected to the external power supply; the start signal EA_ST and the reference voltage signal Vref are both from the bandgap reference voltage circuit.

2. An LDO comprising the power-saving and area-saving soft-start circuit according to claim 1, characterized in that: It also includes an error amplifier, a frequency compensation circuit, a power tube, a first feedback resistor and a second feedback resistor; the output end of the error amplifier is electrically connected to the gate of the power tube via the frequency compensation circuit; the source of the power tube is connected to an external power supply, and the drain is grounded via the first feedback resistor and the second feedback resistor connected in series; the negative input end of the error amplifier is electrically connected to the connection point of the first feedback resistor and the second feedback resistor.

3. The LDO according to claim 2, characterized in that: The error amplifier comprises: the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the third current source; the source electrodes of the fourth MOS tube and the fifth MOS tube are electrically connected to the third current source; the drain electrode of the fourth MOS tube is electrically connected to the drain electrode and the gate electrode of the sixth MOS tube and the gate electrode of the seventh MOS tube; the drain electrode of the fifth MOS tube is electrically connected to the drain electrode of the seventh MOS tube; the source electrodes of the sixth MOS tube and the seventh MOS tube are both grounded; the gate electrode of the fifth MOS tube is led out as the negative input terminal of the error amplifier.

4. The LDO according to claim 2, characterized in that: The fourth MOS tube and the fifth MOS tube are both PMOS tubes; the sixth MOS tube and the seventh MOS tube are both NMOS tubes; and the power tube is a P-type power tube.

Images