Stepped word line structure and preparation method thereof

Abstract

The present invention provides a ladder-type word line structure and a preparation method thereof, which comprises a conductive layer, wherein the top of the conductive layer is in a ladder-type configuration with a high middle and low sides. The ladder-type word line structure of the present invention can reduce the resistance of the word line structure and avoid the GIDL effect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor storage devices, and in particular to a ladder-type word line structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, which consists of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, and the drain or source is connected to the bit line or capacitor. The voltage information on the word line can control the opening or closing of the transistor, and then read the data information in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage. Usually, in order to reduce the size of the device, criss-cross word lines and bit lines are set in the active area of ​​the array.

[0003] For the word line structure, its surface is usually covered with a thicker insulating layer to reduce leakage current and improve the GIDL (Gate-induced Drain Leakage) effect. However, the insulating layer also occupies a larger space of the word line, reduces the thickness of the word line, increases the resistance of the word line, and thus reduces the control ability of the gate over the channel, resulting in a decrease in the transistor's driving current capability.

[0004] Therefore, how to reduce the resistance of the word line while avoiding the GIDL effect and improving the control capability of the gate over the channel has become a technical problem that urgently needs to be solved. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a ladder-type word line structure and a preparation method thereof, which can reduce the resistance of the word line structure and avoid the GIDL effect.

[0006] In order to solve the above problems, the present invention provides a stepped word line structure, which includes a conductive layer, wherein the top of the conductive layer is in a stepped configuration with a high middle and low sides.

[0007] Furthermore, the top of the conductive layer is symmetrically arranged with the center line of the conductive layer as an axis.

[0008] Furthermore, the ladder-type word line structure further includes a barrier layer disposed on the outer surface of the conductive layer, and the highest point of the top of the conductive layer is higher than the upper end surface of the barrier layer.

[0009] Furthermore, the lowest point of the top of the conductive layer is higher than the upper end surface of the barrier layer.

[0010] Furthermore, the ladder-type word line structure further includes a gate insulating layer, and the gate insulating layer is arranged on the outer surface of the barrier layer.

[0011] Furthermore, the upper end surface of the gate insulating layer is higher than the highest point of the top of the conductive layer.

[0012] The present invention also provides a method for preparing a stepped word line structure, which includes the following steps: providing a substrate, the substrate having a plurality of grooves arranged at intervals; filling the grooves with conductive material to form a conductive layer, the top of the conductive layer being lower than the upper edge of the groove; etching the conductive layer multiple times so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

[0013] Furthermore, the preparation method further includes the following steps: before forming the conductive layer, forming a gate insulating layer and a barrier layer on the sidewalls of the trench; and filling the gate barrier layer with a conductive material to form the conductive layer.

[0014] Furthermore, the method for making the top of the conductive layer present a stepped configuration with a high middle and low sides includes the following steps: etching the conductive layer multiple times along a direction perpendicular to the top of the conductive layer from the edge of the top of the conductive layer to the center of the top of the conductive layer, so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

[0015] Furthermore, the method for making the top of the conductive layer present a stepped configuration with a high middle and low sides includes the following steps: forming a mask layer in the portion of the groove not filled by the conductive layer, the mask layer covering the top of the conductive layer; patterning the mask layer multiple times from the edge of the top of the conductive layer, and etching the conductive layer after each patterning of the mask layer, so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

[0016] Furthermore, the method for making the top of the conductive layer present a stepped configuration with a high middle and low sides includes the following steps: forming a plurality of mask layers along the side walls of the groove in the portion of the groove not filled by the conductive layer, and arranging the plurality of mask layers in sequence from the edge to the center of the top of the conductive layer; removing the mask layers in sequence starting from the outermost mask layer, and etching the conductive layer after each mask layer is removed, so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

[0017] Furthermore, four mask layers are formed along the sidewalls of the trench in the portion of the trench not filled by the conductive layer.

[0018] Furthermore, along the direction from the edge to the center of the top of the conductive layer, the materials of the mask layer are nitride, carbon, borophosphosilicate glass, and tetraethyl orthosilicate.

[0019] The advantage of the present invention is that, compared with the top of the existing word line structure being a flat plate, the top of the ladder-type word line structure of the present invention is higher than the top of the existing word line structure, the present invention increases the area of ​​the word line structure, reduces the resistance of the word line structure, increases the control ability of the gate over the channel, and improves the ability of the transistor to drive current. In the direction perpendicular to the top of the word line structure (such as Figure 1 Although the distance between the highest point of the top of the ladder-type word line structure of the present invention and the drain electrode is reduced, the present invention adopts a step configuration, and the highest point of the top of the word line structure is parallel to the drain electrode in the direction of the top of the word line structure (such as Figure 1 The distance in the X direction is not reduced much, which is not enough to generate leakage current. That is to say, the ladder-type word line structure of the present invention can reduce the resistance of the word line structure and avoid the GIDL effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of a specific implementation mode of the ladder-type word line structure of the present invention;

[0021] Figure 2 is a structural schematic diagram of another specific implementation mode of the ladder-type word line structure of the present invention;

[0022] Figure 3 is a structural schematic diagram of another specific implementation mode of the ladder-type word line structure of the present invention;

[0023] Figure 4 It is a schematic diagram of the steps of a specific implementation method of the method for preparing a ladder-type word line structure of the present invention;

[0024] Figure 5A to Figure 5O It is a process flow chart of a specific implementation method of the preparation method of the stepped word line structure. DETAILED DESCRIPTION

[0025] The specific implementation of the ladder-type word line structure and the preparation method thereof provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 FIG. 1 is a schematic diagram of a specific implementation of the ladder-type word line structure of the present invention. Figure 1 The stepped word line structure includes a conductive layer 10, and the top of the conductive layer 10 is in a stepped configuration with a high middle and low sides.

[0027] In this specific embodiment, the top of the conductive layer 10 has four steps from the edge to the center, and the height of the steps increases from the edge to the center of the top of the conductive layer 10, thereby forming a stepped configuration with a high middle and low sides. In other specific embodiments of the present invention, the number of steps can be set according to actual conditions. For example, see Figure 2 , which is a schematic diagram of another specific embodiment of the step-type word line structure of the present invention, the top of the conductive layer 10 is not a step configuration, that is, the top of the conductive layer 10 is divided into a central area A1 and an edge area A2 surrounding the central area A1, and the height of the conductive layer in the central area A1 is greater than the height of the conductive layer in the edge area A2. Figure 3 , which is a structural schematic diagram of another specific embodiment of the stepped word line structure of the present invention. In this specific embodiment, the top of the conductive layer 10 has three steps from the edge to the center, that is, the top of the conductive layer 10 is divided into a central area A1 and a middle area A2 and an edge area A3 that surround the central area A1 in sequence. From the central area A1 to the edge area A3, the height of the conductive layer 10 decreases in sequence.

[0028] Please continue reading Figure 1 ,exist Figure 1 The dotted line B is used to schematically illustrate the position of the top of the planar word line structure in the prior art. Compared with the top of the existing word line structure being a planar configuration, the top of the ladder-type word line structure of the present invention is higher than the top of the existing word line structure. The present invention increases the area of ​​the word line structure, reduces the resistance of the word line structure, increases the control ability of the gate over the channel, and improves the ability of the transistor to drive current. In the direction perpendicular to the top of the word line structure (such as Figure 1 Although the distance between the highest point of the top of the ladder-type word line structure of the present invention and the drain electrode is reduced, the present invention adopts a step configuration, and the highest point of the top of the word line structure is parallel to the drain electrode in the direction of the top of the word line structure (such as Figure 1 The distance in the X direction is not reduced much, which is not enough to generate leakage current. That is to say, the ladder-type word line structure of the present invention can reduce the resistance of the word line structure and avoid the GIDL effect.

[0029] Preferably, in this specific embodiment, the top of the conductive layer 10 is symmetrically arranged with the center line of the conductive layer 10 as an axis. The material of the conductive layer 10 includes but is not limited to metal or metal alloy, for example, tungsten, aluminum, copper and alloys thereof.

[0030] Furthermore, the ladder-type word line structure further includes a barrier layer 11 disposed on the outer surface of the conductive layer 10. The barrier layer 11 includes but is not limited to a titanium nitride layer or a tantalum nitride layer. In this specific embodiment, the lowest point of the top of the conductive layer 10 is higher than the upper end surface of the barrier layer 11. In other specific embodiments of the present invention, the highest point of the top of the conductive layer 10 is higher than the upper end surface of the barrier layer 11, and the lowest point of the top of the conductive layer 10 is lower than the upper end surface of the barrier layer 11.

[0031] Further, the stepped word line structure further includes a gate insulating layer 12, and the gate insulating layer 12 is disposed on the outer surface of the barrier layer 11. The gate insulating layer 12 includes but is not limited to a silicon oxide insulating layer. Further, the upper end surface of the gate insulating layer 12 is higher than the highest point of the top of the conductive layer 10. In the above specific manner, the gate insulating layer 12 may cover the sidewalls of the trench 20 forming the stepped word line structure.

[0032] The invention also provides a method for preparing the ladder-type word line structure. Figure 4 FIG. 1 is a schematic diagram of a specific embodiment of a method for preparing a ladder-type word line structure of the present invention. Figure 4 The preparation method of the stepped word line structure includes the following steps: step S40, providing a substrate, wherein the substrate has a plurality of grooves arranged at intervals; step S41, filling the grooves with a conductive material to form a conductive layer, wherein the top of the conductive layer is lower than the upper edge of the groove; step S42, etching the conductive layer multiple times so that the top of the conductive layer has a stepped configuration with a high middle and low sides.

[0033] Figure 5A to Figure 5O FIG. 1 is a process flow chart of a specific embodiment of the method for preparing the step-type word line structure. In this specific embodiment, the formation of four steps is taken as an example for description.

[0034] Please refer to step S40 and Figure 5A , providing a substrate 200, wherein the substrate 200 has a plurality of grooves 210 arranged at intervals.

[0035] The substrate 200 includes, but is not limited to, silicon crystal or germanium crystal, silicon on insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof). In this step, a mask may be formed on the substrate 200, and a groove 210 may be formed on the substrate 200 by photolithography and etching processes.

[0036] Furthermore, when forming the trench 210, an oxide isolation layer 250 is also formed on the surface of the substrate 200, and the oxide isolation layer 250 does not cover the inner surface of the trench 210, but only covers the upper surface of the substrate 200. The oxide isolation layer 250 can protect the upper surface of the substrate 200 in subsequent processes to prevent it from being etched.

[0037] Please refer to step S41 and Figure 5B to Figure 5E, a conductive material is filled in the groove 210 to form a conductive layer 220 , and the top of the conductive layer 220 is lower than the upper edge of the groove 210 .

[0038] Furthermore, before forming the conductive layer 220, a step of forming a gate insulating layer 230 and a barrier layer 240 is included, and a conductive material is filled in the gate barrier layer to form the conductive layer. A specific implementation of the method for forming the conductive layer 220 is listed below.

[0039] See also Figure 5B , a gate insulating layer 230 is formed in the groove 210. The gate insulating layer 230 may be an oxide layer, which is used for insulation between the gate and the substrate. The gate insulating layer 230 may be formed by thermal oxidation. The gate insulating layer 230 at least covers the inner sidewall of the groove 210, and the gate insulating layer 230 has the same shape as the groove 210. For example, if the groove 210 is U-shaped, the gate insulating layer 230 is also U-shaped. Further, in this specific embodiment, the gate insulating layer 230 also extends outward to cover the upper surface of the oxide isolation layer 250.

[0040] See also Figure 5C , a barrier layer 240 is formed on the gate insulating layer 230, and the barrier layer 240 at least covers the inner side wall of the gate insulating layer 230. The shape of the barrier layer 240 is the same as that of the gate insulating layer 230. For example, if the shape of the gate insulating layer 230 is U-shaped, the shape of the barrier layer 240 is also U-shaped. The material of the barrier layer 240 includes but is not limited to metal nitrides, such as titanium nitride or tantalum nitride. In this specific embodiment, in addition to covering the inner side wall of the gate insulating layer 230, the barrier layer 240 also covers the upper surface of the gate insulating layer 230.

[0041] See also Figure 5D , a conductive layer 220 is formed on the barrier layer 240, and the conductive layer 220 at least fills the groove 210. The material of the conductive layer 220 includes, but is not limited to, metal or metal alloy, for example, tungsten, aluminum, copper and alloys thereof. After this step is completed, the conductive layer 220 is formed on the barrier layer 240, and the conductive layer 220 at least fills the groove 210, that is, the conductive layer 220 fills the gap formed by the inner side wall of the barrier layer 240. In this specific embodiment, the conductive layer 220 not only fills the gap formed by the inner side wall of the barrier layer 240 but also covers the upper surface of the barrier layer 240.

[0042] See also Figure 5E, etching and removing part of the conductive layer 220 and the barrier layer 240, leaving only the conductive layer 220 and the barrier layer 240 located in the groove 210. After performing this step, the top of the conductive layer 220 is lower than the upper edge of the groove 210. In this specific embodiment, the top of the barrier layer 240 is lower than the top of the conductive layer 220. In other specific embodiments, the top of the barrier layer 240 may also be flush with the top of the conductive layer 220, or the top of the barrier layer 240 may be higher than the top of the conductive layer 220.

[0043] Please refer to step S42 and Figure 5F to Figure 5N , the conductive layer is etched for multiple times, so that the top of the conductive layer is in a stepped configuration with a high middle and low sides. Specifically, the conductive layer 220 is etched for multiple times in a direction perpendicular to the top of the conductive layer, so that the top of the conductive layer 220 is in a stepped configuration with a high middle and low sides.

[0044] One method to make the top of the conductive layer present a stepped configuration with a high middle and low sides is to etch the conductive layer multiple times along the edge of the top of the conductive layer toward the center of the top of the conductive layer so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

[0045] A specific implementation of the method for making the top of the conductive layer present a stepped configuration with a high middle and low sides is listed below.

[0046] A mask layer 260 is formed on the portion of the trench 210 not filled by the conductive layer 220 , and the mask layer 260 covers the top of the conductive layer 220 . In this embodiment, the mask layer 260 also covers the top of the barrier layer 240 and the sidewalls of the gate oxide layer 230 .

[0047] See also Fig. 5F, a mask layer 260 is formed on the portion of the groove 210 that is not filled by the conductive layer 220. In this step, the mask layer 260 not only fills the portion of the groove 210 that is not filled by the conductive layer 220, but also covers the upper surface of the gate insulating layer 230. Further, the mask layer 260 may be a one-layer structure or a multi-layer structure. In this specific embodiment, the mask layer 260 is a multi-layer structure, which includes four layers, namely a first mask layer 260A, a second mask layer 260B, a third mask layer 260C and a fourth mask layer 260D. The first mask layer 260A, the second mask layer 260B, the third mask layer 260C and the fourth mask layer 260D can be selected to select a relatively large material for etching, so as to facilitate the subsequent etching process. For example, the material of the first mask layer 260A may be nitride, the material of the second mask layer 260B may be carbon, the material of the third mask layer 260C may be borophosphosilicate glass, and the material of the fourth mask layer 260D may be tetraethyl orthosilicate.

[0048] See also Figure 5G , remove the mask layer 260 covering the upper surface of the gate insulating layer 230, and only retain the mask layer 260 located in and above the trench 210 area. After this step is completed, the multi-layer mask layer is arranged in sequence from the edge to the center of the top of the conductive layer 220.

[0049] The mask layer 260 is patterned multiple times from the top edge of the conductive layer 220, and the conductive layer 220 is etched after each patterning of the mask layer 260, so that the top of the conductive layer is a step-shaped configuration with a high middle and low sides. The specific process is described as follows:

[0050] See also Figure 5H , the first mask layer 260A is removed in a direction perpendicular to the top of the conductive layer 220 to expose the top edge of the conductive layer 220. In this step, part of the first mask layer 260A at the top of the barrier layer 240 is not removed, and the upper end surface of the remaining first mask layer 260A is flush with the exposed end surface of the conductive layer 220. The remaining first mask layer 260A can protect the barrier layer 240 from being etched in subsequent processes.

[0051] See also Fig.5I , using the mask layer 260 as a mask, the conductive layer 220 is etched in a direction perpendicular to the top of the conductive layer 220 , so that the edge height of the conductive layer 220 is lower than the center height of the conductive layer 220 .

[0052] See also Figure 5J, remove the second mask layer 260B in a direction perpendicular to the top of the conductive layer 220, and expose a portion of the top of the conductive layer 220. The exposed area is located at the edge of the unetched area of ​​the top of the conductive layer 220.

[0053] See also Figure 5K , using the mask layer 260 as a mask, the conductive layer 220 is etched in a direction perpendicular to the top of the conductive layer 220 to form a secondary step. After this step is completed, the height of the exposed area of ​​the conductive layer 220 is lower than the height of the area covered by the mask layer 260 at the center of the conductive layer 220.

[0054] See also Figure 5L , the third mask layer 260C is removed in a direction perpendicular to the top of the conductive layer 220, and a partial area of ​​the top of the conductive layer 220 is exposed. The exposed area is located at the edge of the unetched area of ​​the top of the conductive layer 220.

[0055] See also Figure 5M , using the mask layer 260 as a mask, the conductive layer 220 is etched in a direction perpendicular to the top of the conductive layer 220 to form three steps. After this step is completed, the height of the exposed area of ​​the conductive layer 220 is lower than the height of the area covered by the mask layer 260 at the center of the conductive layer 220.

[0056] See also Figure 5N , remove the fourth mask layer 260D and the remaining first mask layer 260A on the upper end surface of the barrier layer 240 to expose the upper end surface of the conductive layer 220 and the upper end surface of the barrier layer 240. After this step is completed, a stepped word line structure is formed in the trench 210.

[0057] In this specific embodiment, multiple mask layers are formed and patterned in sequence to etch the conductive layer to form a stepped word line structure, which can control the width and etching depth of each step to avoid over-etching, thereby increasing the word line area while avoiding leakage current.

[0058] The method for forming the ladder-type word line structure of the present invention is not limited to the above method. In other specific embodiments of the present invention, other methods may also be used to form the ladder-type word line structure.

[0059] For further information, see Fig.5O After forming the stepped word line structure, a dielectric layer 300 is formed on the conductive layer 220, and the dielectric layer 300 fills the trench 210 and covers the upper surface of the gate insulating layer 230. The material of the dielectric layer 300 can be silicon nitride.

[0060] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A ladder-type word line structure, characterized in that: It comprises a conductive layer and a barrier layer arranged on the outer surface of the conductive layer, the top of the conductive layer is in a stepped configuration with a high middle and low sides, the lowest point of the top of the conductive layer is higher than the upper end surface of the barrier layer, and the top of the conductive layer has two steps, three steps or four steps from the edge to the center.

2. The ladder-type word line structure according to claim 1, characterized in that: The top of the conductive layer is symmetrically arranged with the center line of the conductive layer as an axis.

3. The ladder-type word line structure according to claim 1, characterized in that: The highest point of the top of the conductive layer is higher than the upper end surface of the barrier layer.

4. The ladder-type word line structure according to claim 1, characterized in that: The ladder-type word line structure further includes a gate insulating layer, and the gate insulating layer is disposed on an outer surface of the barrier layer.

5. The ladder-type word line structure according to claim 4, characterized in that: The upper end surface of the gate insulating layer is higher than the highest point of the top of the conductive layer.

6. A method for preparing a ladder-type word line structure, characterized in that: The steps include: Providing a substrate having a plurality of grooves arranged at intervals; forming a gate insulating layer and a barrier layer on the sidewalls of the trench; Filling the gate barrier layer with a conductive material to form a conductive layer, wherein the top of the conductive layer is lower than the upper edge of the trench; The conductive layer is etched multiple times so that the top of the conductive layer has a stepped configuration with a high middle and low sides, the lowest point of the top of the conductive layer is higher than the upper end surface of the barrier layer, and the top of the conductive layer has two steps, three steps, or four steps from the edge to the center.

7. The preparation method according to claim 6, characterized in that: The method for making the top of the conductive layer present a stepped configuration with a high middle and low sides includes the following steps: etching the conductive layer multiple times along a direction perpendicular to the top of the conductive layer from the edge of the top of the conductive layer to the center of the top of the conductive layer, so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

8. The preparation method according to claim 7, characterized in that: The method for making the top of the conductive layer present a stepped configuration with a high middle and low sides comprises the following steps: forming a mask layer at a portion of the trench not filled by the conductive layer, wherein the mask layer covers a top of the conductive layer; The mask layer is patterned multiple times starting from the top edge of the conductive layer, and the conductive layer is etched after each patterning of the mask layer, so that the top of the conductive layer presents a stepped configuration with a high middle and low sides.

9. The preparation method according to claim 7, characterized in that: The method for making the top of the conductive layer present a stepped configuration with a high middle and low sides comprises the following steps: forming a plurality of mask layers along the sidewalls of the trench at the portion of the trench not filled by the conductive layer, wherein the plurality of mask layers are arranged in sequence from the edge to the center of the top of the conductive layer; The mask layers are removed sequentially starting from the outermost mask layer, and the conductive layer is etched after each mask layer is removed, so that the top of the conductive layer is in a stepped configuration with a high middle and low sides.

10. The preparation method according to claim 9, characterized in that: Four mask layers are formed along the sidewalls of the trench in the portion of the trench not filled by the conductive layer.

11. The preparation method according to claim 10, characterized in that: The materials of the mask layer along the direction from the edge to the center of the top of the conductive layer are nitride, carbon, borophosphosilicate glass, and tetraethyl orthosilicate.

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