Three-dimensional semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof are disclosed. A semiconductor memory device includes: a stacked structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on a substrate; a vertical channel structure penetrating the stacked structure; and a conductive pad located on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric pattern between the semiconductor pattern and the electrode. The upper portion of the semiconductor pattern includes an impurity region containing a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0120948 filed in the Korean Intellectual Property Office on September 30, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device with improved reliability and a method of manufacturing the same. Background Art

[0004] Semiconductor devices have been highly integrated to meet the high performance and low manufacturing cost that customers may require. Since the integration of semiconductor devices is an important factor in determining product prices, the demand for highly integrated semiconductor devices is increasing. The integration of typical two-dimensional or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, so that it is greatly affected by the level of technology used to form fine patterns. However, extremely expensive processing equipment that can be used to increase the fineness of patterns may set practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device with a three-dimensionally arranged memory cell has been proposed. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a three-dimensional semiconductor memory device having improved reliability and a method of manufacturing the same.

[0006] According to some example embodiments of the inventive concept, a semiconductor memory device may include: a stacked structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on a substrate; a vertical channel structure penetrating the stacked structure; and a conductive pad located on the vertical channel structure. The vertical channel structure may include a semiconductor pattern and a vertical dielectric pattern located between the semiconductor pattern and the electrode. An upper portion of the semiconductor pattern may include an impurity region including a halogen element, the upper portion being adjacent to the conductive pad.

[0007] According to some example embodiments of the inventive concept, a semiconductor memory device may include: a stacked structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on a substrate; a vertical channel structure penetrating the stacked structure; and a conductive pad located on the vertical channel structure. The vertical channel structure may include a filling dielectric pattern, a semiconductor pattern, and a vertical dielectric pattern located between the semiconductor pattern and the electrode. The semiconductor pattern may be located between the vertical dielectric pattern and the filling dielectric pattern. The filling dielectric pattern may have a top surface lower than a top surface of the vertical dielectric pattern. The semiconductor pattern may have a top surface lower than the top surface of the vertical dielectric pattern. The uppermost portion of the top surface of the filling dielectric pattern may be located at a first horizontal height. The uppermost portion of the top surface of the semiconductor pattern may be located at a second horizontal height. The first horizontal height and the second horizontal height may be different from each other.

[0008] According to some example embodiments of the inventive concept, a semiconductor memory device may include: a stacked structure on a substrate; a vertical channel structure penetrating the stacked structure, the vertical channel structure including a filling dielectric pattern, a semiconductor pattern, and a vertical dielectric pattern located between the semiconductor pattern and the stacked structure; a conductive pad on the vertical channel structure and electrically connected to the semiconductor pattern; and a bit line electrically connected to the conductive pad. The stacked structure includes: a plurality of electrodes and a plurality of first dielectric layers alternately stacked on the substrate; and a second dielectric layer located on an uppermost electrode of the electrodes. The vertical dielectric pattern includes a blocking dielectric layer, a charge storage layer, and a tunnel dielectric layer. The charge storage layer is located between the blocking dielectric layer and the tunnel dielectric layer. The top surface of the filling dielectric pattern is located at a level different from that of the top surface of the semiconductor pattern. The conductive pad includes a first pad and a second pad on the first pad. The first pad is located on the top surface of the filling dielectric pattern and on the top surface of the semiconductor pattern. The first pad has a top surface that is concave toward the substrate. The second pad is located on the top surface of the first pad. The top surface of the second pad is coplanar with the top surface of the second dielectric layer.

[0009] According to some example embodiments of the present invention, a method for manufacturing a semiconductor memory device may include: alternately stacking dielectric layers and sacrificial layers on a substrate to form a stacked structure; forming a vertical channel structure penetrating the stacked structure, the vertical channel structure including a filling dielectric pattern, a semiconductor pattern, and a vertical dielectric pattern between the semiconductor pattern and the stacked structure; forming a conductive pad on the vertical channel structure, the conductive pad being electrically connected to the semiconductor pattern; and replacing the sacrificial layer with an electrode.

[0010] The step of forming the conductive pad may include: recessing an upper portion of the filled dielectric pattern to form a top surface of a first recess of the filled dielectric pattern; recessing an exposed upper portion of the semiconductor pattern to form a top surface of a second recess of the semiconductor pattern, wherein a horizontal height of the top surface of the second recess is different from a horizontal height of a top surface of the first recess; forming a first pad layer on the top surface of the first recess and the top surface of the second recess; recessing an upper portion of the first pad layer to form a top surface of a third recess of the first pad layer; forming a second pad layer on the first pad layer covering the top surface of the third recess; and performing a planarization process on the first pad layer and the second pad layer until the top surface of the topmost dielectric layer of the stacked structure is exposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagrams illustrating a simplified configuration of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept are shown.

[0012] Figure 2 A simplified block diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts is shown.

[0013] Figure 3 Plan views illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept are illustrated.

[0014] Figure 4 Shown along Figure 3 A cross-sectional view taken along line II'.

[0015] Figure 5 Shows Shows Figure 4 An enlarged cross-sectional view of portion M.

[0016] Figures 6 to 13 Shown along Figure 3 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0017] Figures 14 to 19 Shows Fig.11 The enlarged cross-sectional view of the portion M shown in FIG. Fig.11 Method of conductive pad.

[0018] Figure 20 to Figure 23 Shows Figure 4 is an enlarged cross-sectional view of a portion M shown in , which illustrates a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

[0019] Fig.24 Shows Fig.11 The enlarged cross-sectional view of the portion M shown in FIG. Fig.23 Method of conductive pad. DETAILED DESCRIPTION

[0020] Figure 1 Schematic diagrams illustrating a simplified configuration of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept are shown.

[0021] Reference Figure 1 , the three-dimensional semiconductor memory device may include a cell array region CAR and a peripheral circuit region. The peripheral circuit region may include a row decoder region ROW DCR, a page buffer region PBR, a column decoder region COL DCR, and a control circuit region (not shown). In some embodiments, a connection region CTR may be provided between the cell array region CAR and each row decoder region ROW DCR.

[0022] The cell array region CAR may include a memory cell array including a plurality of memory cells. In some embodiments, the memory cell array may include three-dimensionally arranged memory cells and a plurality of word lines and bit lines electrically connected to the memory cells.

[0023] The row decoder region ROW DCR may include a row decoder for selecting a word line of a memory cell array, and the connection region CTR may include a connection line structure for electrically connecting the memory cell array to the row decoder. Based on the address information, the row decoder may select one of the word lines of the memory cell array. The row decoder may provide a word line voltage to the selected word line and the unselected word line in response to a control signal from the control circuit.

[0024] The page buffer region PBR may include a page buffer that reads data stored in a memory cell. Depending on the operation mode, the page buffer may temporarily store data to be stored in a memory cell or sense data stored in a memory cell. The page buffer may act as a write driver circuit in a programming operation mode and as a sense amplifier circuit in a read operation mode.

[0025] The column decoder region COL DCR may include a column decoder connected to the bit lines of the memory cell array. The column decoder may provide a data transmission path between the page buffer and an external device (eg, a memory controller).

[0026] Figure 2 A simplified block diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts is shown.

[0027] Reference Figure 2, the cell array area CAR may include a plurality of cell array blocks BLK1, BLK2 ... and BLKn. Each of the cell array blocks BLK1, BLK2 ... and BLKn may include a stacked structure, the stacked structure including electrodes stacked along a third direction D3 on a plane extending along the first direction D1 and the second direction D2. The stacked structure may be combined with a plurality of vertical channel structures (or semiconductor pillars) to form a three-dimensionally arranged memory cell. In addition, each of the cell array blocks BLK1, BLK2 ... and BLKn may include a bit line electrically connected to the memory cell.

[0028] Figure 3 Plan views illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept are illustrated. Figure 4 Shown along Figure 3 A cross-sectional view taken along line II'. Figure 5 Shows Shows Figure 4 An enlarged cross-sectional view of portion M.

[0029] Reference Figure 3 , Figure 4 and Figure 5 , a substrate 100 including a cell array region CAR may be provided. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The substrate 100 may have a first conductivity type (eg, p-type).

[0030] The cell array block BLK may be disposed on the substrate 100. The cell array block BLK may include a stack structure ST including a first dielectric layer IL1, an electrode EL, and a blocking layer STL. The stack structure ST may extend along the second direction D2 on the cell array region CAR. Figure 3 , a single stack structure ST is shown in FIG. 1 , but example embodiments are not limited thereto and a plurality of stack structures ST may be provided. The plurality of stack structures ST may be arranged along the first direction D1 intersecting the second direction D2 .

[0031] The common source region CSR may be disposed on opposite sides of the stacked structure ST. The common source region CSR may be formed on / in an upper portion of the substrate 100. The common source region CSR may extend in the second direction D2 in parallel with the stacked structure ST. The common source region CSR may be doped with impurities to have a second conductivity type. For example, the common source region CSR may be doped with impurities such as arsenic (As) or phosphorus (P) to have an n-type conductivity type.

[0032] The common source plug CSP may be coupled to the common source region CSR. The common source plug CSP may vertically overlap the common source region CSR. The common source plug CSP may extend in the second direction D2 parallel to the stack structure ST. A dielectric spacer ISP may be interposed between the common source plug CSP and the stack structure ST.

[0033] The stack structure ST may include first dielectric layers IL1 and electrodes EL vertically and alternately stacked on the substrate 100. The stack structure ST may further include a second dielectric layer IL2 on the uppermost electrode EL. The thickness of the second dielectric layer IL2 may be greater than that of the first dielectric layer IL1.

[0034] The electrodes EL of the stack structure ST may be stacked along a third direction D3 perpendicular to the top surface of the substrate 100. Vertically adjacent ones of the electrodes EL may be vertically separated from each other by the first dielectric layer IL1 disposed therebetween.

[0035] The lowermost electrode EL of the stacked structure ST may be a lower selection line. The uppermost electrode EL of the stacked structure ST may be an upper selection line. The remaining electrodes EL except the lower selection line and the upper selection line may be word lines. The separation dielectric pattern SEP may extend in the second direction D2 while crossing the uppermost electrode EL (or the upper selection line). The separation dielectric pattern SEP may have a top surface coplanar with the top surface of the second dielectric layer IL2. The separation dielectric pattern SEP may include a dielectric material (e.g., silicon oxide).

[0036] The electrode EL may include a conductive material selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The first dielectric layer IL1 and the second dielectric layer IL2 may include a silicon oxide layer.

[0037] A plurality of vertical channel structures VS penetrating the stacked structure ST may be provided on the cell array region CAR. The vertical channel structures VS may be provided in corresponding channel holes CH of the stacked structure ST. For example, the first column C1 may be composed of four vertical channel structures VS arranged along the first direction D1, and the second column C2 may be composed of five vertical channel structures VS arranged along the first direction D1. The first column C1 and the second column C2 may be repeatedly and alternately arranged along the second direction D2. Each vertical channel structure VS may have a diameter that gradually decreases as the distance from the substrate 100 decreases.

[0038] Each vertical channel structure VS may include a vertical dielectric pattern VP, a semiconductor pattern SP, and a filling dielectric pattern VI. The vertical dielectric pattern VP may extend toward the substrate 100 and along the inner wall of the channel hole CH. The semiconductor pattern SP may cover the inner wall of the vertical dielectric pattern VP and may extend toward the substrate 100 together with the vertical dielectric pattern VP.

[0039] The lower portion of the channel hole CH may extend into the substrate 100. For example, the bottom CHb of the channel hole CH may be lower than the top surface of the substrate 100. The recess RS may be defined to extend from the bottom CHb of the channel hole CH toward the bottom surface of the substrate 100. The lower portion of the semiconductor pattern SP may fill the recess RS and may directly contact the substrate 100.

[0040] The semiconductor pattern SP may have a bottom-closed tubular shape. The filling dielectric pattern VI may fill the inside of the semiconductor pattern SP. The semiconductor pattern SP may serve as a channel of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

[0041] For example, the semiconductor pattern SP may include silicon (Si), germanium (Ge), or a mixture thereof. The semiconductor pattern SP may have a single crystal structure or a polycrystalline structure. The semiconductor pattern SP may be undoped or doped with impurities to have the same first conductivity type as the substrate 100.

[0042] Conductive pads PAD may be disposed on each of the vertical channel structures VS. The conductive pads PAD may include first pads PAD1 on the vertical channel structures VS and second pads PAD2 on the first pads PAD1. The conductive pads PAD may have a top surface coplanar with a top surface of the second dielectric layer IL2.

[0043] Refer again Figure 5 The conductive pad PAD and the upper portion of the vertical channel structure VS will be discussed in detail below. The vertical dielectric pattern VP may include a blocking dielectric layer BK, a charge storage layer TL, and a tunnel dielectric layer TN interposed between the electrode EL and the semiconductor pattern SP.

[0044] For example, the blocking dielectric layer BK may be disposed on the electrode EL and the first dielectric layer IL1 and the second dielectric layer IL2. The blocking dielectric layer BK may cover the inner sidewall of the electrode EL and the inner sidewall of the first dielectric layer IL1 and the second dielectric layer IL2. For example, the blocking dielectric layer BK may cover the inner wall of the channel hole CH. The charge storage layer TL may be disposed on the blocking dielectric layer BK. The tunnel dielectric layer TN may be disposed on the charge storage layer TL. The tunnel dielectric layer TN may cover the outer wall of the semiconductor pattern SP and the outer wall of the conductive pad PAD. The charge storage layer TL may be inserted between the tunnel dielectric layer TN and the blocking dielectric layer BK.

[0045] For example, the blocking dielectric layer BK may include a silicon oxide layer. The charge storage layer TL may include a silicon nitride layer, a silicon oxynitride layer, or a silicon-rich nitride layer. The tunnel dielectric layer TN may include a material having a band gap greater than the band gap of the charge storage layer TL. The tunnel dielectric layer TN may include a silicon oxide layer or a high-k dielectric layer such as an aluminum oxide layer or a hafnium oxide layer.

[0046] A NAND flash memory device may be employed as a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. The charge storage layer TL between the electrode EL and the semiconductor pattern SP may be a data storage area of ​​the NAND flash memory device. Data stored in the charge storage layer TL may be changed by Fowler-Nordheim tunneling caused by a voltage difference between the electrode EL and the semiconductor pattern SP.

[0047] The vertical dielectric pattern VP may have a top surface coplanar with the top surface of the second dielectric layer IL2. For example, the top surfaces of the blocking dielectric layer BK, the charge storage layer TL, and the tunnel dielectric layer TN may all be coplanar with the top surface of the second dielectric layer IL2.

[0048] The filling dielectric pattern VI may have a first recessed top surface RSt1. The first recessed top surface RSt1 may have an uppermost portion at a first level LV1. The first recessed top surface RSt1 may be recessed toward the substrate 100.

[0049] As used herein, the term "recessed" may refer to a top surface lower than that of the second dielectric layer IL2 and / or lower than that of the vertical dielectric pattern VP. Although the "recessed" top surface may be a concave surface, it is not limited thereto and may be, for example, a diagonally inclined surface.

[0050] The semiconductor pattern SP may have a second recessed top surface RSt2. The second recessed top surface RSt2 may have an uppermost portion at a second level LV2. The second level LV2 may be lower than the first level LV1. A distance from the first level LV1 to the second level LV2 may fall within 10 angstroms. to The top surface RSt2 of the second recess may be adjacent to the top surface RSt1 of the first recess.

[0051] The upper portion of the semiconductor pattern SP may include an impurity region IMR. The impurity region IMR may be located below the top surface RSt2 of the second recess. The impurity region IMR may include a halogen element as an impurity. For example, the impurity region IMR may include at least one halogen element, such as fluorine (F), chlorine (Cl), or bromine (Br). The semiconductor pattern SP may have a grain boundary between crystals. The impurity may remain in the grain boundary. The atomic percentage or impurity concentration of the halogen element in the impurity region IMR may fall within the range of 1at% to 5at%. As an embodiment of the inventive concept, the impurity region IMR may further include at least one impurity including oxygen (O), carbon (C), and nitrogen (N).

[0052] The impurity region IMR may have a bottom at a third level LV3. The third level LV3 may be lower than the second level LV2. A distance from the second level LV2 to the third level LV3 may fall within to For example, the impurity region IMR may have to Depth.

[0053] The conductive pad PAD may be disposed on the semiconductor pattern SP and the filling dielectric pattern VI. The conductive pad PAD may be disposed in a space defined by the inner wall of the vertical dielectric pattern VP. For example, the conductive pad PAD may have a side wall in contact with the inner wall of the vertical dielectric pattern VP. The conductive pad PAD may have a top surface coplanar with the top surface of the vertical dielectric pattern VP.

[0054] The first pad PAD1 of the conductive pad PAD may be located on the top surface RSt1 of the first depression and the top surface RSt2 of the second depression (e.g., directly contacting / covering the top surface RSt1 of the first depression and the top surface RSt2 of the second depression). The first pad PAD1 may have a first section and a second section overlapping with the top surface RSt1 of the first depression and the top surface RSt2 of the second depression, respectively (e.g., covering the top surface RSt1 of the first depression and the top surface RSt2 of the second depression), and the first section may be located at a position higher than the second section. For example, the second section of the first pad PAD1 may protrude from the first section toward the semiconductor pattern SP. The first pad PAD1 may have a top surface RSt3 of the third depression. The top surface RSt3 of the third depression may be recessed toward the substrate 100.

[0055] The second pad PAD2 may be disposed on the first pad PAD1 of the conductive pad PAD. The second pad PAD2 may be located on the top surface RSt3 of the third depression (e.g., covering the top surface RSt3 of the third depression). An oxide may be inserted between the first pad PAD1 and the second pad PAD2. For example, the first pad PAD1 and the second pad PAD2 may have a boundary composed of an oxide therebetween. The boundary may have the same profile as the profile of the top surface RSt3 of the third depression.

[0056] The first pad PAD1 and the second pad PAD2 may include the same material. For example, the conductive pad PAD may include silicon (Si), germanium (Ge), or a mixture thereof. The conductive pad PAD may be amorphous. The conductive pad PAD may have a second conductivity type (eg, n-type).

[0057] Still refer to Figure 3 , Figure 4 and Figure 5 , a third dielectric layer IL3 and a fourth dielectric layer IL4 stacked sequentially may be disposed on the stack structure ST. A bit line BL extending along the first direction D1 may be disposed on the fourth dielectric layer IL4. A bit line contact plug BPLG may be disposed between the bit line BL and the conductive pad PAD, and the bit line contact plug BPLG penetrates the fourth dielectric layer IL4 and the third dielectric layer IL3. The bit line BL may be electrically connected to the vertical channel structure VS through the bit line contact plug BPLG and the conductive pad PAD.

[0058] The semiconductor memory device according to the present embodiment may be constructed such that the upper portion of the semiconductor pattern SP may be recessed to have a second recessed top surface RSt2. The conductive pad PAD on the second recessed top surface RSt2 may satisfactorily and completely fill the upper portion of the channel hole CH. Therefore, the conductive pad PAD may be free from process defects, and thus the yield of the semiconductor device may be increased and the reliability may be improved.

[0059] Figures 6 to 13 Shown along Figure 3 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figures 14 to 19 Shows Fig.11 The enlarged cross-sectional view of the portion M shown in FIG. Fig.11 Method of conductive pad.

[0060] Reference Figure 3 and Figure 6 , a stack structure ST may be formed by vertically and alternately stacking first dielectric layers IL1 and sacrificial layers HL on the entire surface of the substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0061] Forming the stack structure ST may further include forming a second dielectric layer IL2 on the uppermost sacrificial layer HL and forming a mask layer ML on the second dielectric layer IL2. The second dielectric layer IL2 may be formed to be thicker than the first dielectric layer IL1.

[0062] The first dielectric layer IL1, the sacrificial layer HL, and the second dielectric layer IL2 may be deposited by using thermal chemical vapor deposition (CVD), plasma enhanced CVD, physical CVD, or atomic layer deposition (ALD). The first dielectric layer IL1 and the second dielectric layer IL2 may be formed of a silicon oxide layer. The sacrificial layer HL may be formed of a silicon nitride layer or a silicon oxynitride layer. The mask layer ML may be formed of a silicon nitride layer or a silicon oxynitride layer.

[0063] Reference Figure 3 and Figure 7 , the upper portion of the stacked structure ST may be patterned to form a channel hole CH. For example, the formation of the channel hole CH may include: forming a mask pattern MP having an opening OP on the stacked structure ST, the opening OP defining a region where the channel hole CH is formed; and performing an anisotropic etching process using the mask pattern MP as an etching mask to anisotropically etch the stacked structure ST.

[0064] The channel holes CH may be over-etched during the anisotropic etching process, and thus the channel holes CH may extend into the substrate 100. A bottom CHb of each of the channel holes CH may be lower than a top surface of the substrate 100.

[0065] Reference Figure 3 and Figure 8 , the mask pattern MP may be selectively removed. A vertical dielectric layer VPL and a sacrificial semiconductor layer SSL may be sequentially formed in the channel hole CH. For example, the formation of the vertical dielectric layer VPL may include: conformally forming a blocking dielectric layer on an inner wall of each channel hole CH; conformally forming a charge storage layer on the blocking dielectric layer; and conformally forming a tunnel dielectric layer on the charge storage layer. The vertical dielectric layer VPL may cover a bottom CHb of each channel hole CH.

[0066] For example, the blocking dielectric layer may include a silicon oxide layer. The charge storage layer may include a silicon nitride layer, a silicon oxynitride layer, or a silicon-rich nitride layer. The tunnel dielectric layer may include a silicon oxide layer or a high-k dielectric layer such as an aluminum oxide layer or a hafnium oxide layer. The blocking dielectric layer, the charge storage layer, and the tunnel dielectric layer may be formed by using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0067] The sacrificial semiconductor layer SSL may be conformally formed on the vertical dielectric layer VPL in each channel hole CH. For example, the sacrificial semiconductor layer SSL may include silicon (Si), germanium (Ge) or a mixture thereof. The sacrificial semiconductor layer SSL may be formed by using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0068] Reference Figure 3 and Fig. 9 , an anisotropic etching process may be performed on the entire surface of the substrate 100 , thereby forming recesses RS extending from corresponding bottoms CHb of the channel holes CH toward the bottom surface of the substrate 100 .

[0069] The anisotropic etching process may be performed so that a portion of the sacrificial semiconductor layer SSL located on the inner wall of the channel hole CH may be used as an etching mask to etch the vertical dielectric layer VPL and a portion of the sacrificial semiconductor layer SSL formed on the bottom CHb of the channel hole CH. The anisotropic etching process may continue until the upper portion of the substrate 100 is overetched to form a recess RS.

[0070] During the anisotropic etching process, the vertical dielectric layer VPL may be removed from the bottom CHb of the channel hole CH, so that the vertical dielectric pattern VP may be formed to cover the inner wall of the channel hole CH. The recess RS and the channel hole CH may expose the substrate 100 .

[0071] Reference Figure 3 and Fig.10 , the sacrificial semiconductor layer SSL may be selectively removed. Then, a semiconductor pattern SP may be formed in each channel hole CH. A lower portion of the semiconductor pattern SP may fill the recess RS. A lower portion of the semiconductor pattern SP may be directly connected to the substrate 100 .

[0072] The semiconductor pattern SP may be conformally formed on the vertical dielectric pattern VP in each channel hole CH. For example, the semiconductor pattern SP may include silicon (Si), germanium (Ge), or a mixture thereof. The semiconductor pattern SP may be formed by using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0073] The filling dielectric pattern VI may be formed to completely fill each channel hole CH. The vertical channel structure VS may be composed of a vertical dielectric pattern VP, a semiconductor pattern SP, and a filling dielectric pattern VI formed in each channel hole CH. Thereafter, a planarization process may be performed until the top surface of the mask layer ML is exposed. Therefore, the vertical channel structure VS may have a top surface coplanar with the top surface of the mask layer ML.

[0074] Reference Figure 3 and Fig.11, a conductive pad PAD may be formed in / on the upper portion of each channel hole CH. The conductive pad PAD may be formed on the vertical channel structure VS. The formation of the conductive pad PAD will refer to Figures 14 to 19 Further detailed discussion.

[0075] Reference Fig.14 , Fig.10 The resulting structure may be subjected to a first etching process to recess the upper portion of the filling dielectric pattern VI. The first etching process may include a dry or wet etching process that selectively etches oxide. During the first etching process, the filling dielectric pattern VI may be recessed to have a first recessed top surface RSt1. The first recessed top surface RSt1 may have an uppermost portion located at a first horizontal height LV1. The first horizontal height LV1 may be lower than the top surface of the second dielectric layer IL2.

[0076] During the first etching process, the upper portion of the vertical dielectric pattern VP may also be etched. However, the vertical dielectric pattern VP may be less etched than the filling dielectric pattern VI. Therefore, the vertical dielectric pattern VP may have a top surface higher than the level of the top surface of the second dielectric layer IL2.

[0077] After the first etching process, the upper portion SPu of the semiconductor pattern SP may be exposed. Since there is no supporting layer, the exposed upper portion SPu of the semiconductor pattern SP may become bent. When a conductive pad PAD is subsequently deposited while the upper portion SPu remains on the semiconductor pattern SP, the bent upper portion SPu may result in incomplete formation of the conductive pad PAD and cause defects such as voids to occur.

[0078] Reference Fig.15 The second etching process may be performed to recess the upper portion SPu of the semiconductor pattern SP. The second etching process may include a dry etching process that selectively etches the semiconductor material (eg, Si, Ge, or SiGe). The second etching process may use an etching gas containing a halogen element, such as Cl 2 , HBr, F 2 or ClF 3 .

[0079] The upper portion SPu of the semiconductor pattern SP may be removed during the second etching process. During the second etching process, the semiconductor pattern SP may be recessed to have a second recessed top surface RSt2. The second recessed top surface RSt2 may have an uppermost portion located at a second level LV2. The second level LV2 may be lower than the first level LV1.

[0080] During the second etching process, a halogen element (e.g., fluorine (F), chlorine (Cl), and / or bromine (Br)) contained in the etching gas may diffuse into the semiconductor pattern SP. Since the semiconductor pattern SP has a grain boundary between crystals, the halogen element may diffuse into the grain boundary and may remain in the grain boundary. The halogen element may diffuse into the semiconductor pattern SP, and thus an impurity region IMR may be formed on / in an upper portion of the semiconductor pattern SP. The impurity region IMR may be located directly below the top surface RSt2 of the second recess.

[0081] An atomic percentage or an impurity concentration of the halogen element in the impurity region IMR may fall within a range of 1 at % to 5 at %. The impurity region IMR may have a bottom located at a third level LV3 . The third level LV3 may be lower than the second level LV2 .

[0082] Reference Fig.16 , the first pad layer PAL1 may be formed on the top surface RSt1 of the first recess and the top surface RSt2 of the second recess. The first pad layer PAL1 may be formed on (e.g., covering) the vertical dielectric pattern VP and the mask layer ML. The first pad layer PAL1 may include silicon (Si), germanium (Ge), or a mixture thereof. The first pad layer PAL1 may be formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0083] Reference Fig.17 , a third etching process may be performed to recess the upper portion of the first pad layer PAL1. The third etching process may include a wet or dry etching process that selectively etches a semiconductor material (e.g., Si, Ge, or SiGe). During the third etching process, the first pad layer PAL1 may be recessed to have a third recessed top surface RSt3. The third recessed top surface RSt3 may be recessed toward the substrate 100.

[0084] Reference Fig.18 , the second pad layer PAL2 may be formed on the first pad layer PAL1. The second pad layer PAL2 may be formed to cover the top surface RSt3 of the third recess. The second pad layer PAL2 may include the same semiconductor material as the semiconductor material of the first pad layer PAL1. The second pad layer PAL2 may be formed by using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0085] Before forming the second pad layer PAL2, an oxide may be formed on the top surface RSt3 of the third recess of the first pad layer PAL1. In this case, a boundary composed of the oxide may be formed between the first pad layer PAL1 and the second pad layer PAL2.

[0086] According to some embodiments of the present inventive concept, the process from Fig.15 The second etching process to Fig.18 For example, the deposition process of the second pad layer PAL2 may be performed sequentially without breaking the vacuum. Fig.15 The second etching process to Fig.18 Therefore, impurities such as oxygen (O), carbon (C), and / or nitrogen (N) may not exist between the first pad layer PAL1 and the top surface RSt2 of the second recess of the semiconductor pattern SP.

[0087] According to other embodiments of the present invention, it is possible to execute Fig.16 The deposition process for the first pad layer PAL1 is Fig.18 The deposition process for the second pad layer PAL2 is performed ex-situ in a different processing facility. Fig.15 For example, in the second etching process Fig.15 After the second etching process of the substrate 100, the entire surface of the substrate 100 may be exposed to air. In this case, impurities such as oxygen (O), carbon (C), and / or nitrogen (N) may additionally exist between the first pad layer PAL1 and the second recessed top surface RSt2 of the semiconductor pattern SP. For example, the impurity region IMR may further contain at least one impurity selected from the group consisting of oxygen (O), carbon (C), and nitrogen (N).

[0088] Reference Fig.19 , a planarization process may be performed until the top surface of the second dielectric layer IL2 is exposed. Thus, the first pad layer PAL1 and the second pad layer PAL2 may be formed as the first pad PAD1 and the second pad PAD2, respectively. The first pad PAD1 and the second pad PAD2 may constitute a conductive pad PAD. During the planarization process, the mask layer ML may be completely removed. The planarization process may make the top surfaces of the vertical dielectric pattern VP and the conductive pad PAD coplanar with the top surface of the second dielectric layer IL2.

[0089] Reference Figure 3 and Fig.12 , a separation dielectric pattern SEP may be formed in an upper portion of the stacked structure ST. The separation dielectric pattern SEP may be formed to extend in the second direction D2. For example, the formation of the separation dielectric pattern SEP may include: forming a recess by etching the second dielectric layer IL2 and the uppermost sacrificial layer HL; and filling the recess with a dielectric layer.

[0090] The third dielectric layer IL3 may be formed on the stacked structure ST. The third dielectric layer IL3 may cover the conductive pad PAD and the separation dielectric pattern SEP. The third dielectric layer IL3 and the stacked structure ST may be patterned to form a trench TR penetrating the stacked structure ST. The trench TR may partially expose the substrate 100. The trench TR may extend in the second direction D2 along the stacked structure ST.

[0091] Reference Figure 3 and Fig.13 , the sacrificial layer HL may be replaced by a corresponding electrode EL. For example, the sacrificial layer HL exposed to the trench TR may be selectively removed to form an empty space. The sacrificial layer HL may be removed using a wet etching process capable of selectively etching the sacrificial layer HL. A conductive material may be deposited on the substrate 100 to fill the empty space from which the sacrificial layer HL is removed. The conductive material may be selected from doped semiconductors, metals, and transition metals. The electrode EL may be formed of a conductive material filling the empty space.

[0092] Portions of the substrate 100 exposed to the trenches TR may be doped with impurities to form common source regions CSR. Dielectric spacers ISP and common source plugs CSP may be formed to sequentially fill each trench TR. The common source plugs CSP may be coupled to the common source regions CSR.

[0093] Refer again Figure 3 and Figure 4 , a fourth dielectric layer IL4 may be formed on the third dielectric layer IL3. A bit line contact plug BPLG may be formed to penetrate the third dielectric layer IL3 and the fourth dielectric layer IL4 and be coupled to the corresponding conductive pad PAD. On the fourth dielectric layer IL4, a bit line BL may be formed to be electrically connected to the bit line contact plug BPLG.

[0094] In the manufacturing method according to some embodiments of the present inventive concept, the upper portion SPu of the semiconductor pattern SP may be recessed before forming the conductive pad PAD, so that the occurrence of process defects such as voids caused by the conductive pad PAD not completely filling the upper portion of the channel hole CH may be suppressed / prevented. Therefore, the yield of the semiconductor device may be improved and the reliability may be improved.

[0095] Figure 20 to Figure 23 Shows Figure 4 The enlarged cross-sectional view of the portion M shown in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the present invention. In the following embodiments, the reference to the above referenced Figure 3 , Figure 4 and Figure 5 The technical features discussed are detailed descriptions of the repeated technical features, and their differences will be discussed in detail.

[0096] As an embodiment of the present invention, refer to Figure 3 , Figure 4 and Fig. 20 , the first pad PAD1 may include at least one gap AG, such as an air gap. The gap AG may be any void or gap, and need not be filled with air. The gap AG may be adjacent to the top surface RSt2 of the second recess. When the first pad PAD1 is formed, the gap AG may be generated due to the height difference between the top surface RSt1 of the first recess and the top surface RSt2 of the second recess.

[0097] As an embodiment of the present invention, refer to Figure 3 , Figure 4 and Fig.21 , the vertical dielectric pattern VP may have a fourth recessed top surface RSt4. Because the vertical dielectric pattern VP is recessed, the first pad PAD1 may have a sidewall in contact with an inner wall of the second dielectric layer IL2 (or an inner wall of the channel hole CH).

[0098] The top surface of the blocking dielectric layer BK may be higher than the top surface of the tunnel dielectric layer TN. The top surface of the blocking dielectric layer BK may have an uppermost portion located at a fourth horizontal height LV4. The top surface of the charge storage layer TL may be higher than the top surface of the blocking dielectric layer BK. The top surface of the charge storage layer TL may have an uppermost portion located at a fifth horizontal height LV5. The fourth horizontal height LV4 may be higher than the second horizontal height LV2. The fifth horizontal height LV5 may be higher than the fourth horizontal height LV4.

[0099] The charge storage layer TL may have greater etching resistance than the blocking dielectric layer BK and the tunnel dielectric layer TN. Therefore, even when the vertical dielectric pattern VP is recessed, the top surface of the charge storage layer TL may be located higher than the top surfaces of the blocking dielectric layer BK and the tunnel dielectric layer TN.

[0100] As an embodiment of the present invention, refer to Figure 3 , Figure 4 and Fig. 22 , the second recessed top surface RSt2 of the semiconductor pattern SP may be higher than the top surface RSt1 of the first recess filled with the dielectric pattern VI. For example, the second level LV2 at which the uppermost portion of the second recessed top surface RSt2 is located may be higher than the first level LV1 at which the uppermost portion of the first recessed top surface RSt1 is located. When the semiconductor pattern SP is relatively less recessed than the filled dielectric pattern VI, the second recessed top surface RSt2 may become higher than the first recessed top surface RSt1.

[0101] As an embodiment of the present invention, refer to Figure 3 , Figure 4 and Fig.23 , the conductive pad PAD may be formed of a single conductive layer. Figure 5 According to the example shown in FIG. 1 , the conductive pad PAD according to the present embodiment may not be divided into the first pad PAD1 and the second pad PAD2. The conductive pad PAD may directly cover the top surface RSt1 of the first recess filling the dielectric pattern VI and the top surface RSt2 of the second recess of the semiconductor pattern SP. The top surface of the conductive pad PAD may be coplanar with the top surface of the vertical dielectric pattern VP. The top surface of the conductive pad PAD may be coplanar with the top surface of the second dielectric layer IL2.

[0102] Fig.24 Shows Fig.11 The enlarged cross-sectional view of the portion M shown in FIG. Fig.23 Method of conductive pad. Fig.24 , the first pad layer PAL1 may be formed on Fig.15 The first pad layer PAL1 may be formed to cover the vertical dielectric pattern VP and the mask layer ML. The first pad layer PAL1 may be formed to completely fill the upper portion of the channel hole CH. Subsequently, the first pad layer PAL1 may undergo a planarization process to form a conductive pad PAD.

[0103] The semiconductor memory device according to some example embodiments of the present invention may include a semiconductor pattern with an upper recess. The upper portion of the channel hole may be satisfactorily and completely filled with a conductive pad formed on the recessed semiconductor pattern. Therefore, the conductive pad may be free from process defects, which may lead to an increase in the yield of the semiconductor device and an improvement in the reliability of the semiconductor device.

[0104] Although the present invention has been described in conjunction with some example embodiments of the inventive concept illustrated in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the inventive concept.

Claims

1. A semiconductor memory device, comprising: A stacked structure comprising a plurality of electrodes and a plurality of dielectric layers alternately stacked on a substrate; a vertical channel structure penetrating the stacked structure; and a conductive pad located on the vertical channel structure, The vertical channel structure includes a semiconductor pattern and a vertical dielectric pattern located between the semiconductor pattern and the plurality of electrodes. wherein an upper portion of the semiconductor pattern includes an impurity region, the impurity region includes a halogen element, the upper portion is adjacent to the conductive pad, and The top surface of the semiconductor pattern is a concave surface or an inclined surface whose level decreases away from the vertical dielectric pattern.

2. The semiconductor memory device according to claim 1, in, The vertical channel structure further includes a filling dielectric pattern, wherein the semiconductor pattern is located between the vertical dielectric pattern and the filling dielectric pattern, and The filling dielectric pattern has a top surface lower than a top surface of the vertical dielectric pattern.

3. The semiconductor memory device according to claim 2, in, The semiconductor pattern has the top surface lower than the top surface of the vertical dielectric pattern, and The conductive pad is located on the top surface of the filling dielectric pattern and on the top surface of the semiconductor pattern. 4 . The semiconductor memory device of claim 3 , wherein the conductive pad is on an upper portion of a sidewall of the filling dielectric pattern, the upper portion of the sidewall protruding upward beyond the top surface of the semiconductor pattern.

5. The semiconductor memory device according to claim 3, in, an uppermost portion of the top surface of the filled dielectric pattern is located at a first level, wherein an uppermost portion of the top surface of the semiconductor pattern is located at a second horizontal height, and Wherein, the second level is lower than the first level. 6 . The semiconductor memory device of claim 3 , wherein the conductive pad includes a gap adjacent to the top surface of the semiconductor pattern.

7. The semiconductor memory device according to claim 3, in, an uppermost portion of the top surface of the filled dielectric pattern is located at a first level, wherein an uppermost portion of the top surface of the semiconductor pattern is located at a second horizontal height, and Wherein, the second level is higher than the first level.

8. The semiconductor memory device according to claim 1, in, The halogen element includes at least one of fluorine, chlorine and bromine, and Wherein, the atomic percentage of the halogen element in the impurity region is in the range of 1 at % to 5 at %.

9. The semiconductor memory device according to claim 1, in, The conductive pad includes a first pad and a second pad on the first pad, wherein the second pad is on the top surface of the first pad, and The semiconductor memory device further includes an oxide boundary between the second pad and the top surface of the first pad.

10. The semiconductor memory device according to claim 1, wherein the impurity region further includes oxygen impurities, carbon impurities, or nitrogen impurities.

11. A semiconductor memory device comprising: A stacked structure comprising a plurality of electrodes and a plurality of dielectric layers alternately stacked on a substrate; a vertical channel structure penetrating the stacked structure; and a conductive pad located on the vertical channel structure, The vertical channel structure includes a filling dielectric pattern, a semiconductor pattern, and a vertical dielectric pattern located between the semiconductor pattern and the plurality of electrodes. Wherein, the semiconductor pattern is located between the vertical dielectric pattern and the filling dielectric pattern, wherein the filling dielectric pattern has a top surface lower than a top surface of the vertical dielectric pattern, wherein the semiconductor pattern has a top surface lower than the top surface of the vertical dielectric pattern, wherein an uppermost portion of the top surface of the filled dielectric pattern is located at a first horizontal height, wherein an uppermost portion of the top surface of the semiconductor pattern is located at a second horizontal height, wherein the first level and the second level are different from each other, wherein the upper portion of the semiconductor pattern includes an impurity region, the impurity region includes at least one halogen element including fluorine, chlorine or bromine, the upper portion is adjacent to the conductive pad, and The top surface of the semiconductor pattern is a concave surface or an inclined surface whose level decreases away from the vertical dielectric pattern.

12. The semiconductor memory device according to claim 11, in, The bottom of the impurity region is located at a third level, and Wherein, the distance from the second level to the third level is in the range of 100 angstroms to 1000 angstroms. 13 . The semiconductor memory device of claim 11 , wherein the top surface of the filling dielectric pattern is recessed toward the substrate.

14. The semiconductor memory device according to claim 11, in, The vertical dielectric pattern includes a blocking dielectric layer, a charge storage layer and a tunnel dielectric layer, The charge storage layer is located between the blocking dielectric layer and the tunnel dielectric layer, and Wherein, an uppermost portion of a top surface of the charge storage layer is located at a level higher than a level of an uppermost portion of a top surface of the blocking dielectric layer.

15. A semiconductor memory device comprising: a stacked structure on a substrate; a vertical channel structure penetrating the stacked structure, the vertical channel structure comprising a filling dielectric pattern, a semiconductor pattern, and a vertical dielectric pattern located between the semiconductor pattern and the stacked structure; a conductive pad on the vertical channel structure and electrically connected to the semiconductor pattern; and a bit line electrically connected to the conductive pad, The stacked structure includes: a plurality of electrodes and a plurality of first dielectric layers alternately stacked on the substrate; and a second dielectric layer located on the topmost electrode of the plurality of electrodes. Wherein, the vertical dielectric pattern includes a blocking dielectric layer, a charge storage layer, and a tunnel dielectric layer. Wherein, the charge storage layer is located between the blocking dielectric layer and the tunnel dielectric layer, wherein a top surface of the filled dielectric pattern is located at a level different from a level of a top surface of the semiconductor pattern, The conductive pad includes a first pad and a second pad on the first pad. wherein the first pad is located on the top surface of the filling dielectric pattern and on the top surface of the semiconductor pattern, wherein the first pad has a top surface that is concave toward the substrate, wherein the second pad is located on the top surface of the first pad, wherein the top surface of the second pad is coplanar with the top surface of the second dielectric layer, wherein the upper portion of the semiconductor pattern includes an impurity region, the impurity region includes at least one halogen element including fluorine, chlorine or bromine, the upper portion is adjacent to the conductive pad, and The top surface of the semiconductor pattern is a concave surface or an inclined surface whose level decreases away from the vertical dielectric pattern. 16 . The semiconductor memory device according to claim 15 , wherein an atomic percentage of the at least one halogen element in the impurity region is in a range of 1 at % to 5 at %. 17 . The semiconductor memory device of claim 15 , wherein the conductive pad includes a gap adjacent to the top surface of the semiconductor pattern. 18 . The semiconductor memory device according to claim 15 , wherein an uppermost portion of a top surface of the charge storage layer is located at a level higher than a level of an uppermost portion of a top surface of the blocking dielectric layer.

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