Device and method for implementing data loading based on memory

Abstract

The present invention provides an implementation device based on memory data loading, which is located between a memory and a slave controller, and the slave controller uses a communication protocol to load data to the memory, and the device includes: a state control module, which is configured to enter different control states according to the communication protocol so that the slave controller loads data to the memory; a verification module, which is configured to verify the loaded data to obtain the verification result of the data loaded each time; and a loading error counting module, which is configured to count the number of loading information errors according to the verification result, and when the value of the loading error counting module reaches a second threshold, the state control module controls the slave controller to terminate the data loading to the memory, and after reconfiguring all the data that needs to be loaded, the state control module controls the slave controller to reload all the reconfigured data that needs to be loaded. The present invention can improve the accuracy of data loading.

Description

Technical Field

[0001] The present invention relates to the field of automation control technology, and in particular to an implementation device and method based on memory data loading. Background Art

[0002] Ethernet Control Automation Technology (EtherCAT) was originally proposed by Beckhoff Automation GmbH in Germany in 2003 as a real-time industrial Ethernet technology based on Ethernet technology. This technology not only has the characteristics of high speed and high data efficiency, but also has a flexible network topology structure, and encapsulates IP / UDP in the protocol, so that communication can be achieved without the IP protocol. Therefore, EtherCAT does not need to use a slave subnet, and the connected network database can be used as an EtherCAT slave. At the same time, this technology adopts a master-slave structure. The master station has bus control rights. The master station sends messages according to the control cycle. The data frame traverses all slave devices. Each slave device addresses the local message when the data frame passes, and writes data or reads data to the specified position in the message according to the command in the data frame. Until the data frame accesses the last slave in the entire bus.

[0003] The IP core (Intellectual property core) of the EtherCAT slave uses EEPROM (Electrically Erasable Programmable read only memory) to store the required device information, mainly including register configuration area, product identification area, hardware delay, mailbox configuration in boot state, standard mailbox communication SM configuration, etc. The data information in the EEPROM is loaded after the IP of the EtherCAT slave is powered on or reset, and the data information in the EEPROM can also be read according to the EEPROM address, so as to realize the configuration of the corresponding information.

[0004] However, in the process of EtherCAT slave loading data information in EEPROM, data loading errors often occur. Summary of the invention

[0005] To solve the above problems, the present invention provides a device and method for implementing memory-based data loading, which can improve the accuracy of data loading.

[0006] In a first aspect, the present invention provides a device for implementing data loading based on a memory, which is located between a memory and a slave controller, and the slave controller uses a communication protocol to load data to the memory, and the device includes:

[0007] a state control module, configured to enter different control states according to the communication protocol, so that the slave controller loads data to the memory;

[0008] A verification module is configured to verify the loaded data to obtain a verification result of the loaded data each time; and

[0009] A loading error counting module is configured to count the number of loading information errors according to the verification result, wherein when the value of the loading error counting module reaches a second threshold, the state control module controls the slave station controller to terminate the loading of data to the memory, and after reconfiguring all the data that needs to be loaded, the state control module controls the slave station controller to reload all the reconfigured data that needs to be loaded.

[0010] Optionally, when the value of the loading error counting module reaches a first threshold, the state control module controls the slave station controller to stop loading data into the memory, and after reconfiguring the loaded erroneous data, the state control module controls the slave station controller to reload the reconfigured data, wherein the loading error counting module counts in a cumulative manner, and the first threshold is less than the second threshold.

[0011] Optionally, the device also includes: a waiting counting module, configured to start counting autonomously when the slave station controller completes power-on or reset, wherein when the value of the waiting counting module reaches a third threshold, the state control module starts sending different control states to the memory according to the communication protocol.

[0012] Optionally, the different control states include: EEPROM_RST state, EEPROM_LOAD_WAIT state, EEPROM_START state, EEPROM_ADDR state, EEPROM_CMD state, EEPROM_ACK state, EEPROM_DATA state, EEPROM_STOP state and EEPROM_IDLE state.

[0013] Optionally, the device further comprises: a data counting module configured to count the number of times the data is loaded by the slave controller.

[0014] Optionally, the state control module is further configured to:

[0015] When the slave controller starts to power on or reset, it enters the EEPROM_RST state;

[0016] After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state, and the waiting counting module starts counting;

[0017] When the waiting counting module reaches a third threshold, the EEPROM_START state is entered, the device is controlled to send a start identifier of the communication protocol, and the waiting counting module stops counting;

[0018] Entering the EEPROM_ADDR state, controlling the device to send a memory address;

[0019] Entering the EEPROM_CMD state, controlling the device to send memory read and write commands;

[0020] Entering the EEPROM_ACK state, controlling the device to receive a memory protocol response signal sent by the memory;

[0021] Entering the EEPROM_DATA state, controlling the device to receive data at a corresponding address of the memory sent by the memory, and controlling the slave controller to start loading the data at the corresponding address of the memory, and the verification module starts to verify the loaded data;

[0022] When the value of the configuration data counting module reaches a fourth threshold, the EEPROM_STOP state is entered to control the device to send an end signal of the communication protocol, wherein the fourth threshold is determined by the number of all data that need to be loaded.

[0023] Optionally, the state control module is further configured to enter the EEPROM_IDLE state when all data that need to be loaded are loaded and the value of the loading error counting module does not reach a second threshold, and stop the slave station controller from loading data to the memory, so that the memory is in an idle state.

[0024] Optionally, the state control module is further configured to enter the EEPROM_RST state when the value of the loading error counting module reaches a second threshold, and the value of the loading error counting module is restored to an initial value.

[0025] Optionally, the device further includes: a clock frequency division module, configured to divide the system clock according to the state of the state control module, so as to flip the clock signal of the memory.

[0026] In a second aspect, the present invention provides an implementation method based on memory data loading, which is applied to the above-mentioned implementation device, and the slave station controller uses a communication protocol to load data to the memory, and the method includes:

[0027] When the slave controller starts to power on or reset, it enters the EEPROM_RST state;

[0028] After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state and starts counting using the waiting counting module;

[0029] When the waiting counting module reaches a third threshold, the EEPROM_START state is entered, a start identifier of the communication protocol is sent, and the counting of the waiting counting module is stopped;

[0030] Enter EEPROM_ADDR state and send memory address;

[0031] Enter EEPROM_CMD state and send memory read and write commands;

[0032] Entering the EEPROM_ACK state, receiving a memory protocol response signal sent by the memory;

[0033] Entering the EEPROM_DATA state, receiving data sent by the memory and corresponding to the address of the memory;

[0034] Controlling the slave controller to start loading data at corresponding addresses of the memory, and start verifying the loaded data to obtain verification results of the data loaded each time, and count the number of times the slave controller loads data;

[0035] Count the number of loading information errors;

[0036] When the number of data loaded by the slave controller reaches a fourth threshold, the slave controller enters the EEPROM_STOP state and sends an end signal of the communication protocol, wherein the fourth threshold is determined by the number of all data that need to be loaded;

[0037] When the number of loading information errors reaches a second threshold, controlling the slave controller to terminate data loading to the memory;

[0038] After reconfiguring all the data that need to be loaded, controlling the slave station controller to reload the reconfigured data that need to be loaded.

[0039] The embodiments of the present invention provide an implementation device and method based on memory data loading, wherein the implementation device can control the slave station controller to load data to the memory according to the corresponding communication protocol through the state control module, the verification module can judge the correctness of the data loaded by the slave station controller, and the loading error counting module can reload the loaded erroneous data according to the verification result of the verification module. When the number of erroneous loadings reaches a certain value, the loaded data is adjusted to ensure the correctness of the data loaded by the slave station controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic structural diagram of an implementation device of an embodiment of the present application;

[0041] Figure 2 A schematic structural diagram of the positional relationship between the implementation device of the embodiment of the present application, the slave station controller and the memory;

[0042] Figure 3 This is a timing diagram of the EtherCAT slave controller loading EEPROM data in an embodiment of the present application;

[0043] Figure 4 A schematic flow chart of the state control module of the embodiment of the present application entering different states;

[0044] Figure 5 A schematic flowchart of an implementation method of an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In a first aspect, the present invention provides a device for implementing memory-based data loading, located between the memory and the slave controller. Figure 1 , Figure 1A schematic structural diagram of an implementation device according to an embodiment of the present application is shown, wherein the slave controller uses a communication protocol to load data to the memory, and the device includes: a state control module, configured to enter different control states according to the communication protocol, so that the slave controller loads data to the memory; a verification module, configured to verify the loaded data to obtain a verification result of the data loaded each time; and a loading error counting module, configured to count the number of loading information errors according to the verification result. Wherein, when the value of the loading error counting module reaches a second threshold, the state control module controls the slave controller to terminate the loading of data to the memory, and after reconfiguring all the data that needs to be loaded, the state control module controls the slave controller to reload all the reconfigured data that needs to be loaded.

[0047] In this embodiment, see Figure 2 , Figure 2 A schematic structural diagram showing the positional relationship between an implementation device, the slave controller and the memory according to an embodiment of the present application is shown. The implementation device is embedded in the slave controller, and the slave controller transmits data and clock to the memory through the implementation device. Wherein, the data includes: EEPROM_DATA; the clock includes: EEPROM_CLK. The memory is EEPROM (Electrically Erasable Programmable read only memory); the slave controller is an EtherCAT (Ether Control Automation Technology) slave controller; the check module is a CRC (Cyclic Redundancy Check) module. The EtherCAT slave controller uses the IIC (Inter-Integrated Circuit) protocol to control the EEPROM. Wherein, the IIC protocol is a half-duplex protocol, and data is effectively transmitted during the low level period of the EEPROM_CLK signal.

[0048] For details, see Figure 3 , Figure 3The timing diagram of the EtherCAT slave controller loading EEPROM data according to an embodiment of the present application is shown. When EEPROM_CLK is at a high level, the falling edge of EEPROM_CLK is the start bit, and the rising edge of EEPROM_CLK is the stop bit. So far, when EEPROM_CLK is at a high level, EEPROM_CLK remains stable. Therefore, according to the above-mentioned conditions for valid data loading, it can be determined that data changes are allowed only during the period when EEPROM_CLK is at a low level; during the period of high level, data changes are not allowed, otherwise the start bit or the end bit will appear.

[0049] The state control module can control the entire EEPROM implementation process, that is, parse the read, write and load commands of the EEPROM, and can also control the operation of the CRC (Cyclic Redundancy Check) check module.

[0050] Furthermore, the implementation device can control the slave station controller to load data to the memory according to the corresponding communication protocol through the state control module, the verification module can judge the correctness of the data loaded by the slave station controller, and the loading error counting module can reload the erroneous data according to the verification result of the verification module. When the number of erroneous loadings reaches a certain value, the loaded data is adjusted to ensure the correctness of the data loaded by the slave station controller.

[0051] In an optional embodiment, when the value of the loading error counting module reaches a first threshold, the state control module controls the slave station controller to stop loading data into the memory, and after reconfiguring the loaded erroneous data, the state control module controls the slave station controller to reload the reconfigured data, wherein the loading error counting module counts in a cumulative manner, and the first threshold is less than the second threshold.

[0052] In this implementation, the first threshold is 1, and the second threshold is 2. The initial value of the loading error counting module is 0. When the value of the loading error counting module is 1, the data with loading error is reloaded, because the data loading error may be caused by a temporary problem in the data loading process. When the value of the loading error counting module is 2, it largely indicates that there is a problem with the loaded data, so the implementation device controls the slave station controller to stop loading the data and report an error. After reconfiguring the data, the data is reloaded, and when the data is reconfigured, the value of the loading error counting module is modified to 0.

[0053] In an optional embodiment, the device also includes: a waiting counting module, configured to start counting autonomously when the slave station controller completes power-on or reset, wherein when the value of the waiting counting module reaches a third threshold, the state control module starts sending different control states to the memory according to the communication protocol.

[0054] The setting of the waiting technology module can complete the power-on or reset of the slave station controller, leaving enough time for the memory to power on, so as to ensure that the memory can complete the loading of data under normal power-on conditions, thereby further ensuring the correctness of the data loaded by the slave station controller. In this embodiment, the third threshold is not further limited.

[0055] In an optional embodiment, the different control states include: EEPROM_RST state, EEPROM_LOAD_WAIT state, EEPROM_START state, EEPROM_ADDR state, EEPROM_CMD state, EEPROM_ACK state, EEPROM_DATA state, EEPROM_STOP state and EEPROM_IDLE state.

[0056] In an optional embodiment, the device further includes: a configuration data counting module configured to count the number of times the data is loaded by the slave station controller.

[0057] In an alternative embodiment, see Figure 4 , Figure 4 A schematic flow chart of a state control module entering different states according to an embodiment of the present application is shown. The state control module is further configured to:

[0058] When the slave controller starts to power on or reset, it enters the EEPROM_RST state;

[0059] After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state, and the waiting counting module starts counting;

[0060] When the waiting counting module reaches a third threshold, the EEPROM_START state is entered, the device is controlled to send a start identifier of the communication protocol, and the waiting counting module stops counting;

[0061] Entering the EEPROM_ADDR state, controlling the device to send a memory address;

[0062] Entering the EEPROM_CMD state, controlling the device to send memory read and write commands;

[0063] Enter the EEPROM_ACK state, control the device to receive the memory protocol response (ACK, Acknowledgement) signal sent by the memory; in this embodiment, the response signal is a signal of a confirmation character, a transmission control character sent by the EEPROM to the EtherCAT slave controller. Specifically, each time the EtherCAT slave controller sends a byte of data to the EEPROM, the EtherCAT slave controller always needs to wait for the EEPROM to give an acknowledgement signal to confirm whether the EEPROM has successfully received the data. The clock required for the EEPROM to respond to the EtherCAT slave controller is also provided by the system host. The response appears in the clock cycle immediately following each time the host completes 8 words, that is, data bits, transmission, wherein the low level 0, that is, ACK = 1'b0, indicates an acknowledgement; the high level 1, that is, ACK = 1'b1, indicates a non-acknowledgement. In the case where the device receives a non-acknowledgement, the state control module enters the EEPROM_START state again; in the case where the device receives an acknowledgement, the state control module enters the EEPROM_DATA state. When a response is required, the data sender sets the EEPROM_DATA bus to a 3-state input. Since there is a pull-up resistor on the IIC bus, the bus defaults to a high level at this time. If the data receiver receives the data correctly, the data receiver pulls the EEPROM_DATA bus low to indicate a correct response.

[0064] Entering the EEPROM_DATA state, controlling the device to receive data at a corresponding address of the memory sent by the memory, and controlling the slave controller to start loading the data at the corresponding address of the memory, and the verification module starts to verify the loaded data;

[0065] When the value of the configuration data counting module reaches a fourth threshold, the EEPROM_STOP state is entered to control the device to send an end signal of the communication protocol, wherein the fourth threshold is determined by the number of all data that need to be loaded.

[0066] In this embodiment, the register configuration area of ​​the slave controller has eight words in total, including: PDI control, PDI configuration, SYNC signal pulse width, extended PDI configuration, site alias, reserved 1, reserved 2 and checksum, as shown in Table 1.

[0067] Table 1

[0068] Word Address Parameter name describe 0 PDI Control PDI control register initial value 1 PDI Configuration PDI configuration register initial value 2 SYNC signal pulse width SYNC signal pulse width register initial value 3 Extended PDI Configuration Extended PDI configuration register initial value 4 Site Alias Site Alias ​​Configuration Initial Register 5 Reserve 1 reserve 6 Reserve 2 reserve 7 Checksum Word 0 to 6 checksum

[0069] Therefore, the fourth threshold is 8, that is, when the value of the configuration data counting module reaches 8, it indicates that the loading is completed.

[0070] In an optional embodiment, the state control module is further configured to enter the EEPROM_IDLE state when all data that need to be loaded are loaded and the value of the loading error count module does not reach a second threshold, and stop the slave station controller from loading data into the memory, so that the memory is in an idle state.

[0071] In an optional embodiment, the state control module is further configured to enter the EEPROM_RST state when the value of the loading error counting module reaches a second threshold, and the value of the loading error counting module is restored to an initial value.

[0072] In an optional embodiment, the device further includes: a clock frequency division module, configured to divide the system clock according to the state of the state control module, so as to flip the clock signal of the memory.

[0073] In this embodiment, since the system clock is 25M and the EEPROM protocol speed is 150K, the division coefficient of the clock division module is 82.

[0074] Second, see Figure 5 , Figure 5 The present invention provides an implementation method based on memory data loading, which is applied to the above-mentioned implementation device, and the slave controller uses a communication protocol to load data to the memory, and the method includes:

[0075] Step S101: When the slave controller starts to power on or reset, it enters the EEPROM_RST state.

[0076] Step S102: After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state and starts counting using a waiting counting module.

[0077] Step S103: When the waiting counting module reaches the third threshold, the EEPROM_START state is entered, the start identifier of the communication protocol is sent, and the counting of the waiting counting module is stopped.

[0078] Step S104: Enter the EEPROM_ADDR state and send the memory address.

[0079] Step S105: Enter the EEPROM_CMD state and send a memory read and write command.

[0080] Step S106: Entering the EEPROM_ACK state, receiving a memory protocol response signal sent by the memory.

[0081] Step S107: Entering the EEPROM_DATA state, receiving data of the corresponding address of the memory sent by the memory.

[0082] Step S108: Control the slave controller to start loading data at the corresponding address of the memory, and start verifying the loaded data to obtain verification results of the loaded data each time, and count the number of times the slave controller loads data.

[0083] Step S109: Count the number of times the loading information is wrong.

[0084] Step S110: When the number of data loaded by the slave controller reaches a fourth threshold, the slave controller enters the EEPROM_STOP state and sends an end signal of the communication protocol, wherein the fourth threshold is determined by the number of all data that need to be loaded.

[0085] Wherein, when the number of loading information errors reaches a second threshold, the slave station controller is controlled to terminate the loading of data to the memory; after reconfiguring all the data that need to be loaded, the slave station controller is controlled to reload the reconfigured data that need to be loaded.

[0086] The implementation method can control the slave controller to load data to the memory according to the corresponding communication protocol by setting different control states, and judge the correctness of the data loaded by the slave controller. According to the verification result, the erroneous data is reloaded. When the number of erroneous loadings reaches a certain value, the loaded data is adjusted to ensure the correctness of the data loaded by the slave controller. At the same time, a third threshold is set to ensure that the memory can complete the loading of data when the power is on normally, thereby further ensuring the correctness of the data loaded by the slave controller.

[0087] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A device for implementing data loading based on a memory, located between a memory and a slave controller, wherein the slave controller uses a communication protocol to load data to the memory, characterized in that: The device comprises: a state control module, configured to enter different control states according to the communication protocol, so that the slave controller loads data to the memory; A verification module is configured to verify the loaded data to obtain a verification result of the loaded data each time; and A loading error counting module, configured to count the number of loading information errors according to the verification result; Wherein, when the value of the loading error counting module reaches a second threshold, the state control module controls the slave controller to terminate the loading of data to the memory and reload the data with loading errors, and after reconfiguring all the data to be loaded, the state control module controls the slave controller to reload all the reconfigured data to be loaded; The device further comprises: a configuration data counting module configured to count the number of times the data is loaded by the slave controller, wherein the different control states include an EEPROM_STOP state; The state control module is configured to enter the EEPROM_STOP state and control the device to send an end signal of the communication protocol when the value of the configuration data counting module reaches a fourth threshold, and the fourth threshold is determined by the number of all data that need to be loaded.

2. The implementation device based on memory data loading according to claim 1, characterized in that: When the value of the loading error counting module reaches a first threshold, the state control module controls the slave station controller to stop loading data into the memory, and after reconfiguring the loaded erroneous data, the state control module controls the slave station controller to reload the reconfigured data, wherein the loading error counting module counts in a cumulative manner, and the first threshold is less than the second threshold.

3. The implementation device based on memory data loading according to claim 1, characterized in that: The device also includes: a waiting counting module, which is configured to start counting autonomously when the slave station controller completes power-on or reset, wherein when the value of the waiting counting module reaches a third threshold, the state control module starts to send different control states to the memory according to the communication protocol.

4. The implementation device based on memory data loading according to claim 3, characterized in that: The different control states also include: EEPROM_RST state, EEPROM_LOAD_WAIT state, EEPROM_START state, EEPROM_ADDR state, EEPROM_CMD state, EEPROM_ACK state, EEPROM_DATA state and EEPROM_IDLE state.

5. The device for implementing memory-based data loading according to claim 4, characterized in that: The state control module is configured as follows: When the slave controller starts to power on or reset, it enters the EEPROM_RST state; After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state, and the waiting counting module starts counting; When the waiting counting module reaches a third threshold, the EEPROM_START state is entered, the device is controlled to send a start identifier of the communication protocol, and the waiting counting module stops counting; Entering the EEPROM_ADDR state, controlling the device to send a memory address; Entering the EEPROM_CMD state, controlling the device to send memory read and write commands; Entering the EEPROM_ACK state, controlling the device to receive a memory protocol response signal sent by the memory; Entering the EEPROM_DATA state, controlling the device to receive data of the corresponding address of the memory sent by the memory, and controlling the slave station controller to start loading the data of the corresponding address of the memory, and the verification module starts to verify the loaded data.

6. The implementation device based on memory data loading according to claim 4, characterized in that: The state control module is configured to enter the EEPROM_IDLE state when all data that need to be loaded are loaded and the value of the loading error counting module does not reach the second threshold, and stop the slave station controller from loading data to the memory, so that the memory is in an idle state.

7. The device for implementing memory-based data loading according to claim 4, characterized in that: The state control module is configured to enter the EEPROM_RST state when the value of the loading error counting module reaches a second threshold, and the value of the loading error counting module is restored to an initial value.

8. The device for implementing memory-based data loading according to claim 1, characterized in that: The device further includes: a clock frequency division module configured to divide the frequency of the system clock according to the state of the state control module, so as to flip the clock signal of the memory.

9. A method for implementing data loading based on memory, applied to the implementation device according to any one of claims 1 to 8, wherein the slave controller uses a communication protocol to load data to the memory, characterized in that: The method comprises: When the slave controller starts to power on or reset, it enters the EEPROM_RST state; After the slave controller is powered on or reset, it enters the EEPROM_LOAD_WAIT state and starts counting using the waiting counting module; When the waiting counting module reaches a third threshold, the EEPROM_START state is entered, a start identifier of the communication protocol is sent, and the counting of the waiting counting module is stopped; Enter EEPROM_ADDR state and send memory address; Enter EEPROM_CMD state and send memory read and write commands; Entering the EEPROM_ACK state, receiving a memory protocol response signal sent by the memory; Entering the EEPROM_DATA state, receiving data sent by the memory and corresponding to the address of the memory; Controlling the slave controller to start loading data at corresponding addresses of the memory, and start verifying the loaded data to obtain verification results of the data loaded each time, and count the number of times the slave controller loads data; Count the number of loading information errors; When the number of data loaded by the slave controller reaches a fourth threshold, the slave controller enters the EEPROM_STOP state and sends an end signal of the communication protocol, wherein the fourth threshold is determined by the number of all data that need to be loaded; When the number of loading information errors reaches a second threshold, controlling the slave controller to terminate data loading to the memory; After reconfiguring all the data that need to be loaded, controlling the slave station controller to reload the reconfigured data that need to be loaded.

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