A New High-Speed ​​DDR Transmitting Circuit

Abstract

The invention provides a novel high-speed DDR sending circuit, comprising two PMOS tubes PM1 and PM2 and two NMOS tubes NM1 and NM2; the source of PM1 is connected to a high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, and the other end of the resistor is connected to an output pad; the gate of PM1 is connected to a control line netp, netp is connected to a data input DIN through an inverter INV1, and a capacitor C is arranged between INV1 and netp; the working voltage of INV1 is a low voltage VDD, and the capacitor C and netp provide a voltage VDDL for the gate of PM1 to protect PM1; the source of NM1 is grounded, the drain is connected to the source of NM2, and the drain of NM2 is connected to the resistor; the gate of NM1 is connected to the data input DIN through the inverter INV2; a low-voltage device with a relatively fast speed is used as a main driving circuit and a front driving circuit, and a voltage is generated by using a clock signal and a switch capacitor without significantly increasing power consumption to ensure the safety of the low-voltage device, thereby effectively improving the working speed of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a novel high-speed DDR sending circuit. Background Art

[0002] The DDR output interface driving circuit usually uses a CMOS tube as the output driving resistor, or a CMOS tube plus a resistor to form an output driving resistor. Limited by the voltage regulations in the electrical specifications, the existing DDR4, DDR5 and other interface sending circuits usually still use slower high-voltage devices as the main driving circuit and the front driving circuit. For example, the DDR4 power supply voltage is specified to be 1.2V, and the main driving unit and the front driving circuit must use a high-voltage CMOS tube (IO device) that can withstand more than 1.2V. With the improvement of the process, the speed of its low-voltage core device (core device) is getting faster and faster, but the tolerance voltage is getting lower and lower, making it difficult to further increase the working speed. Summary of the invention

[0003] In view of the above technical problems, the present invention provides a novel high-speed DDR sending circuit.

[0004] A novel high-speed DDR transmission circuit comprises two PMOS tubes PM1 and PM2 and two NMOS tubes NM1 and NM2 connected in parallel with the PMOS tubes; wherein the source of PM1 is connected to a high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, and the other end of the resistor is connected to an output pad; the gate of PM1 is connected to a control line netp, and netp is connected to a data input DIN through an inverter INV1, and a capacitor C is arranged between INV1 and netp; the working voltage of INV1 is a low voltage VDD, and the capacitor C and netp can provide a voltage VDDL (VDDL=VDDQ-VDD) for the gate of PM1 to protect PM1;

[0005] The source of NM1 is grounded, and the drain is connected to the source of NM2. The drain of NM2 is also connected to the resistor. The gate of NM1 is connected to the data input DIN through the inverter INV2.

[0006] Preferably, PM2 and NM2 are used as static switches for adjusting impedance and are normally open in the working state.

[0007] Preferably, netp includes two nodes net1 and net2 arranged in parallel; one end of net1 and net2 are respectively connected to capacitor C1 and capacitor C2, and the other end is respectively connected to the output pad through CLKN, and a grounded voltage-stabilizing capacitor C3 is connected between the two CLKNs and the output pad; the capacitor C1 and net1 are connected to a high voltage VDDQ through CLK, and the other end of the capacitor C1 is respectively connected to a low voltage VDD through CLK and to ground through CLKN; the capacitor C2 and net2 are grounded through CLK, and the other end of the capacitor C2 is respectively connected to a low voltage VDD through CLK and to a high voltage VDDQ through CLKN.

[0008] Preferably, the bypass of capacitor C is provided with two high-voltage device transmission gates arranged in parallel, and the high-voltage signal EL0H controls one of the transmission gates to transmit the voltage VDDL to netp, and the high-voltage signal EL1H controls the other transmission gate to transmit the voltage VDDQ to netp, so that INV1 can drive netp through capacitor C to quickly flip between VDDQ and VDDL.

[0009] Preferably, the high-voltage signal EL0H comes from a signal obtained by performing an XOR operation on DIN and DIN_E, performing an XOR operation on DIN_EB, performing an XOR operation on DIN_EB, and performing an XOR operation on OEB, and then performing level conversion to a high signal.

[0010] Preferably, the high-voltage signal EL1H comes from the XOR of DIN and DIN_E and the AND of DIN_E, and then is converted into a high signal through level conversion.

[0011] The beneficial effects of the present invention are: using fast low-voltage devices as the main drive circuit and the front drive circuit, and using clock signals and switching capacitors to generate a voltage to ensure the safety of the low-voltage devices without significantly increasing power consumption, thereby effectively improving the operating speed of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will be further described below in conjunction with the accompanying drawings.

[0013] Figure 1 is an overall circuit diagram of an embodiment of the present invention;

[0014] Figure 2 is a circuit diagram of netp in an embodiment of the present invention;

[0015] Figure 3 FIG. 4 is a bypass circuit diagram of capacitor C in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0017] The present invention provides a novel high-speed DDR transmission circuit, the overall circuit structure of which is as follows: Figure 1 As shown, it mainly includes two PMOS tubes PM1 and PM2 and two NMOS tubes NM1 and NM2 connected in parallel with the PMOS tube, among which PM2 and NM2 are static switches for adjusting impedance, which are normally open in the working state and no longer affect the working speed; PM1 and NM1 are added low-voltage devices, which switch at high speed under data control.

[0018] The source of PM1 is connected to the high voltage VDDQ, and the drain is connected to the source of PM2. The drain of PM2 is connected to a resistor, and the other end of the resistor is connected to the output pad. The gate of PM1 is connected to the control line netp, and netp is connected to the data input DIN through the inverter INV1. A capacitor C is provided between INV1 and netp. The operating voltage of INV1 is the low voltage VDD. The capacitor C and netp can provide a voltage VDDL (VDDL = VDDQ-VDD) for the gate of PM1 to protect PM1. For example, VDDQ is 1.2V in DDR4, and under the 14nm process, the withstand voltage difference (Vgs) from the gate to the source of PM1 is 0.8V, so the pre-stage drive circuit needs to generate a signal with a signal amplitude of 1.2V to 0.4V (1.2V-0.8V) for the gate of PM1.

[0019] When the INV1 output at the left end of capacitor C is VDD, the initial voltage of netp at the right end is VDDQ. When the next data INV1 output is 0, under the constraint that the capacitance charge of capacitor C remains unchanged, the voltage of netp suddenly changes to VDDQ-VDD. On the contrary, when INV1 output is 0, the initial voltage of netp is VDDQ-VDD, and when the next data INV1 output is VDD, the voltage of netp suddenly changes to VDDQ.

[0020] The source of NM1 is grounded, and the drain is connected to the source of NM2, and the drain of NM2 is also connected to the resistor. The gate of NM1 is connected to the data input DIN through the inverter INV2.

[0021] like Figure 2As shown, netp includes two nodes net1 and net2 arranged in parallel. The left ends of net1 and net2 are connected to capacitors C1 and C2 respectively, and the right ends are connected to the output pads through CLKN respectively, and a grounded voltage-stabilizing capacitor C3 is connected between the two CLKNs and the output pads. The high voltage VDDQ is connected between capacitor C1 and net1 through CLK, and the left end of capacitor C1 is connected to the low voltage VDD through CLK and grounded through CLKN. The capacitor C2 and net2 are grounded through CLK, and the left end of capacitor C2 is connected to the low voltage VDD through CLK and the high voltage VDDQ through CLKN. Among them, CLKN is the inverted signal of CLK. When CLK or CLKN is at a high level, the switch is turned on, otherwise the switch is turned off.

[0022] When CLK is high, CLKN is low. At this time, the right end of capacitor C1 is connected to VDDQ, and the left end is connected to VDD. The charge of C1 is (VDDQ-VDD)*C1. When CLK becomes low, CLKN is high. At this time, the left end of capacitor C1 is grounded (0V). In the absence of power supply charging, the charge of C1 remains (VDDQ-VDD)*C1, that is, the voltage of the right end net1 becomes VDDQ-VDD. Under the charge sharing effect of voltage stabilizing capacitor C3 on capacitor C1, the output VDDL voltage can be gradually reduced from VDDQ and stabilized at VDDQ-VDD after several CLK cycles.

[0023] Similarly, when CLK is high, CLKN is low, the right end of capacitor C2 is grounded, the left end is connected to VDD, and the charge of C2 is VDD*C2; when CLK becomes low, CLKN is high, the left end of capacitor C2 is connected to VDDQ, and C2 still maintains VDD*C2 without power charging, that is, the voltage of the right end net2 becomes VDDQ-VDD. Under the charge sharing effect of voltage stabilizing capacitor C3 on capacitor C2, the output VDDL voltage can gradually increase from 0V and stabilize at VDDQ-VDD after several CLK cycles.

[0024] Therefore, the parallel connection of the C1 branch and the C2 branch can make VDDL reach 0.5*VDDQ in the first clock cycle, which can prevent VDDL from generating excessively high voltage and greatly improve its stable speed.

[0025] like Figure 3 As shown, the bypass of capacitor C is provided with two high-voltage device transmission gates arranged in parallel, and the high-voltage signal EL0H controls one of the transmission gates to transmit the voltage VDDL to netp, and the high-voltage signal EL1H controls the other transmission gate to transmit the voltage VDDQ to netp, so that INV1 can drive netp through capacitor C to quickly switch between VDDQ and VDDL.

[0026] The high-voltage signal EL1H comes from the XOR of DIN and DIN_E (the previous data of DIN) and the AND of DIN_E, and then the signal after the level conversion to high. That is: when two consecutive data are 1, EL1H becomes high level with the first 1, and then opens the transmission gate of the high-voltage device it controls, and the netp voltage becomes VDDQ. If the third data (DIN_L) does not continue to remain 1 (that is, DIN_E, DIN, DIN_L are 110), EL1H ends with the end of the first 1, and then closes its corresponding transmission gate.

[0027] Similarly, the high-voltage signal EL0H comes from the XOR of DIN and DIN_E, the AND of DIN_EB (the inverted signal of DIN_E), and the OR of OEB (the inverted signal of OE), and then the signal is converted to a high level. That is, when two consecutive data are 0 or OE is 0, EL0H becomes a high level with the first 0, and then opens the transmission gate of the high-voltage device it controls, and the netp voltage becomes VDDL. If the third data (EIN_L) does not continue to remain 0 (that is, DIN_E, DIN, DIN_L are 001), EL0H ends with the end of the first 0, and then closes its corresponding transmission gate.

[0028] The level converter used by EL1H and EL0H is usually slow, so the above logic can be used to charge the right end of capacitor C earlier than INV1. When the data sent by INV1 is 110, the right end of capacitor C starts to charge to VDDQ in the second half of the first 1, and ends charging in the first half of the second 1. When it is 001, it is charged to VDDL in the same way. When the data sent is 0101, INV1 drives netp to quickly flip between VDDQ and VDDL through capacitor C. The combination of various circuits can realize the functions of fast data flipping and timely charging to prevent level drift.

[0029] The present invention adopts low-voltage devices with relatively high speed as the main driving circuit and the front driving circuit, and uses clock signals and switching capacitors to generate a voltage to ensure the safety of the low-voltage devices without significantly increasing power consumption, thereby effectively improving the working speed of the circuit.

[0030] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

Claims

1. A novel high-speed DDR transmission circuit, characterized in that: It includes two PMOS tubes PM1 and PM2 and two NMOS tubes NM1 and NM2 connected in parallel with the PMOS tubes; the source of PM1 is connected to the high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, and the other end of the resistor is connected to the output pad; the gate of PM1 is connected to the control line netp, and netp is connected to the data input DIN through the inverter INV1, and a capacitor C is provided between INV1 and netp; the working voltage of INV1 is the low voltage VDD, and the capacitor C and netp can provide a voltage VDDL for the gate of PM1, and VDDL=VD DQ-VDD, to protect PM1; the source of NM1 is grounded, the drain is connected to the source of NM2, and the drain of NM2 is also connected to the resistor; the gate of NM1 is connected to the data input DIN through the inverter INV2; PM2 and NM2 are static switches for adjusting impedance, and are normally open in the working state; netp includes two nodes net1 and net2 arranged in parallel; one end of net1 and net2 are connected to the capacitor C1 and the capacitor C2 respectively, and the other end is connected to the output pad through CLKN respectively, and a grounded voltage stabilizing capacitor C3 is connected between the two CLKN and the output pad; A high voltage VDDQ is connected between capacitor C1 and net1 through CLK, and the other end of capacitor C1 is connected to a low voltage VDD through CLK and is grounded through CLKN; capacitor C2 is grounded through CLK and the other end of capacitor C2 is connected to a low voltage VDD through CLK and is connected to a high voltage VDDQ through CLKN; the bypass of capacitor C is provided with two high-voltage device transmission gates arranged in parallel, and a high-voltage signal EL0H controls one of the transmission gates to transmit a voltage VDDL to netp, and a high-voltage signal EL1H controls the other transmission gate to transmit a voltage VDDQ to netp, so that INV1 can drive netp to quickly flip between VDDQ and VDDL through capacitor C; the high-voltage signal EL0H comes from a signal after DIN is XORed with DIN_E and ANDed with DIN_EB, and then ORed with OEB, and then converted to a high level; the high-voltage signal EL1H comes from a signal after DIN is XORed with DIN_E and ANDed with DIN_E, and then converted to a high level.

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