Chip packaging module

Abstract

The present disclosure relates to a chip packaging module. The chip packaging module includes a packaging substrate, a chip and a conductive connection assembly. The chip is arranged on the packaging substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip includes a flip chip pad group, a wire bonding pad group and a signal pad group. The flip chip pad group is located in the first area, the wire bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the packaging substrate. One of the flip chip pad group and the wire bonding pad group is electrically and physically connected to the conductive connection assembly, while the other is not physically connected to the conductive connection assembly.

Description

Technical Field

[0001] The present disclosure relates to a chip packaging module, and more particularly to a chip packaging module that can select a flip-chip packaging technology and a wire-bonding packaging technology according to actual needs. Background Art

[0002] Currently, wire-bonding package technology and flip-chip package are widely used to package integrated circuit chips (IC chips) to form electronic component packaging structures.

[0003] The cost of wire bonding packaging technology is low, but the electronic component packaging structure packaged by wire bonding packaging technology has a large size. In addition, when transmitting signals, the spacing between multiple welding wires is too dense, which is more likely to cause crosstalk and increase noise.

[0004] In comparison, although the cost of using flip chip packaging technology is higher, the volume of the electronic component packaging structure is smaller. In addition, the transmission distance between the integrated circuit chip and the wire substrate used for packaging is smaller, the noise is less, and the signal transmission quality is better. Therefore, higher-end products usually use flip chip packaging technology, while lower-end products usually use wire bonding packaging technology.

[0005] The same specification of integrated circuit chips may be used in high-end products and mid-to-low-end products. However, for the application of flip chip packaging technology or the application of lead bonding packaging technology, the configuration of multiple pads of the integrated circuit chip is different. Further, among the multiple pads of the integrated circuit chip used to cooperate with the flip chip packaging technology, multiple power pads and multiple ground pads are usually distributed in the central area of ​​the integrated circuit chip. In comparison, among the multiple pads of the integrated circuit chip used to cooperate with the flip chip packaging technology, multiple power pads and multiple ground pads are usually distributed in the central area of ​​the integrated circuit chip.

[0006] That is to say, in the prior art, the pad configuration of the integrated circuit chip used for the flip chip packaging technology is not compatible with the wire bonding packaging technology, and vice versa, which will limit the flexibility of the integrated circuit chip in the application end. Summary of the invention

[0007] The technical problem to be solved by the present disclosure is to provide a chip packaging module to address the deficiencies of the prior art, which includes a chip that can be selected using a flip-chip packaging technology or a wire-bonding packaging technology according to actual needs.

[0008] In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present disclosure is to provide a chip packaging module, which includes a packaging substrate, a chip and a conductive connection assembly. The chip is arranged on the packaging substrate. The chip has a first surface and a second surface opposite to the first surface. The first surface is divided into a first area, a second area and a third area. The second area is located between the first area and the third area. The chip includes a flip chip pad group, a lead bonding pad group and a signal pad group. The flip chip pad group is located in the first area, the lead bonding pad group is located in the third area, and the signal pad group is located in the second area. The conductive connection assembly is electrically connected between the chip and the packaging substrate. One of the flip chip pad group and the lead bonding pad group is electrically and physically connected to the conductive connection assembly, while the other is not physically connected to the conductive connection assembly.

[0009] The beneficial effect of the technical solution of the present disclosure is at least that the chip packaging module provided by the present disclosure can, through the technical solutions of "the chip includes a flip chip pad group, a lead bonding pad group and a signal pad group" and "one of the flip chip pad group and the lead bonding pad group is electrically and physically connected to the conductive connection assembly, and the other is not physically connected to the conductive connection assembly", enable the chip packaging module to choose to use the flip chip packaging technology or the lead bonding packaging technology according to the field of its application, which can further increase the flexibility of the chip at the application end.

[0010] In order to further understand the features and technical contents of the present disclosure, please refer to the following specific implementation methods and drawings of the present disclosure. However, the drawings provided are only for reference and illustration and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagram of a top view of a chip according to an embodiment of the present disclosure.

[0012] Figure 2 for Figure 1 Schematic diagram of a partial enlargement of the chip in area II.

[0013] Figure 3 for Figure 1 Schematic diagram of a partial side view of a chip.

[0014] Figure 4It is a partially enlarged schematic diagram of a chip according to another embodiment of the present disclosure.

[0015] Figure 5 FIG. 4 is a partial side view of a chip packaging module according to a first embodiment of the present disclosure.

[0016] Figure 6 FIG. 4 is a partial side view of a chip packaging module according to a second embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following is an explanation of the implementation of the "chip packaging module" of the present disclosure through specific embodiments. Those skilled in the art can understand the advantages and effects of the present disclosure from the contents disclosed in this specification. The present disclosure can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present disclosure. In addition, the drawings of the present disclosure are only simple schematic illustrations and are not depicted according to actual dimensions. This is hereby stated in advance. The following embodiments will further explain the relevant technical contents of the present disclosure in detail, but the disclosed contents are not intended to limit the scope of protection of the present disclosure.

[0018] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0019] See also Figures 1 to 3 . Figure 1 Schematic diagram of a top view of a chip according to an embodiment of the present disclosure. Figure 2 for Figure 1 Schematic diagram of a partial enlargement of the chip in area II. Figure 3 for Figure 1 Schematic diagram of a partial side view of a chip.

[0020] like Figure 1 and Figure 3 As shown, the chip 1 of the embodiment of the present disclosure has a first surface 1a and a second surface 1b opposite to the first surface 1a. Figure 1 The first surface 1 a of the chip 1 can be divided into a first area A1 , a second area A2 , and a third area A3 from the center to the edge (in the radial direction).

[0021] like Figure 1As shown, the first area A1 is located in the central area of ​​the first surface 1a, the second area A2 surrounds the first area A1, and the third area A3 surrounds the second area A2. That is, the second area A2 is located between the first area A1 and the third area A3.

[0022] Reference Figure 2 The chip 1 further includes a flip chip pad group 10, a signal pad group 11 and a wire bonding pad group 12. The flip chip pad group 10 is located in the first area A1 and includes a plurality of pads. Further, the flip chip pad group 10 includes a plurality of flip chip power pads P1 and a plurality of flip chip ground pads G1 arranged in a plurality of groups.

[0023] Furthermore, a plurality of flip chip power pads P1 are arranged in at least one row along the first direction D1 ( Figure 2 Two rows are shown as an example), and a plurality of flip chip ground pads G1 are arranged in another row along the first direction D1. In the embodiment, a plurality of rows of flip chip power pads P1 and a plurality of rows of flip chip ground pads G1 are alternately arranged in the entire first area A1.

[0024] In this embodiment, a row of flip chip ground pads G1 is provided between every two rows of flip chip power pads P1. That is, in the second direction D2, a flip chip ground pad G1 is provided between any two flip chip power pads P1. It should be noted that Figure 2 The flip chip pad group 10 shown in the figure is only used as an example and is not intended to limit the present disclosure. The number and arrangement of the plurality of flip chip power pads P1 and the plurality of flip chip ground pads G1 can be adjusted according to actual needs.

[0025] Please refer to Figure 4 , showing a partially enlarged schematic diagram of a chip of another embodiment of the present disclosure. In the flip chip pad group 10 of this embodiment, the arrangement of the plurality of flip chip power pads P1 and the plurality of flip chip ground pads G1 is similar to Figure 2 The embodiments shown are different. Specifically, Figure 4 As shown, in the flip chip pad group 10, two rows of flip chip power pads P1 are adjacent to each other. In another embodiment, in the flip chip pad group 10, two rows of flip chip ground pads G1 are adjacent to each other.

[0026] Therefore, as long as the plurality of flip chip power pads P1 and the plurality of flip chip ground pads G1 are compatible with the flip chip packaging technology, the present disclosure does not limit the arrangement of the plurality of flip chip power pads P1 and the plurality of flip chip ground pads G1.

[0027] Please refer to Figure 2The signal pad group 11 is disposed in the second area A2 and includes a plurality of signal pads S. The plurality of signal pads S are arranged around the first area A1. Figure 2 In the illustrated embodiment, the plurality of signal pads S are arranged in three rows on one side of the first area A1 , but this is not intended to limit the present disclosure. In other embodiments, the number and arrangement of the signal pads S may also be adjusted according to the function and size of the chip 1 .

[0028] For example, multiple signal pads S can be designated as different signal connection terminals, such as: access voltage terminal (VCC), working voltage terminal (VDD) or common ground voltage (VSS), power supply, clock signal terminal (clock), address signal terminal (address signals), etc.

[0029] It is worth noting that the configuration of the plurality of signal pads S in the signal pad group 11 needs to be compatible with the flip chip packaging technology and the wire bonding packaging technology. Generally speaking, in the flip chip packaging technology, the spacing between two adjacent pads can be narrower, while in the wire bonding packaging technology, the spacing between two adjacent pads needs to be wider. Accordingly, in order to make the configuration of the plurality of signal pads S compatible with the flip chip packaging technology and the wire bonding packaging technology, the spacing d2 between two adjacent signal pads S in the same column can be mainly based on the requirements of the wire bonding packaging technology.

[0030] Therefore, the spacing d2 between two adjacent signal pads S in the same column can be greater than the spacing d1 between any two adjacent flip chip ground pads G1 (or flip chip power pads P1) in the same column. The aforementioned spacing can be defined as the shortest distance between the geometric center of one pad (such as the signal pad S) and the geometric center of the adjacent pad (such as the other signal pad S). In addition, in the second area A2, the row spacing d2 between two adjacent rows can also be greater than the row spacing L1 between two adjacent rows in the first area A1.

[0031] Please continue to refer to Figure 2 The wire bonding pad group 12 includes a plurality of wire bonding power pads P2 and a plurality of wire bonding ground pads G2, wherein the plurality of wire bonding ground pads G2 are arranged in a first row along one side edge of the chip 1. In addition, the plurality of wire bonding power pads P2 are arranged in a second row along the side edge, wherein the second row is located inside the first row, that is, farther from the side edge of the chip 1.

[0032] In another embodiment, the positions of the first row and the second row may also be swapped. That is, the wire bonding ground pad G2 is located farther from the side edge of the chip 1 , while the wire bonding power pad P2 is located closer to the side edge of the chip 1 .

[0033] It should be noted that Figure 2 Only a partial area of ​​the chip 1 is shown for illustration. In fact, a plurality of wire-bonded ground pads G2 and a plurality of wire-bonded power pads P2 may be arranged along the entire edge of the chip 1 and surround the second area A2.

[0034] In this embodiment, two adjacent wire bonding power pads P2 and wire bonding ground pads G2 may be staggered. Figure 2 As shown, the line connecting the geometric center of one of the wire bonding power pads P2 and the geometric center of the wire bonding ground pad G2 closest thereto is not parallel to the second direction D2.

[0035] The spacing d3 between two adjacent wire bonding ground pads G2 may be the same or substantially the same as the spacing between two adjacent wire bonding power pads P2. It is worth noting that the configuration of the wire bonding pad group 12 may meet the requirements of the wire bonding packaging technology, so the spacing d3 between two adjacent wire bonding ground pads G2 may be greater than the spacing d1 between two adjacent flip chip ground pads G1.

[0036] In addition, in the third area A3, the line distance L3 between two adjacent rows (the first row and the second row) may also be greater than the line distance L1 between two adjacent rows in the first area A1.

[0037] Based on the above, the chip 1 provided in the embodiment of the present disclosure can be applied to flip chip packaging technology and wire bonding packaging technology. Figure 5 , Figure 5 The schematic diagram of a partial side view of a chip packaging module M1 formed after packaging a chip 1 using a flip chip packaging technology. The chip packaging module M1 includes a chip 1, a packaging substrate 2, a conductive connection assembly 3, and a packaging layer 4. The packaging substrate 2 includes a support surface 2a and a bottom surface 2b opposite to the support surface 2a.

[0038] The package substrate 2 may be a circuit substrate, a ceramic substrate, a metal substrate or a composite substrate. In the present embodiment, the package substrate 2 is a circuit substrate, a plurality of circuits (not shown) are pre-configured in the package substrate 2, a plurality of pads 20G, 20P, 20S are provided on the support surface 2a, and a plurality of solder balls 21 are provided on the bottom surface 2b. Specifically, the plurality of pads 20G, 20P, 20S and the plurality of solder balls 21 may be electrically connected through the plurality of circuits configured in the package substrate 2.

[0039] The plurality of pads 20G, 20P, 20S may include a plurality of power pads 20P, a plurality of ground pads 20G, and a plurality of signal pads 20S. In this embodiment, the arrangement of the plurality of pads 20G, 20P, 20S, the plurality of circuits, and the plurality of solder balls 21 of the package substrate 2 may meet the requirements of the flip chip packaging technology.

[0040] Furthermore, if Figure 5 As shown, the support surface 2a of the package substrate 2 defines a chip default area 20a, and a plurality of pads 20G, 20P, and 20S may be located in the chip default area 20a. When the chip 1 is disposed on the package substrate 2, it is disposed with the first surface 1a facing the package substrate 2, that is, it is disposed on the package substrate 2 in a flip chip manner. A plurality of power pads 20P, a plurality of ground pads 20G, and a plurality of signal pads 20S are all located directly below the chip 1.

[0041] In addition, in this embodiment, the plurality of power pads 20P and the plurality of ground pads 20G may also be arranged into a plurality of groups. Further, the positions of the plurality of power pads 20P may correspond to the positions of the plurality of flip chip power pads P1, and the positions of the plurality of ground pads 20G may correspond to the positions of the plurality of flip chip ground pads G1. Similarly, the positions of the plurality of signal pads 20S may correspond to the second area A2 of the chip 1, and correspond to the positions of the plurality of signal pads S, respectively.

[0042] When the chip 1 is disposed on the package substrate 2, it can be electrically connected to the package substrate 2 through the conductive connection assembly 3. In this embodiment, the conductive connection assembly 3 is electrically and physically connected to the flip chip pad group 10, but not physically connected to the wire bonding pad group 12. That is, when the chip 1 is packaged using the flip chip packaging technology, the multiple wire bonding power pads P2 and the multiple wire bonding ground pads G2 of the chip 1 are all dummy pads.

[0043] In addition, depending on whether the flip chip packaging technology or the wire bonding packaging technology is used, the conductive connection assembly 3 of this embodiment may include a plurality of (conductive) bumps or a plurality of wires. Figure 5 In the embodiment of FIG. 5 , the conductive connection assembly 3 includes a plurality of power bumps 30P, a plurality of ground bumps 30G, and a plurality of signal bumps 30S.

[0044] Each power bump 30P is connected between the corresponding power pad 20P and the corresponding flip chip power pad P1, and each ground bump 30G is connected between the corresponding ground pad 20G and the corresponding flip chip ground pad G1. Each signal bump 30S is connected between the corresponding signal pad 20S and the corresponding signal pad S. In this way, the chip 1 can be fixed and electrically connected to the package substrate 2 through the conductive connection assembly 3. The packaging layer 4 covers the chip 1 and the supporting surface 2a of the package substrate 2 to protect the chip.

[0045] Please refer to Figure 6 , Figure 6 A partial side view schematic diagram of a chip packaging module M2 formed after the chip 1 is packaged using the wire bonding packaging technology is shown.

[0046] The chip packaging module M2 includes a chip 1, a packaging substrate 2, a conductive connection assembly 3' and a packaging layer 4. In this embodiment, the configuration of the multiple pads 20G, 20P, 20S, multiple circuits and multiple solder balls 21 of the packaging substrate 2 can meet the requirements of the lead bonding package. Therefore, the multiple pads 20G, 20P, 20S (including multiple power pads 20P, multiple ground pads 20G and multiple signal pads 20S) can be set outside the chip default area 20a and around the chip default area 20a.

[0047] In the embodiment, among the plurality of solder balls 21 disposed on the bottom surface 2b of the package substrate 2, a portion of the solder balls 21 may be electrically connected to the power pad 20P and the ground pad 20G, and the positions of these solder balls 21 may overlap with the position of the chip default area 20a. Therefore, compared with the signal pad 20S, the power pad 20P and the ground pad 20G of the package substrate 2 may be located closer to the chip default area 20a.

[0048] When the chip 1 is disposed on the package substrate 2, the second surface 1b is disposed toward the package substrate 2. That is, in this embodiment, the arrangement direction of the chip 1 is in the same direction as the package substrate 2. Figure 5 In contrast to the embodiment of the present disclosure, the first surface 1a is arranged upward. In addition, the chip packaging module M2 of the embodiment of the present disclosure further includes a glue layer 5, and the glue layer 5 is located between the chip 1 and the packaging substrate 2, so that the chip 1 can be fixed on the packaging substrate 2.

[0049] In addition, if Figure 6As shown, the shortest distance between any signal pad 20S and the chip 1 is greater than the shortest distance between any power pad 20P and the chip 1. In addition, the shortest distance between any signal pad 20S and the chip 1 may also be greater than the shortest distance between any ground pad 20G and the chip 1. As long as the above conditions are met, the configuration positions of the power pad 20P and the ground pad 20G may also be swapped with each other, and the present disclosure has no particular restrictions on this.

[0050] When the chip 1 is disposed on the package substrate 2, it can be electrically connected to the package substrate 2 through the conductive connection assembly 3'. Figure 5 Unlike the embodiment of the present invention, in the present embodiment, the conductive connection assembly 3' is electrically and physically connected to the wire bonding pad group 12, but not physically connected to the flip chip pad group 10. That is, when the chip 1 is packaged using the wire bonding packaging technology, the multiple flip chip power pads P1 and the multiple flip chip ground pads G1 of the chip 1 are all dummy pads.

[0051] In addition, Figure 6 In the embodiment of the present invention, the conductive connection assembly 3' includes a plurality of power conductors 30P', a plurality of ground conductors 30G', and a plurality of signal conductors 30S'. Each power conductor 30P' is connected between a corresponding power pad 20P and a corresponding wire bonding power pad P2, and each ground conductor 30G' is connected between a corresponding ground pad 20G and a corresponding wire bonding ground pad G2. Similarly, each signal conductor 30S' is connected between a corresponding signal pad 20S and a corresponding signal pad S. In this way, the chip 1 can be electrically connected to the package substrate 2 through the conductive connection assembly 3', and electrically connected to the external control circuit through a plurality of solder balls 21 on the package substrate 2.

[0052] It is worth noting that, regardless of whether the flip chip packaging technology or the wire bonding packaging technology is used, the signal pad group 11 of the chip 1 can be electrically connected to the conductive connection assembly 3 (3'). That is, when the chip 1 is bonded to the packaging substrate 2 in a flip chip manner, the plurality of signal pads S can be respectively connected to the plurality of signal bumps 30S, so as to be respectively electrically connected to the plurality of signal pads 20S. When the chip 1 is bonded to the packaging substrate 2 in a wire bonding manner, the plurality of signal pads S can be respectively connected to the plurality of signal wires 30S', so as to be respectively electrically connected to the plurality of signal pads 20S.

[0053] The beneficial effect of the technical solution of the present disclosure is at least that the chip packaging modules M1 and M2 provided by the present disclosure can further increase the flexibility of the chip 1 at the application end by using the technical solutions of "the chip 1 includes a flip chip pad group 10, a wire bonding pad group 12 and a signal pad group 11" and "one of the flip chip pad group 10 and the wire bonding pad group 12 is electrically and physically connected to the conductive connection assembly 3, 3', while the other is not physically connected to the conductive connection assembly 3, 3'". That is to say, the chip 1 provided in the embodiment of the present disclosure can be applied to two different packaging technologies.

[0054] For example, according to actual needs, the chip 1 of the embodiment of the present disclosure can be packaged using flip chip packaging technology to manufacture a chip packaging module M1 that can be used in higher-end electronic products. In addition, the chip 1 of the embodiment of the present disclosure can also be packaged using wire bonding packaging technology to manufacture a chip packaging module M2 that can be used in mid-end or low-end electronic products.

[0055] The contents disclosed above are only preferred feasible embodiments of the present disclosure, and are not intended to limit the protection scope of the claims of the present disclosure. Therefore, all equivalent technical changes made using the contents of the present disclosure specification and drawings are included in the protection scope of the claims of the present disclosure.

Claims

1. A chip packaging module, include: Package substrate: A chip is arranged on the packaging substrate, wherein the chip has a first surface and a second surface opposite to the first surface, the first surface is divided into a first area, a second area and a third area, the second area is located between the first area and the third area, and the chip comprises: A flip chip pad group, which is located in the first area; a wire bonding pad group located in the third area; and a signal pad group, which is located in the second area; and A conductive connection assembly electrically connected between the chip and the package substrate, wherein one of the flip chip pad group and the wire bonding pad group is electrically and physically connected to the conductive connection assembly, and the other is not physically connected to the conductive connection assembly; Among them, the lead bonding pad group includes multiple lead bonding power pads and multiple lead bonding grounding pads, multiple lead bonding grounding pads are arranged in a first row along one side edge of the chip, multiple lead bonding power pads are arranged in a second row along the side edge, and two adjacent lead bonding power pads and lead bonding grounding pads are staggered with each other.

2. The chip packaging module according to claim 1, in, The first area is located in a central area of ​​the first surface, the second area surrounds the first area, and the third area surrounds the second area.

3. The chip packaging module according to claim 1, in, The flip chip pad group includes a plurality of flip chip power pads and a plurality of flip chip ground pads arranged in a plurality of groups, the chip is arranged with the first surface facing the packaging substrate, the packaging substrate includes a plurality of power pads, a plurality of ground pads and a plurality of signal pads, and the plurality of power pads, the plurality of ground pads and the plurality of signal pads are all arranged directly below the chip.

4. The chip packaging module according to claim 3, in, The signal pad group includes a plurality of signal pads, the conductive connection assembly is electrically and physically connected to the flip chip pad group, and includes: A plurality of power bumps, wherein each of the power bumps is connected between a corresponding power pad and a corresponding flip chip power pad; a plurality of ground bumps, wherein each of the ground bumps is connected between a corresponding ground pad and a corresponding flip chip ground pad; and A plurality of signal bumps are provided, wherein each of the signal bumps is connected between a corresponding signal pad and a corresponding signal pad.

5. The chip packaging module according to claim 1, in, The signal pad group includes a plurality of signal pads, and the plurality of signal pads are arranged around the first area. The flip chip pad group includes a plurality of flip chip grounding pads arranged in at least one column, and the spacing between any two adjacent signal pads is greater than the spacing between any two adjacent flip chip grounding pads.

6. The chip packaging module according to claim 1, in, The chip is arranged with the second surface facing the packaging substrate, the packaging substrate comprises a plurality of power pads, a plurality of ground pads and a plurality of signal pads, and the plurality of power pads, the plurality of ground pads and the plurality of signal pads are arranged around the chip; The shortest distance between any of the signal pads and the chip is greater than the shortest distance between any of the power pads and the chip, and the shortest distance between any of the signal pads and the chip is greater than the shortest distance between any of the ground pads and the chip.

7. The chip packaging module according to claim 6, in, The signal pad group includes a plurality of signal pads, the conductive connection assembly is electrically and physically connected to the wire bonding pad group, and the conductive connection assembly includes: A plurality of power conductors, wherein each of the power conductors is connected between a corresponding power pad and a corresponding wire bonding power pad; a plurality of grounding wires, wherein each of the grounding wires is connected between a corresponding grounding pad and a corresponding wire bonding grounding pad; and A plurality of signal wires are provided, wherein each of the signal wires is connected between a corresponding signal pad and a corresponding signal pad.

8. The chip packaging module as claimed in claim 1, wherein the flip chip pad group includes a plurality of flip chip grounding pads and a plurality of flip chip power pads, and the spacing between any two adjacent wire bonding grounding pads is greater than the spacing between any two adjacent flip chip grounding pads.

9. The chip packaging module according to claim 1, in, The package substrate has a support surface and a bottom surface opposite to the support surface, the chip is arranged on the support surface, and the package substrate includes a plurality of solder balls arranged on the bottom surface, and the conductive connection assembly is electrically and physically connected to the signal pad group.

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