Array substrate, display panel and display device

Abstract

The present application discloses an array substrate, a display panel and a display device, belonging to the field of display technology. The array substrate includes: a pixel driving circuit, which is arranged in rows and columns corresponding to each pixel area; a first initialization signal line extends along the row direction, and a plurality of first initialization signal lines are arranged in a spaced relationship along the column direction; a second initialization signal line is arranged corresponding to each pixel area, and is located in a different layer and intersects with the first initialization signal line in space, and the second initialization signal line of each pixel area is electrically connected to the corresponding first initialization signal line; a third initialization signal line is arranged corresponding to at least part of the pixel area, and is located in a different layer and intersects with the first initialization signal line in space, and the third initialization signal line corresponding to the same pixel area is electrically connected to the second initialization signal line, and the third initialization signal line in the pixel area corresponding to the i-th first initialization signal line is electrically connected to the i+1-th first initialization signal line. According to the embodiments of the present application, the display effect can be improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, the functions of display panels have also increased. In order to realize functions such as display shooting and light sensing, it is necessary to integrate functional components such as cameras and infrared photosensitive components into the display panel.

[0003] In order to integrate functional components such as cameras and infrared photosensitive elements, it is necessary to remove the pixel driving circuit at the predetermined position and set the camera, infrared photosensitive element and other functional components at the predetermined position. However, such a setting will cause the continuously arranged pixel driving circuit to be disconnected at the predetermined position, and the structure around the predetermined position will be affected by the disconnection, and the characteristics will have certain differences, thereby causing the display brightness around the predetermined position of the display panel to be different, resulting in a split screen phenomenon, which reduces the display effect of the display panel. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel and a display device, which can improve or eliminate the split-screen phenomenon and enhance the display effect.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising: a pixel driving circuit, which is distributed in rows and columns corresponding to each pixel area; a first initialization signal line, which extends in the row direction, and a plurality of first initialization signal lines are distributed in the column direction at intervals from each other; a second initialization signal line, which is arranged corresponding to each pixel area, the second initialization signal line and the first initialization signal line are located in different layers and intersect in space, and the second initialization signal line corresponding to each pixel area is electrically connected to the corresponding first initialization signal line; a third initialization signal line, which is arranged corresponding to at least part of the pixel area, the third initialization signal line and the first initialization signal line are located in different layers and intersect in space, the third initialization signal line corresponding to the same pixel area is electrically connected to the second initialization signal line, and the third initialization signal line of the pixel area corresponding to the i-th first initialization signal line is electrically connected to the i+1-th first initialization signal line, where i is a positive integer.

[0006] In some possible embodiments, a pixel region corresponding to the target sub-pixel is provided with a third initialization signal line, and each pixel region corresponds to one sub-pixel;

[0007] The target sub-pixel includes one or two sub-pixels of a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0008] In some possible embodiments, the second initialization signal line is electrically connected to the first initialization signal line through the first via hole;

[0009] The third initialization signal line is electrically connected to the first initialization signal line through the second via hole.

[0010] In some possible embodiments, one end of the second initialization signal line is electrically connected to the first initialization signal line, and the other end of the second initialization signal line is electrically connected to the pixel driving circuit.

[0011] In some possible embodiments, the array substrate further includes a light-emitting element, which is disposed in each pixel region; the pixel driving circuit includes a first initialization transistor, a second initialization transistor, a driving transistor and a storage capacitor, the first initialization transistor is electrically connected to the storage capacitor and the driving transistor, and the second initialization transistor is electrically connected to the light-emitting element;

[0012] The other end of the second initialization signal line corresponding to the first target pixel area is electrically connected to the first initialization transistor, and is electrically connected to the second initialization transistor in the second target pixel area.

[0013] The first target pixel region includes any pixel region, and the second target pixel region is a pixel region adjacent to the first target pixel region in a column direction.

[0014] In some possible embodiments, one end of the third initialization signal line corresponding to the third target pixel region is electrically connected to the first initialization transistor, and is electrically connected to the second initialization transistor corresponding to the fourth target pixel region, and the other end of the third initialization signal line is electrically connected to the first initialization signal line;

[0015] The third target pixel region includes any pixel region corresponding to the third initialization signal line, and the fourth target pixel region is a pixel region adjacent to the third target pixel region in a column direction.

[0016] In some possible embodiments, the pixel driving circuit includes a driving transistor;

[0017] A portion of the third initialization signal line corresponding to the fifth target pixel region is located between the target data line and the driving transistor in the fifth target pixel region.

[0018] The fifth target pixel region includes any pixel region corresponding to which the third initialization signal line is set, and the target data line is adjacent to the data line corresponding to the fifth target pixel region.

[0019] In some possible embodiments, the array substrate further includes a power supply signal line and a light emitting element, the power supply signal line extends along a column direction, and the light emitting element is arranged in each pixel region;

[0020] A portion of the third initialization signal line corresponding to the sixth target pixel region is located between the anode of the light emitting element in the sixth target pixel region and the power supply signal line.

[0021] The sixth target pixel region includes any one pixel region where the third initialization signal line is disposed.

[0022] In some possible embodiments, the second initialization signal line, the third initialization signal line and the data line are located in the same layer.

[0023] In some possible embodiments, the array substrate further includes a power supply signal line, and the second initialization signal line, the third initialization signal line, the data line and the power supply signal line are located in the same layer.

[0024] In a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate of the first aspect.

[0025] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel of the second aspect.

[0026] The present application provides an array substrate, a display panel and a display device, wherein the array substrate includes a pixel driving circuit arranged in rows and columns corresponding to each pixel area, a second initialization signal line arranged corresponding to each pixel area and a third initialization signal line arranged corresponding to at least part of the pixel area. The second initialization signal line is arranged in layers and electrically connected to the first initialization signal line. The third initialization signal line is electrically connected to the second initialization signal line. The third initialization signal line is arranged in layers and electrically connected to the first initialization signal line. The second initialization signal line and the third initialization signal line make two adjacent first initialization signal lines electrically connected, reduce the resistance of the signal line transmitting the initialization signal, reduce the load difference of the initialization signal of different pixel areas, improve the transmission capacity of the initialization signal, thereby reducing the difference of the initialization signal of the pixel driving circuit around the functional element setting, improve or eliminate the split screen phenomenon, and improve the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 is a schematic diagram of an example of a display panel integrated with functional elements;

[0029] Figure 2 A schematic top view of an example of an array substrate provided in an embodiment of the present application;

[0030] Figure 3 An equivalent circuit diagram of an example of a pixel driving circuit provided in an embodiment of the present application;

[0031] Figure 4This is a schematic structural diagram of an example of a local area in an array substrate in an embodiment of the present application;

[0032] Figure 5 A schematic structural diagram of another example of a local area in an array substrate in an embodiment of the present application;

[0033] Figure 6 for Figure 5 A schematic diagram of an example of a pattern of the M1 metal layer of the array substrate;

[0034] Figure 7 for Figure 5 A schematic diagram of an example of a pattern of the M2 metal layer of the array substrate;

[0035] Figure 8 for Figure 5 A schematic diagram of an example of a pattern of the M3 metal layer of the array substrate;

[0036] Fig. 9 A schematic diagram of the structure of an example of a display panel provided in the present application. DETAILED DESCRIPTION

[0037] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0038] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0039] With the development of display technology, the functions of display panels have also increased. In order to realize functions such as display shooting and light sensing, it is necessary to integrate functional components such as cameras and infrared photosensitive components into the display panel. Figure 1 FIG. 1 is a schematic diagram of an example of a display panel integrated with functional elements. Figure 1As shown, a functional element 11 is provided on the display panel 10. No pixel driving circuit is provided in the area where the functional element 11 is located. In other words, the continuously arranged pixel driving circuits are disconnected at the functional element 11. This causes the wiring and other structures around the functional element 11 to be affected by the disconnection, resulting in a difference in display brightness around the functional element 11 of the display panel, thereby causing a split screen phenomenon and reducing the display effect of the display panel.

[0040] The present application provides an array substrate, a display panel and a display device. By setting an initialization signal line extending along the row direction and an initialization signal line extending at least partially along the column direction, the resistance of the initialization signal line is reduced and the transmission capacity of the initialization signal is improved, thereby reducing the difference in the initialization signal of the pixel driving circuit around the functional element setting, improving or eliminating the split screen phenomenon, and improving the display effect.

[0041] The array substrate provided by the present application is introduced below. Figure 2 FIG. 1 is a schematic top view of an example of an array substrate provided in an embodiment of the present application. Figure 2 As shown, the array substrate 20 has pixel regions 21 distributed in rows and columns. The pixel regions 21 may be formed by interlacing data lines Vdata and scan lines Scan.

[0042] The array substrate 20 has a predetermined area 22. The predetermined area 22 can be used to set functional elements such as a camera, an infrared photosensitive element, etc. The pixel area 21 may not be set in the predetermined area 22.

[0043] The array substrate 20 includes a pixel driving circuit 23. The pixel driving circuits 23 are arranged in rows and columns corresponding to the pixel regions 21 of the array substrate 20. Each pixel region 21 may be provided with a pixel driving circuit 23. The pixel driving circuit 23 may not be provided in the predetermined region 22. The pixel driving circuit 23 is used to drive the light-emitting element corresponding to the pixel region 21 to emit light. Specifically, the pixel driving circuit 23 may include components such as transistors and capacitors having a connection relationship, and the specific structure of the pixel driving circuit 23 is not limited here.

[0044] The array substrate further includes a first initialization signal line Vr1. The first initialization signal line Vr1 can provide an initialization signal for the pixel driving circuit 23. The initialization signal can be used to initialize some components and light-emitting elements in the pixel driving circuit 23.

[0045] For ease of explanation, a 7T1C pixel driving circuit including 7 transistors and 1 capacitor is taken as an example to briefly explain the parts related to the embodiments of the present application. Figure 3 FIG. 1 is an equivalent circuit diagram of an example of a pixel driving circuit provided in an embodiment of the present application. Figure 3As shown, the pixel driving circuit includes transistors T1 to T7 and a storage capacitor C1, wherein the transistor T1 is a first initialization transistor, the transistor T2 is a second initialization transistor, and the transistor T3 is a driving transistor.

[0046] The control end of the first initialization transistor T1 is connected to the scan line Scan n, the first end of the first initialization transistor is connected to the initialization signal line Vref and the first initialization signal line in the embodiment of the present application, and the second end of the first initialization transistor is connected to the storage capacitor C1 and the control end of the driving transistor T3. Through the first initialization transistor, the control end of the driving transistor T3 and the storage capacitor C1 can be initialized using the initialization signal provided by the first initialization signal line.

[0047] The control end of the second initialization transistor T2 is connected to the scan line Scan n+1, the first end of the second initialization transistor T2 is connected to the initialization signal line Vref, that is, the first initialization signal line in the embodiment of the present application, and the second end of the second initialization transistor T2 is connected to the anode of the light-emitting element D1. Through the second initialization transistor T2, the anode of the light-emitting element D1 can be initialized using the initialization signal provided by the first initialization signal line.

[0048] The array substrate may further include a second initialization signal line and a third initialization signal line. For the convenience of description, a local area in the array substrate is taken for specific description. Figure 4 FIG. 1 is a schematic diagram of an example of a local area of ​​an array substrate in an embodiment of the present application. Figure 4 As shown, the array substrate is provided with a first initialization signal line Vr1, a second initialization signal line Vr2 and a third initialization signal line Vr3. The first initialization signal line Vr1, the second initialization signal line Vr2 and the third initialization signal line Vr3 can all transmit initialization signals.

[0049] The first initialization signal line Vr1 extends along the row direction. A plurality of first initialization signal lines Vr1 are spaced apart from each other along the column direction. One row of pixel regions corresponds to one first initialization signal line Vr1, that is, one row of pixel regions shares one first initialization signal line Vr1.

[0050] The second initialization signal line Vr2 is set corresponding to each pixel area. The second initialization signal line Vr2 and the first initialization signal line Vr1 are located in different layers and intersect in space. The second initialization signal line Vr2 and the first initialization signal line Vr1 intersect in space means that the projection of the first initialization signal line Vr1 on the plane defined by the row direction and the column direction partially overlaps with the projection of the second initialization signal line Vr2 on the plane defined by the row direction and the column direction. The second initialization signal line Vr2 extends along the column direction. The second initialization signal line Vr2 corresponding to each pixel area is electrically connected to the first initialization signal line corresponding to the pixel area. In some examples, such as Figure 4 As shown, the second initialization signal line Vr2 may be electrically connected to the first initialization signal line Vr1 through the first via hole 24. The first via hole 24 may be an inter-layer dielectric (ILD) via hole.

[0051] The third initialization signal Vr3 is set corresponding to at least part of the pixel area. The third initialization signal line Vr3 and the first initialization signal line Vr1 are located in different layers and intersect in space. The spatial intersection of the third initialization signal line Vr3 and the first initialization signal line Vr1 means that the projection of the first initialization signal line Vr1 on the plane defined by the row direction and the column direction overlaps with the projection of the third initialization signal line Vr3 on the plane defined by the row direction and the column direction. Part of the third initialization signal line Vr3 extends along the column direction. In some examples, the third initialization signal line Vr3 can be set to bypass the driving transistor T3. The third initialization signal line Vr3 corresponding to the same pixel area 21 is electrically connected to the second initialization signal line Vr2. The third initialization signal line of the pixel area 21 corresponding to the i-th first initialization signal line Vr1 is electrically connected to the i+1-th first initialization signal line Vr1, where i is a positive integer. The i-th first initialization signal line Vr1 is any first initialization signal line in the array substrate except the last first initialization signal line. The i-th row first initialization signal line Vr1 corresponds to the i-th row pixel area. Corresponding to the pixel area of ​​the i-th row, the i-th first initialization signal line Vr1 can be electrically connected to the i+1-th first initialization signal line Vr1 through the second initialization signal line Vr2 and the third initialization signal line Vr3 of at least part of the pixel area. The i+1-th first initialization signal line Vr1 is the first initialization signal line Vr1 adjacent to the i-th first initialization signal line Vr1. In some examples, the third initialization signal line Vr3 is electrically connected to the first initialization signal line Vr1 through the second via 25. The second via 25 can be specifically an ILD via.

[0052] In some examples, in two pixel regions adjacent to each other along the column direction, the second via hole 25 corresponding to one pixel region and the first via hole 24 corresponding to the other pixel region may be the same via hole, which is not limited here.

[0053] In the embodiment of the present application, the array substrate 20 includes a pixel driving circuit 23 arranged in rows and columns corresponding to each pixel area 21, a second initialization signal line Vr2 arranged corresponding to each pixel area 21, and a third initialization signal line Vr3 arranged corresponding to at least part of the pixel area 21. The second initialization signal line Vr2 is layered and electrically connected to the first initialization signal line Vr1. The third initialization signal line Vr3 is electrically connected to the second initialization signal line Vr2. The third initialization signal line Vr3 is layered and electrically connected to the first initialization signal line Vr1. The second initialization signal line Vr2 and the third initialization signal line Vr3 make the two adjacent first initialization signal lines Vr1 electrically connected, reduce the resistance of the signal line transmitting the initialization signal, reduce the load difference of the initialization signal of different pixel areas, improve the transmission capacity of the initialization signal, thereby reducing the difference of the initialization signal of the pixel driving circuit around the functional element setting, improve or eliminate the split screen phenomenon, and improve the display effect.

[0054] In some examples, such as Figure 4 As shown, each pixel region may be correspondingly provided with a third initialization signal line Vr3. Each pixel region corresponds to a sub-pixel.

[0055] In some other examples, a third initialization signal line Vr3 may be correspondingly disposed in a portion of the pixel regions. Figure 5 FIG. 2 is a schematic diagram of another example of a local area in an array substrate in an embodiment of the present application. Figure 5 As shown, the third initialization signal line Vr3 is set corresponding to a part of the pixel area. Specifically, the pixel area of ​​the target sub-pixel is corresponding to the third initialization signal line Vr3. Each pixel area corresponds to a sub-pixel. The target sub-pixel may include one or two sub-pixels of a first sub-pixel, a second sub-pixel, and a third sub-pixel. The colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different. The first sub-pixel, the second sub-pixel, and the third sub-pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0056] For example, the target sub-pixel includes a red sub-pixel, that is, the pixel area of ​​the red sub-pixel is correspondingly set with the third initialization signal line Vr3, and the pixel area of ​​the green sub-pixel and the pixel area of ​​the blue sub-pixel are not correspondingly set with the third initialization signal line Vr3. For another example, the target sub-pixel includes a red sub-pixel and a green sub-pixel, that is, the pixel area of ​​the red sub-pixel and the pixel area of ​​the green sub-pixel are correspondingly set with the third initialization signal line Vr3, and the pixel area of ​​the blue sub-pixel is not correspondingly set with the third initialization signal line Vr3.

[0057] The third initialization signal line Vr3 is only set corresponding to part of the pixel area, which can improve or eliminate the split screen phenomenon and improve the display effect, simplify the wiring structure of the array substrate, and improve the transmittance, which is beneficial to the design of optical fingerprint recognition in the display panel.

[0058] In some examples, such as Figure 4 and Figure 5 As shown, the second initialization signal line Vr2, the third initialization signal line Vr3 and the data line Vdata can be located in the same layer. Specifically, the first initialization signal line Vr1 can be located in the M2 metal layer, and the second initialization signal line Vr2, the third initialization signal line Vr3 and the data line Vdata can all be located in the M3 metal layer.

[0059] In other examples, such as Figure 4 and Figure 5 As shown, the array substrate may further include a power supply signal line VDD. The power supply signal line VDD may provide a power supply signal. The second initialization signal line Vr2, the third initialization signal line Vr3, the data line Vdata and the power supply signal line VDD may be located in the same layer. Specifically, the first initialization signal line Vr1 may be located in the M2 metal layer, and the second initialization signal line Vr2, the third initialization signal line Vr3, the data line Vdata and the power supply signal line VDD may all be located in the M3 metal layer.

[0060] In the array substrate, in order from near to far from the substrate, the array substrate may include an M1 metal layer, an M2 metal layer and an M3 metal layer. Among them, the M1 metal layer may include a scan line Scan and a signal control line EM. The signal control line EM may provide a switch control signal. The M2 metal layer may include a first initialization signal line Vr1. The M3 metal layer may include a data line Vdata and a power supply signal line VDD. The second initialization signal line Vr2 and the third initialization signal line Vr3 in the embodiment of the present application may be arranged in the M3 metal layer. The material of the M2 metal layer may be molybdenum (Mo) metal, which is not limited here. The M3 metal layer may be a titanium (Ti) / aluminum (Al) / titanium (Ti) multilayer metal structure, which is not limited here.

[0061] For ease of explanation, Figure 6 , Figure 7 and Figure 8 Specific patterns of the M1 metal layer, the M2 metal layer and the M3 metal layer in the array substrate of the embodiment of the present application are shown. Figure 6 for Figure 5 A schematic diagram of an example of the pattern of the M1 metal layer of the array substrate. Figure 7 for Figure 5 A schematic diagram of an example of the pattern of the M2 metal layer of the array substrate. Figure 8 for Figure 5Schematic diagram of an example of the pattern of the M3 metal layer of the array substrate. The specific contents of the M1 metal layer, the M2 metal layer and the M3 metal layer can be found in the above related descriptions, which will not be repeated here.

[0062] like Figures 4 to 8 As shown, one end of the second initialization signal line Vr2 can be electrically connected to the first initialization signal line Vr1, and the other end of the second initialization signal line Vr2 can be electrically connected to the pixel driving circuit 23. Specifically, the other end of the second initialization signal line Vr2 corresponding to any pixel area, that is, the first target pixel area, can be electrically connected to the first initialization transistor T1 in the first target pixel area. Furthermore, the other end of the second initialization signal line Vr2 corresponding to the first target pixel area can be electrically connected to the first end of the first initialization transistor T1 in the pixel driving circuit 23 corresponding to the first target pixel area. The initialization signal in the first initialization signal line Vr1 can be transmitted to the first initialization transistor T1 through the second initialization signal line Vr2, and then transmitted to the control end of the driving transistor T3 and the storage capacitor C1 through the first initialization transistor T1. The second initialization signal line Vr2 and the first initialization transistor T1 can be electrically connected through the semiconductor layer of the transistor. The first initialization transistor and the storage capacitor C1 can be electrically connected through the semiconductor layer of the transistor and the conductive connection.

[0063] The other end of the second initialization signal line Vr2 corresponding to the first target pixel area can also be electrically connected to the second initialization transistor T2 in the second target pixel area. The second target pixel area is a pixel area adjacent to the first target pixel area in the column direction. Specifically, the other end of the second initialization signal line Vr2 corresponding to the first target pixel area is electrically connected to the first end of the second initialization transistor T2 of the pixel driving circuit 23 in the second target pixel area. The initialization signal of the first initialization signal line Vr1 corresponding to the first target pixel area can be transmitted to the second initialization transistor T2 in the second target pixel area through the second initialization signal line Vr2, and then transmitted to the anode Anode of the light-emitting element D1 in the second target pixel area through the second initialization transistor T2. The second initialization signal line Vr2 and the second initialization transistor T2 can be electrically connected through the semiconductor layer of the transistor. The second initialization transistor T2 and the anode Anode of the light-emitting element D1 can be electrically connected through the semiconductor layer of the transistor.

[0064] Any corresponding pixel region provided with the third initialization signal line Vr3, that is, one end of the third initialization signal line Vr3 corresponding to the third target pixel region can be electrically connected to the first initialization transistor T1 in the third target pixel region. Specifically, one end of the third initialization signal line Vr3 corresponding to the third target pixel region can be electrically connected to the first end of the first initialization transistor T1 of the pixel driving circuit 23 in the third target pixel region. One end of the third initialization signal line Vr3 corresponding to the third target pixel region can also be electrically connected to the second initialization transistor T2 in the fourth target pixel region. The fourth pixel region is a pixel region adjacent to the third target pixel region in the column direction. Specifically, one end of the third initialization signal line Vr3 corresponding to the third target pixel region is electrically connected to the first end of the second initialization transistor T2 of the pixel driving circuit 23 in the fourth target pixel region. By electrically connecting the second initialization signal line Vr2, the third initialization signal line Vr3 with the first initialization transistor T1 and the second initialization transistor T2, the second initialization signal line Vr2 and the third initialization signal line Vr3 can be electrically connected, thereby realizing the electrical connection between the first initialization signal line Vr1 corresponding to the third target pixel area and the first initialization signal line Vr1 corresponding to the fourth target pixel area, that is, realizing the electrical connection between the two adjacent first initialization signal lines Vr1.

[0065] The first target pixel region in the above embodiment may include a third target pixel region.

[0066] The third initialization signal line may be a bent signal line and may bypass the storage capacitor in the pixel driving circuit and the anode of the light emitting element.

[0067] In some examples, a portion of the third initialization signal line Vr3 corresponding to any pixel region, that is, the fifth target pixel region, is located between the target data line and the driving transistor T3 in the fifth target pixel region. The target data line is adjacent to the data line Vdata corresponding to the fifth target pixel region.

[0068] The fifth target pixel region may be the same as the third target pixel region.

[0069] The third initialization signal line Vr3 is located between the target data line and the driving transistor T3, which can shield the influence of the data line Vdata in the adjacent pixel area on the driving transistor T3 in the pixel area, improve the accuracy of the pixel driving circuit in driving the light-emitting element, and further improve the display effect.

[0070] In some examples, a portion of the third initialization signal line Vr3 corresponding to any pixel region provided with the third initialization signal line Vr3, that is, the sixth target pixel region, is located between the anode Anode of the light-emitting element D1 in the sixth target pixel region and the target power supply signal line. The target power supply signal line is the power supply signal line VDD corresponding to the sixth target pixel region.

[0071] The sixth target pixel region may be the same as the third target pixel region. The sixth target pixel region may also be the same as the fifth target pixel region.

[0072] The third initialization signal line Vr3 is located between the anode Anode of the light-emitting element D1 in this pixel area and the power supply signal line VDD, which can shield the influence of the power supply signal in the power supply signal line VDD on the anode via and anode Anode of the light-emitting element D1, thereby improving the accuracy of the pixel driving circuit in driving the light-emitting element, thereby further improving the display effect.

[0073] The third initialization signal line Vr3 may be specifically an integrated structure routing. The third initialization signal line may include a first routing portion and a second routing portion that are successively distributed. The first routing portion is arranged to bypass the storage capacitor, and may be an arc-shaped routing or an L-shaped routing, etc. The second routing portion is arranged to bypass the anode of the light-emitting element, and may be an arc-shaped routing or an L-shaped routing, etc.

[0074] For example, Figure 8 As shown, the first routing portion 26 may include a first sub-routing portion 261 and a second sub-routing portion 262, and the second routing portion 27 may include a third sub-routing portion 271 and a fourth sub-routing portion 272. Among them, the first sub-routing portion 261 is parallel to the third sub-routing portion 271 and extends in the column direction. The second sub-routing portion 262 is parallel to the fourth routing portion 272 and extends in the row direction. The first sub-routing portion 261, the second sub-routing portion 262, the third sub-routing portion 273 and the fourth sub-routing portion 272 are distributed successively. The first sub-routing portion 261 is located between the data line in the adjacent pixel area and the driving transistor in the pixel area. The third sub-routing portion 271 is located between the anode of the light-emitting element in the pixel area and the power supply signal line VDD corresponding to the pixel area.

[0075] An embodiment of the present application further provides a display panel, which includes the array substrate in the above embodiment. Fig. 9 This is a schematic diagram of an example of a display panel provided in this application. Fig. 9 As shown, the display panel 30 has a display area 31 , a first non-display area 32 and a second non-display area 33 .

[0076] The first non-display area 32 may be arranged around the display area 31. The display area 31 may be arranged around the second non-display area 33. Functional elements such as a camera and an infrared sensing element may be installed corresponding to the second non-display area 33, but are not limited here.

[0077] The display area 31 is provided with the pixel region 21, the pixel driving circuit 23, the first initialization signal line Vr1, the second initialization signal line Vr2 and the third initialization signal line Vr3 in the above embodiment. For details, please refer to the relevant description in the above embodiment, which will not be repeated here.

[0078] The display panel in the embodiments of the present application may include a panel with a display function of a mobile phone, a tablet, a PDA, an IPAD, a wearable device, an electronic photo frame, an electronic paper, and the like, but is not limited thereto.

[0079] The present application also provides a display device, which may include the display panel in the above embodiment. The display device may include a mobile phone, a tablet, a PDA, an IPAD, a wearable device, an electronic photo frame, an electronic paper, and other devices with display functions, which are not limited here.

[0080] It should be clear that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For the display panel embodiment and the display device embodiment, the relevant parts can refer to the description part of the array substrate embodiment. The present application is not limited to the specific structure described above and shown in the figures. Those skilled in the art can make various changes, modifications and additions after understanding the spirit of the present application. In addition, for the sake of brevity, a detailed description of the known technology is omitted here.

[0081] Those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on the study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other devices or steps; the quantifier "one" does not exclude a plurality; the terms "first" and "second" are used to indicate names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The presence of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A pixel driving circuit is arranged in rows and columns corresponding to each pixel area, and the pixel driving circuit includes a driving transistor; A first initialization signal line extends along a row direction, and a plurality of the first initialization signal lines are spaced apart from each other along a column direction; a second initialization signal line, arranged corresponding to each of the pixel regions, the second initialization signal line and the first initialization signal line being located in different layers and intersecting in space, the second initialization signal line corresponding to each of the pixel regions being electrically connected to the corresponding first initialization signal line; a third initialization signal line, arranged corresponding to at least part of the pixel area, the third initialization signal line and the first initialization signal line are located in different layers and intersect each other in space, the third initialization signal line corresponding to the same pixel area is electrically connected to the second initialization signal line, the third initialization signal line of the pixel area corresponding to the i-th first initialization signal line is electrically connected to the i+1-th first initialization signal line, where i is a positive integer; a fifth target pixel region, comprising any one of the pixel regions corresponding to which the third initialization signal line is arranged, a portion of the third initialization signal line corresponding to the fifth target pixel region is located between a target data line and the driving transistor in the fifth target pixel region, and the target data line is adjacent to the data line corresponding to the fifth target pixel region; The array substrate further comprises a power supply signal line and a light emitting element, wherein the power supply signal line extends along the column direction, and the light emitting element is arranged in each of the pixel regions; The sixth target pixel region includes any one of the pixel regions provided with the third initialization signal line, and a portion of the third initialization signal line corresponding to the sixth target pixel region is located between the anode of the light-emitting element in the sixth target pixel region and the power supply signal line.

2. The array substrate according to claim 1, characterized in that: The pixel area corresponding to the target sub-pixel is correspondingly provided with the third initialization signal line, and each of the pixel areas corresponds to one sub-pixel; The target sub-pixel includes one or two sub-pixels of a first sub-pixel, a second sub-pixel, and a third sub-pixel.

3. The array substrate according to claim 1, characterized in that: The second initialization signal line is electrically connected to the first initialization signal line through a first via hole; The third initialization signal line is electrically connected to the first initialization signal line through a second via hole.

4. The array substrate according to claim 1, characterized in that: One end of the second initialization signal line is electrically connected to the first initialization signal line, and the other end of the second initialization signal line is electrically connected to the pixel driving circuit.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes a light-emitting element, which is disposed in each of the pixel regions; the pixel driving circuit includes a first initialization transistor, a second initialization transistor, a driving transistor and a storage capacitor, the first initialization transistor is electrically connected to the storage capacitor and the driving transistor, and the second initialization transistor is electrically connected to the light-emitting element; The other end of the second initialization signal line corresponding to the first target pixel area is electrically connected to the first initialization transistor, and is electrically connected to the second initialization transistor in the second target pixel area. The first target pixel region includes any one of the pixel regions, and the second target pixel region is the pixel region adjacent to the first target pixel region in a column direction.

6. The array substrate according to claim 5, characterized in that: One end of the third initialization signal line corresponding to the third target pixel region is electrically connected to the first initialization transistor, and is electrically connected to the second initialization transistor corresponding to the fourth target pixel region, and the other end of the third initialization signal line is electrically connected to the first initialization signal line; The third target pixel region includes any one of the pixel regions corresponding to the third initialization signal line, and the fourth target pixel region is the pixel region adjacent to the third target pixel region in the column direction.

7. The array substrate according to claim 1, characterized in that: The array substrate further includes a data line, and the second initialization signal line, the third initialization signal line and the data line are located in the same layer.

8. The array substrate according to claim 7, characterized in that: The array substrate further includes a power supply signal line, and the second initialization signal line, the third initialization signal line, the data line and the power supply signal line are located in the same layer.

9. A display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel according to claim 9.

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