Chips and electronic devices

Abstract

The present invention provides a chip, including a substrate and a guard ring structure, wherein the guard ring structure is arranged on the substrate and around the edge of the substrate, the guard ring structure includes an inner ring and an outer ring, and the guard ring structure also includes a pressure dispersion structure, wherein the pressure dispersion structure includes a pressure dispersion unit, and the pressure dispersion unit is arranged on the substrate and connected between the inner ring and the outer ring. The chip of the present invention significantly improves the strength of the guard ring structure by arranging a pressure dispersion structure in the guard ring structure, and the pressure dispersion structure includes a pressure dispersion unit, and the pressure dispersion unit is connected between the inner ring and the outer ring of the guard ring structure, thereby improving its pressure resistance, reducing cracks in the chip caused by stress, and greatly reducing the breakage rate of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices, and in particular to a chip and an electronic device. Background Art

[0002] On semiconductor integrated circuit chips, a guard ring is generally set around the integrated circuit. The guard ring is generally formed by the interconnect layer metal and the plug layer metal, and is close to the chip's cutting path. It serves as a protective barrier during the chip packaging and cutting process to prevent the chip from being damaged. At the same time, it can prevent moisture from entering the chip and causing damage to the integrated circuit, ensuring the chip's good product reliability. However, the traditional guard ring has a weak pressure resistance, and it is still inevitable that it will break during the chip packaging and cutting process, resulting in internal damage.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute related technology known to ordinary technicians in the field. Summary of the invention

[0004] One object of the present invention is to overcome the deficiencies of the above-mentioned related technologies and to provide a chip, which is provided with a protective ring structure. By arranging a pressure dispersion structure between the inner ring and the outer ring of the protective ring structure, the strength of the protective ring can be significantly improved, thereby improving its pressure resistance, avoiding damage to the internal structure of the chip, and greatly reducing the breakage rate of the chip.

[0005] Another object of the present invention is to provide an electronic device, comprising the chip with the guard ring structure, so that the service life of the electronic device is improved.

[0006] According to one aspect of the present invention, there is provided a chip, comprising a substrate and a guard ring structure, wherein the guard ring structure is disposed on the surface of the substrate and arranged around the edge of the substrate, wherein the guard ring structure comprises an inner ring and an outer ring, and wherein the guard ring structure further comprises a pressure dispersion structure, wherein the pressure dispersion structure comprises a pressure dispersion unit, wherein the pressure dispersion unit is disposed on the substrate and connected between the inner ring and the outer ring.

[0007] According to an exemplary embodiment of the present invention, the pressure dispersion structure includes a plurality of the pressure dispersion units, and the plurality of the pressure dispersion units are disposed between the inner ring and the outer ring at intervals along a circumferential path of the protection ring structure.

[0008] According to an exemplary embodiment of the present invention, the chip has a plurality of corner portions, and the surrounding path of the protective ring structure has a plurality of first segments and a plurality of second segments, the plurality of first segments respectively correspond to a plurality of side edges of the chip, and the plurality of second segments respectively correspond to the plurality of corner portions; wherein the plurality of pressure dispersion units are divided into a plurality of first unit groups and a plurality of second unit groups, the plurality of first unit groups are respectively distributed in the plurality of first segments of the protective ring structure, and the plurality of second unit groups are respectively distributed in the plurality of second segments of the protective ring structure.

[0009] According to an exemplary embodiment of the present invention, the number of the pressure dispersion units in each of the first unit groups is multiple, and they are distributed at intervals along the extension direction of the first segment of the protective ring structure; and / or, the number of the pressure dispersion units in each of the second unit groups is multiple, and they are distributed at intervals along the extension direction of the second segment of the protective ring structure.

[0010] According to an exemplary embodiment of the present invention, the outer ring is provided with a first interconnection layer structure and a first plug layer structure, the first interconnection layer structure is provided on a side of the first plug layer structure away from the substrate surface, and the inner ring is provided with a second interconnection layer structure and a second plug layer structure, the second interconnection layer structure is provided on a side of the second plug layer structure away from the substrate surface; wherein at least one of the pressure dispersion units includes: a third interconnection layer structure, connected between the first interconnection layer structure and the second interconnection layer structure; a third plug layer structure, connected between the first plug layer structure and the second plug layer structure; the first interconnection layer structure, the second interconnection layer structure and the third interconnection layer structure form an interconnection body; the first plug layer structure, the second plug layer structure and the third plug layer structure form a plug body.

[0011] According to an exemplary embodiment of the present invention, the pressure dispersion structure includes a plurality of the pressure dispersion units, and the plurality of the pressure dispersion units are arranged between the inner ring and the outer ring at intervals along the circumferential path of the protective ring structure; wherein the plurality of the pressure dispersion units include: a first pressure dispersion unit, including the third interconnect layer structure and the third plug layer structure; and a second pressure dispersion unit, including the third interconnect layer structure and a plurality of the third plug layer structures, and the plurality of the third plug layer structures are connected between the first plug layer structure of the outer ring and the second plug layer structure of the inner ring.

[0012] According to an exemplary embodiment of the present invention, the chip has multiple corners, and the surrounding path of the protective ring structure has multiple first segments and multiple second segments, the multiple first segments respectively correspond to the multiple side edges of the chip, and the multiple second segments respectively correspond to the multiple corners; wherein the multiple pressure dispersion units are divided into multiple first unit groups and multiple second unit groups, the multiple first unit groups are respectively distributed in the multiple first segments of the protective ring structure, and the multiple second unit groups are respectively distributed in the multiple second segments of the protective ring structure; each of the first unit groups includes at least one first pressure dispersion unit or at least one second pressure dispersion unit; and each of the second unit groups includes at least one second pressure dispersion unit or at least one first pressure dispersion unit.

[0013] According to an exemplary embodiment of the present invention, the chip has multiple corners, and the surrounding path of the protective ring structure has multiple first segments and multiple second segments, the multiple first segments respectively correspond to the multiple side edges of the chip, and the multiple second segments respectively correspond to the multiple corners; wherein the multiple pressure dispersion units are divided into multiple first unit groups and multiple second unit groups, the multiple first unit groups are respectively distributed in the multiple first segments of the protective ring structure, and the multiple second unit groups are respectively distributed in the multiple second segments of the protective ring structure; each of the first unit groups includes at least one first pressure dispersion unit and at least one second pressure dispersion unit; each of the second unit groups includes at least one first pressure dispersion unit and / or at least one second pressure dispersion unit.

[0014] According to an exemplary embodiment of the present invention, the chip has multiple corners, and the surrounding path of the protective ring structure has multiple first segments and multiple second segments, the multiple first segments respectively correspond to the multiple side edges of the chip, and the multiple second segments respectively correspond to the multiple corners; wherein the multiple pressure dispersion units are divided into multiple first unit groups and multiple second unit groups, the multiple first unit groups are respectively distributed in the multiple first segments of the protective ring structure, and the multiple second unit groups are respectively distributed in the multiple second segments of the protective ring structure; each of the first unit groups includes at least one first pressure dispersion unit or at least one second pressure dispersion unit; each of the second unit groups includes at least one first pressure dispersion unit and at least one second pressure dispersion unit.

[0015] According to an exemplary embodiment of the present invention, in the second pressure dispersion unit, a distance between two adjacent third plug layer structures is smaller than a distance between two adjacent third plug layer structures in the first pressure dispersion unit.

[0016] According to an exemplary embodiment of the present invention, the interconnectors and the plug bodies are the same in number and are plural in number, and the interconnectors and the plug bodies are alternately arranged in a direction perpendicular to the surface of the substrate.

[0017] According to an exemplary embodiment of the present invention, the guard ring structure is electrically connected to a P-type well of the substrate.

[0018] According to another aspect of the present invention, there is provided an electronic device comprising the chip as described in the above embodiment.

[0019] It can be seen from the above technical solution that the present invention has at least one of the following advantages and positive effects:

[0020] By setting a pressure dispersion structure in the protection ring structure, and the pressure dispersion structure includes a pressure dispersion unit, and the pressure dispersion unit is connected between the inner ring and the outer ring of the protection ring structure, the strength of the protection ring structure is significantly improved, thereby improving its pressure resistance, reducing cracks in the chip caused by stress, and greatly reducing the breakage rate of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0022] Figure 1 is a top view of a substrate and a guard ring structure thereof in an exemplary embodiment of the present invention;

[0023] Figure 2 for Figure 1 A cross-sectional view of the substrate and guard ring structure along line AA;

[0024] Figure 3 is a top view of a substrate and a guard ring structure thereof in another exemplary embodiment of the present invention;

[0025] Figure 4 FIG. 4 is a top view of a substrate and a guard ring structure thereof in another exemplary embodiment of the present invention.

[0026] Description of reference numerals:

[0027] 1. substrate; 2. guard ring structure; 21. outer ring; 211. first plug layer structure;

[0028] 212, first interconnect layer structure; 22, inner ring; 221, second plug layer structure;

[0029] 222, second interconnection layer structure; 23, pressure dispersion structure; 231, pressure dispersion unit;

[0030] 231', a first pressure dispersion unit; 231", a second pressure dispersion unit;

[0031] 2311', 2311", a third interconnect layer structure; 2312', 2312", a third plug layer structure;

[0032] 24. Circumferential path; 241. First segment; 242. Second segment. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0034] Although relative terms such as "top", "bottom", "upper", "lower", "inside" and "outside" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification for convenience only. If the device of the illustration is turned over so that it is upside down, the component described as being "on" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure. The terms "a", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0035] like Figures 1 to 4 , which representatively shows a chip and a guard ring structure disposed thereon in an embodiment of the present invention. Figure 1 , Figure 3 and Figure 4 The top view of the substrate and its guard ring structure in different embodiments is representatively shown. Figure 2 Representatively shown Figure 1 Cross-sectional view of the guard ring structure in FIG.

[0036] The chip in the embodiment of the present invention can be taken as an example of a semiconductor chip, in which an integrated circuit is arranged at the central position of the semiconductor chip, and the guard ring structure 2 is electrically connected to the P-type well of the semiconductor chip and surrounds the integrated circuit, adjacent to the edge of the semiconductor chip. The guard ring structure 2 is formed in the process of forming the semiconductor chip, and is generally formed by an interconnect layer metal and a plug layer metal. When the semiconductor chip has not been cut, the guard ring structure 2 is formed at the edge adjacent to the cutting line to resist the pressure stress generated by the chip cutting, thereby protecting the internal integrated circuit and other structures, and avoiding stress cracks in the substrate and the integrated circuit. Of course, the above-mentioned chip is not limited to semiconductor chips, but can also be other electronic chips, which are not limited here.

[0037] The traditional chip protection ring structure includes an inner ring and an outer ring to form a double-layer protection structure. However, in actual applications, it is found that although the double-layer protection structure is used, it only has the effect of resisting pressure to a certain extent. If the pressure increases slightly during the cutting or packaging process, at least one layer of the double-layer protection structure will be damaged. Once one of the layers (inner ring or outer ring) is damaged, the protection ability of the other layer will be greatly weakened and it is also easy to be damaged, which will cause damage to the integrated circuit inside the chip, greatly reducing the performance and life of the entire chip.

[0038] like Figure 1 As shown, an embodiment of the present invention provides a chip, including a substrate 1 and a guard ring structure 2. The guard ring structure 2 is disposed on the surface of the substrate 1 and is arranged around the edge of the substrate 1. The guard ring structure 2 includes an inner ring 22 and an outer ring 21. In addition, the guard ring structure 2 also includes a pressure dispersion structure 23, and the pressure dispersion structure 23 includes a pressure dispersion unit 231. The pressure dispersion unit 231 is disposed on the substrate 1 and connected between the inner ring 22 and the outer ring 21.

[0039] In some embodiments of the present invention, Figure 1 As shown, the pressure dispersion structure 23 includes a plurality of pressure dispersion units 231 , which are arranged between the inner ring 22 and the outer ring 21 at intervals along the circumferential path 24 of the protection ring structure 2 .

[0040] It should be noted that the inner ring 22 and the outer ring 21 each form a closed loop, and the circumferential path 24 of the protective ring structure 2 can be a closed loop area between the inner ring 22 and the outer ring 21. For a more vivid understanding, it can be a path trace starting from a certain point in the closed loop area between the inner ring 22 and the outer ring 21, moving clockwise or counterclockwise until moving to the point again.

[0041] The substrate 1 may be a silicon substrate or a germanium substrate, on which a plurality of semiconductor devices may be formed. Those skilled in the art will be able to know the semiconductor devices not involved in the embodiments of the present invention. Therefore, in order to make the drawings more clearly expressed, the semiconductor devices not involved in the embodiments of the present invention are not shown in the drawings. In some embodiments of the present invention, such as Figure 1 As shown, the chip has multiple corners, and the surrounding path 24 of the protection ring structure 2 has multiple first sections 241 and multiple second sections 242. The multiple first sections 241 correspond to multiple side edges of the chip respectively, and the multiple second sections 242 correspond to multiple corners respectively.

[0042] It should be noted that the chip in this embodiment is a rectangle, and the corners are the four corners of the rectangle. In addition, the chip can also be other shapes, such as triangles, pentagons, hexagons or other polygons, which are not limited here. Since the stress on the corners of the chip is more concentrated, in this embodiment, the part of the protection ring corresponding to the corner of the chip is cut to increase the force area of ​​the position of the protection ring structure 2 corresponding to the corner, disperse the stress here, and improve the pressure resistance of the protection ring structure 2.

[0043] In addition, in this embodiment, the first section 241 is in a straight line, the second section 242 is in a straight line, and two adjacent first sections 241 are connected by a second section 242. Since the chip in this embodiment is rectangular, the shape of the guard ring structure 2 is an octagon. Of course, the first section 241 and the second section 242 can also be arcs or other curves. The skilled person can choose according to the specific process of chip preparation, which is not limited here. The extension direction of the first section 241 is the length direction of the first section 241. Figure 1 In the embodiment of the present invention, the extension direction is parallel to the side of the substrate 1 corresponding to the first section 241. The extension direction of the second section 242 is the length direction of the second section 241. Figure 1 As shown, the multiple pressure dispersion units 231 are grouped. In some embodiments, the multiple pressure dispersion units 231 can be divided into multiple first unit groups and multiple second unit groups. The pressure dispersion units 231 of the multiple first unit groups are respectively distributed in the multiple first sections 241 of the protection ring structure 2, and the pressure dispersion units 231 of the multiple second unit groups are respectively distributed in the multiple second sections 242 of the protection ring structure 2.

[0044] In some embodiments of the present invention, the number of pressure dispersion units 231 in each first unit group may be at least one, and the number of pressure dispersion units 231 in each second unit group may be at least one. When the number is one, all of them are arranged in the corresponding first section 241 and second section 242. When the number is multiple, the multiple pressure dispersion units 231 are spaced apart and distributed along the extension direction of the first section 241 and the second section 242 of the protective ring structure 2.

[0045] Through the above design, a plurality of pressure dispersion units 231 are arranged in the surrounding path 24 of the protective ring structure 2, which can strengthen the connection between the inner ring 22 and the outer ring 21, reinforce the inner ring 22 and the outer ring 21 of the protective ring structure 2, and realize proper dispersion of pressure, thereby improving the pressure resistance of the protective ring structure 2.

[0046] In some embodiments, Figure 1 As shown, the outer ring 21 and the inner ring 22 have the same structure, both including an interconnection layer structure and a plug layer structure. Specifically, the outer ring 21 is provided with a first interconnection layer structure 212 and a first plug layer structure 211, wherein the first interconnection layer structure 212 is provided on a side of the first plug layer structure 211 away from the surface of the substrate, and the inner ring 22 is provided with a second interconnection layer structure 222 and a second plug layer structure 221, wherein the second interconnection layer structure 222 is provided on a side of the second plug layer structure 221 away from the surface of the substrate 1. In some embodiments, as Figure 1 As shown, at least one pressure dispersion unit 231 includes a third interconnect layer structure and a third plug layer structure. Among them, the third interconnect layer structure is connected between the first interconnect layer 212 of the outer ring 21 and the second interconnect layer 222 of the inner ring 22. Specifically, it is connected between the inner surface of the outer ring 21 and the outer surface of the inner ring 22. The third plug layer structure connects the first plug layer structure 211 of the outer ring 21 and the second plug layer structure 221 of the inner ring 22. Specifically, both ends of the third plug layer structure can extend into the interior of the first plug layer structure 211 and the second plug layer structure 221. The specific size is determined according to the preparation process of the chip and is not limited here. The above-mentioned first interconnect layer structure, the second interconnect layer structure and the third interconnect layer structure form a whole, which can be called an interconnect; the above-mentioned first plug layer structure, the second plug layer structure and the third plug layer structure form a whole, which can be called a plug body.

[0047] In some embodiments, the interconnectors and plug bodies in the above embodiments are the same in number and are plural, and the interconnectors and plug bodies are alternately arranged in a direction perpendicular to the surface of the substrate.

[0048] In some embodiments, Figure 2 As shown, the interconnection layer structure and the plug layer structure of the guard ring structure can be arranged in multiple layers in a direction perpendicular to the surface of the substrate 1 . Figure 2Only the structures of the outer ring 21 and the inner ring 22 are shown. The third interconnect layer structure in the pressure dispersion unit has the same number of layers as the first interconnect layer structure 212 and the second interconnect layer structure 222, and the third plug layer structure has the same number of layers as the first plug layer structure 211 and the second plug layer 221.

[0049] It should be noted that the attached Figure 1 , 3 In the top view of FIG. 4, the layout of the interconnection layer structure and the plug layer structure is fully shown, and the blocked part is shown. A person skilled in the art can combine the above-mentioned figures and Figure 2 The specific setting of the protection ring structure of this application can be clarified.

[0050] The first interconnection layer structure 212, the second interconnection layer structure 222 and the third interconnection layer structure in the embodiment of the present invention are made of the same material, which may be metal. The first plug layer structure, the second plug layer structure and the third plug layer structure are made of the same material. For example, they may all be copper, tungsten or other metals, and the material may be selected according to actual needs and is not limited here.

[0051] The process for forming the above interconnect layer structure and plug layer structure is a relatively mature technology in semiconductor process. Those skilled in the art are familiar with the process and can implement it, and will not be described in detail here.

[0052] It should be noted that, in the embodiment of the present invention, "inside" further refers to a position close to the center of the chip, and "outside" refers to a position close to the edge of the chip. For example, the inner ring 22 is located inside the outer ring 21, and the inner ring 22 is located outside the center of the chip. Figures 1 to 3 As shown, the outer surface of the inner ring 22 is opposite to the inner surface of the outer ring 21 .

[0053] In some embodiments, the pressure dispersion structure 23 includes a plurality of pressure dispersion units 231, and the plurality of pressure dispersion units 231 may include a first pressure dispersion unit 231' and a second pressure dispersion unit 231" with different structures. Figure 1 As shown, the first pressure dispersion unit 231' may include a third interconnected layer structure in the above embodiment, the third interconnected layer structure is connected between the first interconnected layer structure 212 of the outer ring 21 and the second interconnected layer structure 222 of the inner ring 22. Figures 1 to 4In the embodiment, the third interconnected layer structure of the first pressure dispersion unit 231' is marked as 2311'; in addition, the first pressure dispersion unit 231' also includes a third plug layer structure 2312' in the above embodiment, and the third plug layer structure 2312' connects the first plug layer structure 211 of the outer ring 21 and the second plug layer structure 221 of the inner ring 22. The second pressure dispersion unit 231" may include a third interconnected layer structure 2311" in the above embodiment, and the third interconnected layer structure 2311" is connected between the first interconnected layer structure 212 of the outer ring 21 and the second interconnected layer structure 222 of the inner ring 22, except that , the third interconnection layer structure 2311" has a larger size along the extension direction of the surrounding path 24. The second pressure dispersion unit 231" may also include a plurality of third plug layer structures 2312" in the above embodiment, wherein the plurality of third plug layer structures 2312" are connected to the third plug layer structure 2312" between the first plug layer structure 211 of the outer ring 21 and the second plug layer structure 221 of the inner ring 22. A third interconnection layer structure 2311" in the second pressure dispersion unit 231" is provided with a plurality of third plug layer structures 2312". This design makes the preparation process simpler and enables the distribution of the third plug layer structure to be denser to share more pressure.

[0054] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the third interconnect layer structure and the third plug layer structure are respectively perpendicular to the extension direction of each segment of the surrounding path 24, thereby vertically connecting the inner ring 22 and the outer ring 21. Such a design makes the stress distribution more uniform. Of course, it can also be connected to the inner ring 22 and the outer ring 21 at other angles, which is not limited here.

[0055] In some embodiments, the material of the third interconnected layer structure in the first pressure dispersion unit 231' and the second pressure dispersion unit 231" is the same as the material of the first interconnected layer structure 212 in the outer ring 21 and the second interconnected layer structure 222 in the inner ring 22, and the material of the third plug layer structure is the same as the material of the filler in the first plug layer structure 211 of the outer ring 21 and the second plug layer structure 221 of the inner ring 22. As a result, it can be formed once in the process without changing the material, reducing the complexity of the process.

[0056] In some embodiments, Figure 3 and Figure 4As shown, each first unit group may include at least one first pressure dispersion unit 231' or at least one second pressure dispersion unit 231", and each second unit group may include at least one second pressure dispersion unit 231" or at least one first pressure dispersion unit 231'. That is, in the surrounding path 24 of the protection ring structure 2, the pressure dispersion units 231 in each first segment 241 corresponding to the side of the substrate 1 have the same structure, and the pressure dispersion units 231 in each second segment 242 corresponding to the corner of the substrate 1 have the same structure.

[0057] In some embodiments, each first unit group may include at least one first pressure dispersion unit 231' and at least one second pressure dispersion unit 231"; each second unit group may include at least one first pressure dispersion unit 231' or at least one second pressure dispersion unit 231".

[0058] In some embodiments, each first unit group may include at least one first pressure dispersion unit 231' and at least one second pressure dispersion unit 231"; each second unit group may also include at least one first pressure dispersion unit 231' and at least one second pressure dispersion unit 231".

[0059] In some embodiments, each first unit group includes at least one first pressure dispersion unit 231 ′ or at least one second pressure dispersion unit 231 ″; each second unit group includes at least one first pressure dispersion unit 231 ′ and at least one second pressure dispersion unit 231 ″.

[0060] In some embodiments, Figure 1 , 3 As shown in Figures 4 to 5, the interval between the third plug layer structures 2312' of two adjacent first pressure dispersion units 231' is assumed to be d1, and in the second pressure dispersion unit 231", the interval between the two adjacent third plug layer structures 2312" is assumed to be d2, then d2<d1. In some embodiments, according to the minimum design rules in the chip production process (the minimum design rules are different for different chips and preparation processes, and those skilled in the art can obtain them based on the common sense in the field, which will not be repeated here), a minimum distance d is specified in different chip production processes. In a second pressure dispersion unit 231", the interval between two adjacent third plug layer structures 2312" can be 1 to 2 times the minimum distance d, and the interval between the third plug layer structures 2312' of two adjacent first pressure dispersion units 231' can be 3 to 6 times the minimum distance d. Those skilled in the art can make appropriate adjustments based on the process requirements, which are not limited here.

[0061] In the above embodiment, the second pressure dispersion unit 231" may be disposed at a position that is subjected to greater pressure. For example, the second pressure dispersion unit 231" is generally disposed at a corner of the chip, so that the density of the third plug layer structure 2312" is greater, thereby bearing more pressure and protecting the chip from being easily damaged. Of course, depending on the process, the second pressure dispersion unit 231" may also be disposed at other positions of the chip, such as where the first section 241 is subjected to greater pressure.

[0062] In the above embodiment, the intervals between the first pressure dispersion units 231' of the first section 241 and the second section 242 can be the same, the number of pressure dispersion units 231 of the multiple first unit groups can be the same, and the multiple pressure dispersion units 231 are arranged in parallel and evenly spaced. The number of pressure dispersion units 231 of the multiple second unit groups can be the same, and the multiple pressure dispersion units 231 are arranged in parallel and evenly spaced. The above uniform arrangement can not only share the pressure stress more evenly, but also make the pressure on the chip more even, avoiding local damage.

[0063] In summary, in the implementation of the present invention, a pressure dispersion structure 23 is set in the protective ring structure 2, and the pressure dispersion structure 23 includes a pressure dispersion unit 231, and the pressure dispersion unit 231 is connected between the inner ring 22 and the outer ring 21 of the protective ring structure 2, thereby significantly improving the strength of the protective ring structure 2, thereby improving its pressure resistance, avoiding damage to the internal structure of the chip, reducing cracks in the chip caused by stress, and greatly reducing the breakage rate of the chip.

[0064] According to another aspect of the present invention, an embodiment of the present invention further provides an electronic device, comprising the chip in the above embodiment.

[0065] It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A chip, comprising a substrate and a guard ring structure, wherein the guard ring structure is disposed on the surface of the substrate and surrounds the edge of the substrate, and the guard ring structure comprises an inner ring and an outer ring, wherein: The protection ring structure further includes a pressure dispersion structure, wherein the pressure dispersion structure includes a pressure dispersion unit, and the pressure dispersion unit is disposed on the substrate and connected between the inner ring and the outer ring; The pressure dispersion structure comprises a plurality of the pressure dispersion units, and the plurality of the pressure dispersion units are arranged between the inner ring and the outer ring at intervals along the circumferential path of the protection ring structure; The chip has a plurality of corners, the surrounding path of the protection ring structure has a plurality of first sections and a plurality of second sections, the plurality of first sections respectively correspond to a plurality of side edges of the chip, and the plurality of second sections respectively correspond to a plurality of corners; wherein the plurality of pressure dispersion units are divided into a plurality of first unit groups and a plurality of second unit groups, the plurality of first unit groups are respectively distributed in the plurality of first sections of the protection ring structure, and the plurality of second unit groups are respectively distributed in the plurality of second sections of the protection ring structure; Wherein, the substrate is a silicon substrate or a germanium substrate.

2. The chip according to claim 1, characterized in that: The number of the pressure dispersion units in each of the first unit groups is multiple and is distributed at intervals along the extension direction of the first section of the protective ring structure; and / or the number of the pressure dispersion units in each of the second unit groups is multiple and is distributed at intervals along the extension direction of the second section of the protective ring structure.

3. A chip, comprising a substrate and a guard ring structure, wherein the guard ring structure is disposed on the surface of the substrate and surrounds the edge of the substrate, and the guard ring structure comprises an inner ring and an outer ring, wherein: The protection ring structure further includes a pressure dispersion structure, wherein the pressure dispersion structure includes a pressure dispersion unit, and the pressure dispersion unit is disposed on the substrate and connected between the inner ring and the outer ring; The outer ring is provided with a first interconnect layer structure and a first plug layer structure, wherein the first interconnect layer structure is provided on a side of the first plug layer structure away from the substrate surface, and the inner ring is provided with a second interconnect layer structure and a second plug layer structure, wherein the second interconnect layer structure is provided on a side of the second plug layer structure away from the substrate surface; wherein at least one of the pressure dispersion units comprises: a third interconnection layer structure connected between the first interconnection layer structure and the second interconnection layer structure; a third plug layer structure connected between the first plug layer structure and the second plug layer structure; The first interconnect layer structure, the second interconnect layer structure and the third interconnect layer structure form an interconnect body; The first plug layer structure, the second plug layer structure and the third plug layer structure form a plug body; Wherein, the substrate is a silicon substrate or a germanium substrate.

4. The chip according to claim 3, characterized in that: The pressure dispersion structure comprises a plurality of pressure dispersion units, and the plurality of pressure dispersion units are arranged between the inner ring and the outer ring at intervals along the circumferential path of the protective ring structure; wherein the plurality of pressure dispersion units comprise: A first pressure dispersion unit includes the third interconnect layer structure and the third plug layer structure; and The second pressure dispersing unit includes the third interconnect layer structure and a plurality of the third plug layer structures, and the plurality of the third plug layer structures are connected between the first plug layer structure of the outer ring and the second plug layer structure of the inner ring.

5. The chip according to claim 4, characterized in that: The chip has a plurality of corners, the surrounding path of the protection ring structure has a plurality of first sections and a plurality of second sections, the plurality of first sections respectively correspond to the plurality of side edges of the chip, and the plurality of second sections respectively correspond to the plurality of corners; wherein the plurality of pressure dispersion units are divided into a plurality of first unit groups and a plurality of second unit groups, the plurality of first unit groups are respectively distributed in the plurality of first sections of the protection ring structure, and the plurality of second unit groups are respectively distributed in the plurality of second sections of the protection ring structure; Each of the first unit groups includes at least one first pressure dispersion unit or at least one second pressure dispersion unit; and Each of the second unit groups includes at least one second pressure dispersion unit or at least one first pressure dispersion unit.

6. The chip according to claim 5, characterized in that: The chip has a plurality of corners, the surrounding path of the protection ring structure has a plurality of first sections and a plurality of second sections, the plurality of first sections respectively correspond to the plurality of side edges of the chip, and the plurality of second sections respectively correspond to the plurality of corners; wherein the plurality of pressure dispersion units are divided into a plurality of first unit groups and a plurality of second unit groups, the plurality of first unit groups are respectively distributed in the plurality of first sections of the protection ring structure, and the plurality of second unit groups are respectively distributed in the plurality of second sections of the protection ring structure; Each of the first unit groups includes at least one first pressure dispersion unit and at least one second pressure dispersion unit; each of the second unit groups includes at least one first pressure dispersion unit and / or at least one second pressure dispersion unit.

7. The chip according to claim 4, characterized in that: The chip has a plurality of corners, the surrounding path of the protection ring structure has a plurality of first sections and a plurality of second sections, the plurality of first sections respectively correspond to the plurality of side edges of the chip, and the plurality of second sections respectively correspond to the plurality of corners; wherein the plurality of pressure dispersion units are divided into a plurality of first unit groups and a plurality of second unit groups, the plurality of first unit groups are respectively distributed in the plurality of first sections of the protection ring structure, and the plurality of second unit groups are respectively distributed in the plurality of second sections of the protection ring structure; Each of the first unit groups includes at least one first pressure dispersion unit or at least one second pressure dispersion unit; each of the second unit groups includes at least one first pressure dispersion unit and at least one second pressure dispersion unit.

8. The chip according to claim 7, characterized in that: In the second pressure dispersion unit, a distance between two adjacent third plug layer structures is smaller than a distance between two adjacent third plug layer structures in the first pressure dispersion unit.

9. The chip according to claim 3, characterized in that: The interconnectors and the plug bodies are provided in the same number and are plural in number. The interconnectors and the plug bodies are alternately arranged in a direction perpendicular to the surface of the substrate.

10. The chip according to claim 1 or 3, characterized in that: The guard ring structure is electrically connected to a P-type well of the substrate.

11. An electronic device, characterized in that: include: A chip as claimed in any one of claims 1 to 10.

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