Stacked packaging structure and packaging method

Abstract

The present invention relates to a stacked packaging structure, comprising a chip, a first dielectric layer arranged on the active surface of the chip; a redistribution layer arranged on the first dielectric layer, the redistribution layer having a first metal layer opening, the first metal layer opening exposing at least a portion of the first dielectric layer; a second dielectric layer arranged on the redistribution layer; a first groove also arranged on the surface of the first dielectric layer, the first groove and the first metal layer opening being interconnected, the second dielectric layer being connected to the first dielectric layer via the first metal layer opening and the first groove. The above arrangement can solve the problem of the current stacked packaging structure being prone to delamination or cracks at the junction of the three-layer stacked structure due to the different expansion or contraction degrees of the structural materials between the redistribution layer and the two dielectric layers during the thermal cycle process and reliability process.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a stacked packaging structure and a packaging method. Background Art

[0002] As the main method of high-density packaging, stacked packaging has received more and more attention. Chip stacking is one of the main ways to improve the high density of electronic packaging. Stacked packaging technology has been widely developed and applied in the industry.

[0003] In the stacked packaging structure of the prior art, a metal layer such as a redistribution layer is arranged between two organic dielectric passivation layers, that is, the redistribution layer covers the first dielectric layer, and the second dielectric layer covers the redistribution layer, forming a three-layer stacked packaging structure.

[0004] During the thermal cycle process and reliability process, the redistribution layer and the two dielectric layers are susceptible to temperature differences and are susceptible to thermal expansion and contraction when cooled. The dielectric layer and the redistribution layer have different thermal expansion coefficients, and the redistribution layer and the two dielectric layers expand or contract to different degrees. The junction of the two structural materials will be subject to stress pulling, so delamination or cracks are prone to occur at the junction of the three-layer stacked packaging structure, that is, delamination or cracks are prone to occur at the junction of the redistribution layer, the first dielectric layer, and the second dielectric layer. Summary of the invention

[0005] The purpose of the present invention is to provide a stacked packaging structure and a packaging method to solve the problem that in the current stacked packaging structure, delamination or cracks are easily generated at the junction of the three-layer stacked structure due to the different degrees of expansion or contraction of the structural materials of the redistribution layer and the two dielectric layers during the thermal cycle process and reliability process.

[0006] In order to achieve one of the above-mentioned purposes of the invention, one embodiment of the present invention provides a stacked packaging structure, including a chip, a first dielectric layer is arranged on the active surface of the chip; a redistribution layer is arranged on the first dielectric layer, and the redistribution layer is provided with a first metal layer opening, and the first metal layer opening exposes at least a portion of the first dielectric layer; a second dielectric layer is arranged on the redistribution layer; a first groove is also opened on the surface of the first dielectric layer, and the first groove is interconnected with the first metal layer opening, and the second dielectric layer is connected to the first dielectric layer via the first metal layer opening and the first groove.

[0007] As a further improvement of an embodiment of the present invention, the width of the first groove is not less than the width of the opening of the first metal layer, and the depth of the first groove exceeds 0.3 um.

[0008] As a further improvement of an embodiment of the present invention, the width of the first groove is equal to the width of the opening of the first metal layer.

[0009] As a further improvement of one embodiment of the present invention, the second dielectric layer is further provided with a second dielectric layer opening, and the second dielectric layer opening exposes at least a portion of the redistribution layer; the packaging structure also includes a solder ball, and the solder ball is electrically connected to the redistribution layer through the second dielectric layer opening.

[0010] As a further improvement of one embodiment of the present invention, the packaging structure also includes an under-ball metal layer arranged between the solder ball and the redistribution layer, the under-ball metal layer electrically connects the solder ball and the redistribution layer via the second dielectric layer opening, and a second metal layer opening is formed on part of the side surface of the under-ball metal layer and the surface of the redistribution layer; a second groove is also opened on the surface of the second dielectric layer.

[0011] As a further improvement of an embodiment of the present invention, the height difference between the bottom surface of the second groove and the upper side surface of the second metal layer opening exceeds 0.3 um.

[0012] As a further improvement of an embodiment of the present invention, the second groove is connected to or at least partially overlaps with the opening of the second metal layer.

[0013] As a further improvement of an embodiment of the present invention, the packaging structure further includes a third dielectric layer disposed above the second dielectric layer, and the third dielectric layer encapsulates the UBM layer.

[0014] One embodiment of the present invention also provides a stacked packaging method, comprising the steps of: setting a first dielectric layer on the active surface of a wafer or a chip; setting a redistribution layer on the first dielectric layer, and opening a first metal layer on the redistribution layer, so that the first metal layer opening exposes at least a portion of the first dielectric layer; opening a first groove on the surface of the first dielectric layer, so that the first groove and the first metal layer opening are interconnected; setting a second dielectric layer on the redistribution layer, so that the second dielectric layer is connected to the first dielectric layer via the first metal layer opening and the first groove.

[0015] As a further improvement of an embodiment of the present invention, the method further includes: a width of the first groove is not less than a width of the first metal layer opening, and a depth of the first groove exceeds 0.3 um.

[0016] As a further improvement of one embodiment of the present invention, the method also includes: opening a second dielectric layer opening on the second dielectric layer so that the second dielectric layer opening exposes at least a portion of the redistribution layer; implanting a solder ball at the second dielectric layer opening so that the solder ball is electrically connected to the redistribution layer.

[0017] As a further improvement of one embodiment of the present invention, the method also includes: setting an under-ball metal layer between the solder ball and the redistribution layer, so that the under-ball metal layer electrically connects the solder ball and the redistribution layer via the second dielectric layer opening, and part of the side surface of the under-ball metal layer and the surface of the redistribution layer are surrounded to form a second metal layer opening.

[0018] As a further improvement of one embodiment of the present invention, the method also includes: opening a second groove on the surface of the second dielectric layer, so that the height difference between the bottom surface of the second groove and the upper side surface of the second metal layer opening exceeds 0.3um, and the second groove is connected to or at least partially overlaps with the second metal layer opening.

[0019] Compared with the prior art, the beneficial effect of the present invention is that by opening a groove on the surface of the first dielectric layer and embedding the second dielectric layer into the first dielectric layer, the contact area between the two dielectric layers is increased and the adhesion between the dielectric layers is increased, thereby resisting the stress between the redistribution layer and the two dielectric layers, and preventing delamination or cracks from occurring at the junction of the redistribution layer and the two dielectric layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic cross-sectional view of a packaging structure in a first embodiment of the present invention;

[0021] Figure 2 is a schematic cross-sectional view of a packaging structure in a second embodiment of the present invention;

[0022] Figure 3 is a schematic cross-sectional view of a packaging structure in a third embodiment of the present invention;

[0023] Figure 4 is a schematic cross-sectional view of a packaging structure in a fourth embodiment of the present invention;

[0024] Figure 5 is a flow chart of a packaging method in a first embodiment of the present invention;

[0025] Figure 6 It is a schematic structural diagram corresponding to each step in the first embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in combination with the specific implementation methods of this application and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0028] like Figures 1 to 3 As shown, an embodiment of the present invention provides a stacked packaging structure, including a chip 9, which can be a silicon chip, or a fan-out type rewiring substrate, such as a heterogeneous chip composed of eWLB (embedded wafer-level ball grid array) plastic packaging material and silicon. The first dielectric layer 21 is arranged on the active surface 91 of the chip 9; the rewiring layer 4 is arranged on the first dielectric layer 21, and the rewiring layer 4 is provided with a first metal layer opening 41, and the first metal layer opening 41 exposes at least part of the first dielectric layer 21; the second dielectric layer 22 is arranged on the rewiring layer 4; the surface of the first dielectric layer 21 is also provided with a first groove 211, and the first groove 211 is interconnected with the first metal layer opening 41, and the second dielectric layer 22 is connected to the first dielectric layer 21 via the first metal layer opening 41 and the first groove 211.

[0029] In an embodiment of the present invention, the stacked packaging structure is a chip-level packaging, and the packaging structure includes a chip 9 having an active surface 91. The three-layer stacked structure is arranged on the active surface 91 of the chip 9 in the form of layer-by-layer flat stacking, that is, the first dielectric layer 21 is arranged above the active surface 91 of the chip 9, the redistribution layer 4 is arranged above the first dielectric layer 21, and the second dielectric layer 22 is arranged above the redistribution layer 4, forming a three-layer structure.

[0030] The redistribution layer 4 is a metal layer. In order to realize line routing, the redistribution layer 4 is provided with a first metal layer opening 41. The first metal layer opening 41 penetrates the redistribution layer 4 along the material thickness direction, exposing at least part of the surface of the first dielectric layer 21; the second dielectric layer 22 can pass through or penetrate the first metal layer opening 41 and be interconnected with the first dielectric layer 21 below.

[0031] Since the thermal expansion coefficients of the dielectric layer and the redistribution layer 4 are different, and the first dielectric layer 21 and the second dielectric layer 22 may be made of different materials, or the thickness and area of ​​the two dielectric layers are also different, the three-layer structure is susceptible to thermal expansion and contraction during the thermal cycle process, and the junction of the three-layer structure at the boundary of the first metal layer opening 41 is susceptible to stress pulling, resulting in delamination or cracking of the three-layer structure. For this reason, a first groove 211 is opened on the surface of the first dielectric layer 21, and the second dielectric layer 22 can continue to pass through the first groove 211 downward after passing through the first metal layer opening 41, and finally connect with the first dielectric layer 21; that is, the second dielectric layer 22 at least partially enters or is embedded in the first dielectric layer 21. As a result, the contact area between the two dielectric layers is increased, and the adhesion between the two is improved, which can resist the stress between the redistribution layer 4, thereby preventing delamination or cracking and improving reliability.

[0032] At the same time, in order to achieve functional system interconnection, a metal pad 95 and a protective layer 93 may be provided on the active surface 91 of the chip 9, and the metal pad 95 is exposed outside the protective layer 93; the first dielectric layer 21 is also provided with an opening for exposing at least part of the metal pad 95; the redistribution layer 4 is electrically connected to the metal pad 95 through this opening, so that the redistribution layer 4 and the chip 9 are electrically connected to each other.

[0033] The first dielectric layer 21 can be disposed on the active surface 91 of the chip 9 by coating or other processes. The material is not limited and can be benzocyclobutene (BCB) or polyimide (PI), or other polymer dielectric materials and polymer dielectric materials with fillers.

[0034] The redistribution layer 4 can be disposed on top of the first dielectric layer 21 by sputtering or electroplating. The material of the redistribution layer 4 can be titanium, TiW, copper, gold and metal alloys, or a single-layer or multi-layer structure of metals such as titanium, TiW, copper, nickel and gold alloys, such as 200-1000A Ti and 2-30um Cu.

[0035] The second dielectric layer 22 can also be processed by coating or other processes to be disposed on the redistribution layer 4 and the exposed surface of the first dielectric layer 21 .

[0036] The processing form of the first metal layer opening 41 and the first groove 211 is not limited. Part of the redistribution layer 4 and part of the first dielectric layer 21 can be removed by photolithography or laser etching to obtain both the first metal layer opening 41 and the first groove 211. The processing forms of the two can be the same or different.

[0037] In addition, the stacked packaging structure is a wafer-level or board-level packaging, such as a packaging structure including a wafer, the wafer having an active surface 91, and a three-layer stacked structure arranged on the active surface 91 of the wafer in a layer-by-layer flat stacking form. Among them, the chip 9 can be a silicon chip, or a fan-out type rewiring substrate, such as an eWLB (embedded wafer-level ball grid array) heterogeneous chip composed of plastic packaging material and silicon.

[0038] Furthermore, the width of the first groove 211 is not less than the width of the first metal layer opening 41 , and the depth of the first groove 211 exceeds 0.3 um.

[0039] Furthermore, the width of the first groove 211 is equal to the width of the first metal layer opening 41 .

[0040] Specifically, to increase the contact area between the two dielectric layers, the depth of the first groove 211 can be set to be greater than 0.3 um, so that the nested portion between the first dielectric layer 21 and the second dielectric layer 22 is as large as possible. It has been verified through actual experiments that setting the embedding depth to be greater than 0.3 um can effectively avoid delamination.

[0041] At the same time, the width of the first groove 211 is widened so that the boundary of the first groove 211 can be aligned with the first metal layer opening 41, or the boundary of the first groove 211 is located below the redistribution layer 4; Figure 2 As shown, preferably, for the convenience of processing, the boundary of the first groove 211 can be aligned with the first metal layer opening 41, and both can be formed by laser or etching at the same time.

[0042] As a result, the two dielectric layers are nested with each other, the contact area is greatly increased, and the adhesion is improved, which can resist the stress between the redistribution layer 4 and prevent delamination or cracks.

[0043] Furthermore, the second dielectric layer 22 is also provided with a second dielectric layer opening 221 , which exposes at least a portion of the redistribution layer 4 ; the packaging structure also includes a solder ball 8 , which is electrically connected to the redistribution layer 4 through the second dielectric layer opening 221 .

[0044] In order to electrically connect other external circuits, such as a circuit board (PCB), a chip 9 or other semiconductor packages, a solder ball 8 may be disposed above the second dielectric layer 22 in the packaging structure to electrically connect the solder ball 8 to the redistribution layer 4 .

[0045] Specifically, the second dielectric layer 22 is provided with a second dielectric layer opening 221, which penetrates the second dielectric layer 22 along the material thickness direction, exposing at least a portion of the surface of the redistribution layer 4; the solder ball 8 can pass through or penetrate the second dielectric layer opening 221 and be electrically connected to the underlying redistribution layer 4. The solder ball 8 can be implanted in the second dielectric layer opening 221 and directly contact the redistribution layer 4, or contact the redistribution layer 4 through the metal layer 6 under the ball.

[0046] Furthermore, the packaging structure also includes a under-ball metal layer 6 arranged between the solder ball 8 and the redistribution layer 4, and the under-ball metal layer 6 electrically connects the solder ball 8 and the redistribution layer 4 via the second dielectric layer opening 221. Part of the side surfaces of the under-ball metal layer 6 and the surface of the redistribution layer 4 are surrounded by a second metal layer opening 62; the surface of the second dielectric layer 22 is also provided with a second groove 222.

[0047] Furthermore, the height difference between the bottom surface of the second groove 222 and the upper side surface of the second metal layer opening 62 exceeds 0.3 um.

[0048] Furthermore, the second groove 222 is connected to or at least partially overlaps with the second metal layer opening 62 .

[0049] like Figure 3 As described above, in order to facilitate soldering of the solder ball 8, an under-ball metal layer 6 can be formed in the second dielectric layer opening 221. After the under-ball metal layer 6 passes through or through the second dielectric layer opening 221, it is electrically connected to the underlying redistribution layer 4. Then, metal solder balls such as solder balls 8 are formed above the under-ball metal layer 6, so that the solder balls 8 are electrically connected to the under-ball metal layer 6. As a result, the exposed area of ​​the metal circuit of the redistribution layer 4 is increased, the solder ball 8 is convenient to solder, and the electrical connection with the redistribution layer 4 is reliable.

[0050] When the UBM layer 6 is provided, the second dielectric layer 22 is located below the UBM layer 6 and is embedded with the UBM layer 6. Stress caused by thermal expansion and contraction also exists between the UBM layer 6 and the second dielectric layer 22. To improve this situation, a second groove 222 may be provided on the surface of the second dielectric layer 22 to reduce the material weight of the second dielectric layer 22.

[0051] Preferably, part of the second dielectric layer 22 is removed, and a second groove 222 with a depth exceeding 0.3 um is formed on its surface to reduce the material weight of the second dielectric layer 22; at the same time, the boundary of the second groove 222 can be flush with the boundary of the metal layer 6 under the ball to facilitate processing; or the second groove 222 enters under the metal layer 6 under the ball, so that the hollowing area of ​​the second groove 222 on the surface of the second dielectric layer 22 is as large as possible, and the contact area between the second dielectric layer 22 and the metal layer 6 under the ball is as small as possible, thereby maximally alleviating the stress effect and change of stress direction caused by thermal expansion and contraction of different materials, preventing delamination or cracks, and improving reliability.

[0052] Furthermore, the packaging structure further includes a third dielectric layer 23 disposed above the second dielectric layer 22 , and the third dielectric layer 23 encapsulates the UBM layer.

[0053] In order to further improve the reliability of the overall packaging structure, a third dielectric layer 23 is provided to encapsulate the UBM under ball metallization layer 6, and wrap the exposed UBM under ball metallization layer 6. The third dielectric layer 23 may be an island structure covering the UBM under ball metallization layer 6, and may be opened along the side of the UBM under ball metallization layer 6, such as the cross-sectional shape of the third dielectric layer 23 may be a ring or a square with chamfered corners.

[0054] In this way, the durability and endurance of the overall packaging structure are improved, and the reliability is enhanced; the independent third dielectric layer 23 protects the single UBM metal layer 6, which can alleviate the deformation of the UBM metal layer 6 due to thermal expansion and contraction, and prevent the warping of the wafer and the package body.

[0055] For easier understanding, the following example is described in detail:

[0056] Example 1

[0057] like Figure 1 As shown, the active surface 91 of the chip 9 is provided with a three-layer stacked structure. A metal pad 95 and a protective layer 93 are also provided on the active surface 91 , and the metal pad 95 is exposed outside the protective layer 93 .

[0058] The first dielectric layer 21 is disposed above the active surface 91 of the chip 9 ; the first dielectric layer 21 is also provided with an opening to expose at least a portion of the metal pad 95 .

[0059] The redistribution layer 4 is arranged above the first dielectric layer 21; the redistribution layer 4 is electrically connected to the exposed portion of the metal pad 95 through the opening set in the first dielectric layer 21; the redistribution layer 4 is provided with a first metal layer opening 41, and the first metal layer opening 41 penetrates the redistribution layer 4 along the material thickness direction to expose at least part of the surface of the first dielectric layer 21.

[0060] The surface of the first dielectric layer 21 is further provided with a first groove 211 , which is connected to the first metal layer opening 41 , and has a width greater than that of the first metal layer, that is, a boundary of the first groove 211 extends below the redistribution layer 4 .

[0061] The second dielectric layer 22 is arranged above the redistribution layer 4; a second dielectric layer opening 221 is opened on the second dielectric layer 22 to expose at least part of the surface of the redistribution layer 4; a solder ball 8 is provided at the position of the second dielectric layer opening 221, and the solder ball 8 is welded and fixed to the redistribution layer 4 to achieve electrical connection.

[0062] Example 2

[0063] like Figure 2 As shown, similarly, the active surface 91 of the chip 9 has a three-layer stacked structure, and a metal pad 95 and a protective layer 93 are also provided on the active surface 91 , and the metal pad 95 is exposed outside the protective layer 93 .

[0064] Different from the first embodiment, in this embodiment, the first groove 211 and the first metal layer are of equal width, that is, the boundary of the first groove 211 is flush with the boundary of the first metal layer, and both can be formed by laser or etching at the same time, which is convenient and simple to process.

[0065] Example 3

[0066] like Figure 3 As shown, similarly, the active surface 91 of the chip 9 has a three-layer stacked structure, and a metal pad 95 and a protective layer 93 are also provided on the active surface 91 , and the metal pad 95 is exposed outside the protective layer 93 .

[0067] Different from the first embodiment, in this embodiment, an UBM layer 6 is formed in the second dielectric layer opening 221 . After passing through the second dielectric layer opening 221 , the UBM layer 6 is electrically connected to the underlying redistribution layer 4 .

[0068] A metal solder ball such as a solder ball 8 is formed by soldering above the UBM layer 6 , so that the solder ball 8 is electrically connected to the UBM layer 6 .

[0069] Example 4

[0070] like Figure 4 As shown, similarly, the active surface 91 of the chip 9 has a three-layer stacked structure, and a metal pad 95 and a protective layer 93 are also provided on the active surface 91 , and the metal pad 95 is exposed outside the protective layer 93 .

[0071] Different from the third embodiment, in this embodiment, a third dielectric layer 23 encapsulating the UBM under ball metallization layer 6 is provided above the second dielectric layer 22 to encapsulate the exposed UBM under ball metallization layer 6. The third dielectric layer 23 is an island structure covering the UBM under ball metallization layer 6 and is opened along the side of the UBM under ball metallization layer 6. For example, the cross-sectional shape of the third dielectric layer 23 is a ring or a square with chamfered corners.

[0072] like Figure 5 As shown, an embodiment of the present invention further provides a stacking packaging method, which includes the following steps, which are specifically described below:

[0073] S2: disposing the first dielectric layer 21 on the active surface 91 of the wafer or chip 9;

[0074] S4: disposing a redistribution layer 4 on the first dielectric layer 21, and opening a first metal layer opening 41 on the redistribution layer 4, so that the first metal layer opening 41 exposes at least a portion of the first dielectric layer 21;

[0075] S6: opening a first groove 211 on the surface of the first dielectric layer 21, so that the first groove 211 is connected to the first metal layer opening 41;

[0076] S8 : disposing the second dielectric layer 22 on the redistribution layer 4 , so that the second dielectric layer 22 is connected to the first dielectric layer 21 via the first metal layer opening 41 and the first groove 211 .

[0077] In the embodiment of the present invention, the packaging structure is a wafer-level packaging or a chip-level packaging, and the wafer or chip 9 is provided with an active surface 91 .

[0078] First, the first dielectric layer 21 is disposed on the active surface 91 of the chip 9 by coating or other processes. Then, the redistribution layer 4 is disposed on the first dielectric layer 21 by sputtering or electroplating or other methods; and a first metal layer opening 41 is opened on the redistribution layer 4, and the first metal layer opening 41 penetrates the redistribution layer 4 along the material thickness direction, exposing at least part of the surface of the first dielectric layer 21; at the same time, a first groove 211 is also opened on the surface of the first dielectric layer 21, and the first groove 211 can be processed together with the first metal layer opening 41 by lithography or laser etching or other methods; then, the second dielectric layer 22 is disposed on the redistribution layer 4 by coating or other processes; the second dielectric layer 22 can enter the first dielectric layer 21 below after passing through the first metal layer opening 41 and the first groove 211, that is, the first dielectric layer 21 and the second dielectric layer 22 are mutually nested and connected. The first dielectric layer 21 and the second dielectric layer 22 may be made of different materials, or the thickness and area of ​​the two dielectric layers may be different.

[0079] Further, for step S6, the method specifically includes:

[0080] The width of the first groove 211 is not less than the width of the first metal layer opening 41 , and the depth of the first groove 211 exceeds 0.3 um.

[0081] To increase the contact area between the two dielectric layers, the depth of the first groove 211 is set to be greater than 0.3 um, and the width of the first groove 211 is widened so that the boundary of the first groove 211 is aligned with the first metal layer opening 41, or the boundary of the first groove 211 is located below the redistribution layer 4.

[0082] Furthermore, after step S8, the method further includes:

[0083] S91: opening a second dielectric layer opening 221 on the second dielectric layer 22, so that the second dielectric layer opening 221 exposes at least a portion of the redistribution layer 4;

[0084] S93 implants a solder ball 8 in the second dielectric layer opening 221 , so that the solder ball 8 is electrically connected to the redistribution layer 4 .

[0085] Further, for step S93, the method specifically includes:

[0086] S931 sets an under-ball metal layer 6 between the solder ball 8 and the redistribution layer 4, so that the under-ball metal layer 6 electrically connects the solder ball 8 and the redistribution layer 4 via the second dielectric layer opening 221, and part of the side surface of the under-ball metal layer 6 and the surface of the redistribution layer 4 are surrounded to form a second metal layer opening 62.

[0087] In order to electrically connect other external circuits, a solder ball 8 may be further provided above the second dielectric layer 22. Specifically, a second dielectric layer opening 221 is provided on the second dielectric layer 22, and the second dielectric layer opening 221 penetrates the second dielectric layer 22 along the material thickness direction, exposing at least a portion of the surface of the redistribution layer 4; an under-ball metal layer 6 is formed in the second dielectric layer opening 221, and the under-ball metal layer 6 is electrically connected to the redistribution layer 4 below after passing through or penetrating the second dielectric layer opening 221; and a metal solder ball such as a solder ball 8 is formed above the under-ball metal layer 6, so that the solder ball 8 is electrically connected to the under-ball metal layer 6.

[0088] Further, for step S931, the method specifically includes:

[0089] A second groove 222 is formed on the surface of the second dielectric layer 22 , so that the bottom surface of the second groove 222 and the upper side surface of the second metal layer opening 62 differ in height by more than 0.3 um, and the second groove 222 is connected to or at least partially overlaps with the second metal layer opening 62 .

[0090] After the UBM layer 6 is provided, part of the side surface of the UBM layer 6 and the surface of the redistribution layer 4 surround a second metal layer opening 62 . Stress caused by thermal expansion and contraction also exists between the UBM layer 6 and the second dielectric layer 22 .

[0091] To improve this situation, a second groove 222 may be opened on the surface of the second dielectric layer 22. The depth of the second groove 222 may exceed 0.3 um, and the boundary may be flush with the boundary of the metal layer 6 under the ball, or the second groove 222 may enter under the metal layer 6 under the ball, so that the contact area between the second dielectric layer 22 and the metal layer 6 under the ball is as small as possible, thereby alleviating the stress caused by thermal expansion and contraction of different materials to the greatest extent.

[0092] The following is an overall description of the stacking packaging method:

[0093] In the embodiment of the present invention, Figure 6 As shown, the packaging structure is a wafer-level packaging or a chip-level packaging, and the wafer or chip 9 is provided with an active surface 91. A metal pad 95 and a protective layer 93 are also provided on the active surface 91, and the metal pad 95 is exposed outside the protective layer 93.

[0094] First, the first dielectric layer 21 is disposed on the active surface 91 and the metal pad 95 by coating or other processes. The first dielectric layer 21 is also provided with an opening to expose at least a portion of the metal pad 95 .

[0095] The redistribution layer 4 is then disposed above the first dielectric layer 21 by sputtering or electroplating; the redistribution layer 4 is electrically connected to the exposed portion of the metal pad 95 through the opening disposed in the first dielectric layer 21, so as to be electrically connected to the chip 9.

[0096] Removing a portion of the redistribution layer 4 and a portion of the first dielectric layer 21 by photolithography or laser etching to form a first metal layer opening 41 penetrating the redistribution layer 4 and a first groove 211 located on the surface of the first dielectric layer 21;

[0097] Then, through coating and other processes, the second dielectric layer 22 is set above the redistribution layer 4; a second dielectric layer opening 221 is opened on the second dielectric layer 22 to expose at least part of the surface of the redistribution layer 4; a solder ball 8 is implanted at the position of the second dielectric layer opening 221, so that the solder ball 8 is electrically connected to the redistribution layer 4.

[0098] In summary, the stacked packaging structure provided by the present invention has three stacked structures, namely, a first dielectric layer 21, a redistribution layer 4 and a second dielectric layer 22, which are arranged in sequence above the active surface 91 of the chip 9. By adding a first groove 211 on the surface of the first dielectric layer 21, the first dielectric layer 21 can enter the second dielectric layer 22, and the contact area between the two nested dielectric layers is increased, and the adhesion between the two is improved, which can resist the stress between the redistribution layer 4, thereby preventing delamination or cracks and improving reliability.

[0099] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0100] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A stacking packaging method, characterized in that: The method comprises: Disposing a first dielectric layer on the active surface of the wafer or chip; Disposing a redistribution layer on the first dielectric layer, and opening a first metal layer on the redistribution layer, so that the first metal layer opening exposes at least a portion of the first dielectric layer; After forming the first metal layer opening, opening a first groove on the surface of the first dielectric layer so that the first groove is connected to the first metal layer opening; A second dielectric layer is disposed on the redistribution layer, so that the second dielectric layer is connected to the first dielectric layer through the first metal layer opening and the first groove; at least a portion of the second dielectric layer covers the side edge of the redistribution layer and is embedded in the first dielectric layer.

2. The stacking packaging method according to claim 1, characterized in that: The step of "forming a first groove on the surface of the first dielectric layer" specifically includes: The width of the first groove is not less than the width of the opening of the first metal layer, and the depth of the first groove exceeds 0.3 um.

3. The stacking packaging method according to claim 1, characterized in that: After the step of "arranging a second dielectric layer on the redistribution layer", the method further comprises: Opening a second dielectric layer opening on the second dielectric layer, so that the second dielectric layer opening exposes at least a portion of the redistribution layer; A solder ball is implanted in the opening of the second dielectric layer so that the solder ball is electrically connected to the redistribution layer.

4. The stacking packaging method according to claim 3, characterized in that: The step of "implanting a solder ball at the opening of the second dielectric layer so that the solder ball is electrically connected to the redistribution layer" specifically includes: An under-ball metal layer is arranged between the solder ball and the redistribution layer, so that the under-ball metal layer electrically connects the solder ball and the redistribution layer through the second dielectric layer opening, and part of the side surface of the under-ball metal layer and the surface of the redistribution layer are surrounded to form a second metal layer opening.

5. The stacking packaging method according to claim 4, characterized in that: After the step of "arranging an under ball metal layer between the solder ball and the redistribution layer", the method further comprises: A second groove is formed on the surface of the second dielectric layer, and the second groove is connected to or at least partially overlaps with the opening of the second metal layer.

6. The stacking packaging method according to claim 5, characterized in that: The height difference between the bottom surface of the second groove and the upper side surface of the second metal layer opening exceeds 0.3 um.

7. A stacked packaging structure, characterized in that: The stacked package is manufactured using the stacked package method according to any one of claims 1 to 6.

8. The package-on-package structure according to claim 7, wherein: The packaging structure also includes a third dielectric layer disposed above the second dielectric layer.

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