Integrated chip with junction isolation structure and manufacturing method thereof

Abstract

The present invention provides an integrated chip with a junction isolation structure and a manufacturing method thereof, wherein the integrated chip comprises a substrate and an epitaxial structure. The substrate is provided with a well region, and the well region divides the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in a transverse direction. The substrate comprises an N-type region and a P-type region, and two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the two semiconductor device regions. A first drain, a first gate, and a first source located in the first semiconductor device region and a second drain, a second gate, and a second source located in the second semiconductor region are provided on the upper side of the epitaxial structure, and the first drain or the second source is electrically connected to the well region through a first electrical interconnection. The first source is electrically connected to the N-type region or the P-type region through a second electrical interconnection, and the second drain and the first source are short-circuited. The second source is electrically connected to the N-type region or the P-type region through a third electrical interconnection. The integrated chip can realize effective isolation of the substrates of the two semiconductor device regions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an integrated chip with a junction isolation structure and a manufacturing method thereof. Background Art

[0002] Wide bandgap gallium nitride high electron mobility transistor (GaN High Electron Mobility Transistor, GaN HEMT) devices have become a power device that has attracted much attention in high-frequency applications and high-power density applications because of their combination of high switching speed, low conduction loss and low switching loss. When GaN HEMT is used in traditional DC-DC fields (such as buck, boost and fly back, etc.), it has begun to be used more and more widely. Half-bridge circuits are widely used in PWM motor control, DC-AC inverters, electronic ballasts and other occasions. Compared with depletion-mode GaN HEMT devices, enhancement-mode GaN HEMT devices are more suitable for use in half-bridge circuits because their driving circuits are simpler, which is conducive to reducing the area and complexity of the system. However, most of the GaNHEMT devices on the market are discrete devices, which must be connected to other components through external circuits to realize specific functions, making the circuit volume large and parasitic, and unable to meet the system's requirements for higher frequency and smaller volume.

[0003] If the upper tube and the lower tube in the half-bridge circuit can be integrated on the same chip, the parasitic effects introduced by the interconnection between devices can be reduced, the switching speed of the switch tube can be increased, and the switching power consumption of the switch tube can be reduced. However, in the integrated half-bridge circuit designed with enhanced GaN HEMT devices, if the upper tube and the lower tube are not effectively isolated, the substrates of the upper tube and the lower tube are both grounded. When the upper tube is turned on, the source and drain are both positive voltages close to Vdd, and the substrate is at 0 potential. Due to the back gate effect, the threshold voltage and on-resistance of the device will increase, thereby increasing the power consumption of the upper tube, and then increasing the power consumption of the entire system.

[0004] In addition, when the substrate potentials of various parts of the integrated circuit lack effective isolation, the substrate potentials of the power tube part and the analog part of the integrated circuit will interfere with each other due to the difference in voltage levels. When the potential of the power tube part is unstable, it may affect the analog part, causing the analog part to malfunction or even burn out. Summary of the invention

[0005] A first object of the present invention is to provide an integrated chip with a junction isolation structure capable of effectively isolating the substrates of two semiconductor device regions.

[0006] The second object of the present invention is to provide a method for manufacturing the above-mentioned integrated chip.

[0007] To achieve the above first objective, the present invention provides an integrated chip with a junction isolation structure, the integrated chip comprising a substrate and an epitaxial structure arranged in a longitudinal direction. A well region is arranged on the substrate, and the well region divides the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in a transverse direction. The substrate comprises an N-type region and a P-type region, and two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the first semiconductor device region and the second semiconductor device region. A first drain, a first gate, a first source, a second drain, a second gate, and a second source are arranged on the upper side of the epitaxial structure, the first drain, the first gate, and the first source are all located in the first semiconductor device region, and the second drain, the second gate, and the second source are all located in the second semiconductor device region. A first through-glass through hole, a second through-glass through hole, and a third through-glass through hole extending longitudinally are opened in the epitaxial structure, the second through-glass through hole is located in the first semiconductor device region, and the third through-glass through hole is located in the second semiconductor device region. A first electrical interconnection is arranged in the first through-glass through hole, and the first drain or the second source is electrically connected to the well region through the first electrical interconnection. A second electrical interconnection is provided in the second through-glass via, the first source is electrically connected to the N-type region or the P-type region through the second electrical interconnection, and the second drain is short-circuited to the first source. A third electrical interconnection is provided in the third through-glass via, the second source is electrically connected to the N-type region or the P-type region through the third electrical interconnection.

[0008] It can be seen from the above scheme that the present invention forms two equivalent diodes in the portion of the substrate located in the first semiconductor device region and the portion of the substrate located in the second semiconductor device region by setting the well region, the first through-glass via, the second through-glass via and the third through-glass via. When the circuit is working, the first drain is connected to the high voltage Vdd, the second source is grounded (0V), the first source and the second drain are short-circuited as output; the metal in the first through-glass via is connected to the first drain and then connected to the high voltage Vdd.

[0009] In this way, substrate isolation of the first semiconductor device region and the second semiconductor device region is achieved, that is, the first semiconductor device region and the second semiconductor device region can have independent substrate potentials according to different device working states, and when the first semiconductor device region is turned on, the influence of the back gate effect caused by the substrates of the first semiconductor device region and the second semiconductor device region being at 0 potential is avoided, thereby reducing the increase in system power consumption caused by the increase in the on-resistance of the first semiconductor device region due to the back gate effect.

[0010] The integrated chip of the present invention integrates the first semiconductor device area and the second semiconductor device area on the same substrate and effectively isolates the substrate potential through the well area, thereby reducing the parasitic effects introduced by the interconnection between devices, increasing the switching speed of the switch tube, and reducing the switching power consumption of the switch tube.

[0011] A preferred solution is that the substrate includes a P-type silicon substrate and an N-type silicon epitaxial layer formed by epitaxial growth upward from the P-type silicon substrate, the P-type silicon substrate serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

[0012] A further solution is that the well region is located on the P-type silicon substrate, and the second electrical interconnection and the third electrical interconnection both extend downward into the N-type silicon epitaxial layer.

[0013] It can be seen that the substrate doping type is a NP two-layer structure, that is, after ion implantation is performed on a P-type substrate to form a P-type well region, epitaxy is performed to form an N-type epitaxial layer.

[0014] A further solution is that the well region passes through the N-type silicon epitaxial layer and extends downward into the P-type silicon substrate, and the second electrical interconnection and the third electrical interconnection both extend downward into the N-type silicon epitaxial layer.

[0015] It can be seen that the doping of the P-type well region can also be carried out after the NP structure epitaxy is completed. At this time, the metal in the first through-glass via does not directly contact the upper N-type silicon epitaxial layer, and forms a PN junction with the upper N-type silicon epitaxial layer through the P-type well region. In this way, the process step of forming an isolation dielectric layer on the side wall of the first through-glass via can be omitted.

[0016] A preferred solution is that the substrate includes a P-type silicon substrate and an N-type silicon epitaxial layer and a P-type silicon epitaxial layer formed sequentially upward by epitaxy from the P-type silicon substrate, the P-type silicon epitaxial layer serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

[0017] A further solution is that the well region is located on the N-type silicon epitaxial layer, and the second electrical interconnection and the third electrical interconnection both extend downward into the P-type silicon epitaxial layer.

[0018] It can be seen that the substrate doping type is a PNP three-layer structure, that is, after an N-type epitaxial layer is formed on a P-type substrate by epitaxial growth, ion implantation is performed on the N-type epitaxial layer to form an N-type well region, and then epitaxial growth is continued to form an upper P-type silicon epitaxial layer.

[0019] A further solution is that the well region passes through the P-type silicon epitaxial layer and extends downward into the N-type silicon epitaxial layer, and the second electrical interconnection and the third electrical interconnection both extend downward into the P-type silicon epitaxial layer.

[0020] It can be seen that the doping of the N-type well region can also be carried out after the epitaxy of the PNP structure is completed. At this time, the metal in the first through-glass via does not directly contact the upper P-type silicon epitaxial layer, and forms a PN junction with the upper P-type silicon epitaxial layer through the N-type well region. In this way, the process step of forming an isolation dielectric layer on the side wall of the first through-glass via can be omitted.

[0021] A preferred solution is that an isolation dielectric layer is provided on the side wall of the first through-glass hole.

[0022] It can be seen that the sidewall of the first through-glass via is protected by the isolation dielectric layer, thereby preventing leakage between the metal of the first through-glass via and the substrate.

[0023] A further solution is that the material of the isolation dielectric layer is oxide or silicon nitride.

[0024] A preferred solution is that the epitaxial structure includes a channel layer, a barrier layer, an EPI passivation protection layer, an interlayer dielectric (ILD) layer, a first metal layer, an intermetallic dielectric (IMD) layer, a second metal layer and a passivation protection layer stacked in sequence from bottom to top; an ohmic metal layer is arranged on the EPI passivation protection layer, the upper end of the ohmic metal layer is located in the ILD layer, and the lower end of the ohmic metal layer is connected to the barrier layer; a vertically stacked P-type gate dielectric layer and a gate metal layer are also arranged in the EPI passivation protection layer, and the P-type gate dielectric layer is connected to the top of the barrier layer; a first contact is opened in the ILD layer A through hole is provided in the IMD layer, and the metal filled in the through hole electrically connects the second metal layer with the first metal layer; the passivation protection layer is provided with a plurality of openings extending through the vertical direction, and the first drain, the first gate, the first source, the second drain, the second gate and the second source are all located on the second metal layer and leak out from the corresponding openings respectively.

[0025] A further solution is that the upper end of the first electrical interconnection is connected to the first metal layer, and the upper ends of the second electrical interconnection and the third electrical interconnection are both connected to the second metal layer.

[0026] A further solution is that the upper ends of the first electrical interconnection, the second electrical interconnection and the third electrical interconnection are all connected to the first metal layer.

[0027] A further solution is that the upper ends of the first electrical interconnection, the second electrical interconnection and the third electrical interconnection are all connected to the second metal layer.

[0028] A preferred solution is that the well region surrounds the first semiconductor device region, and the second semiconductor device region is located outside the well region.

[0029] It can be seen that the first semiconductor device region is manufactured in the area surrounded by the well region.

[0030] A preferred solution is that the well region surrounds the second semiconductor device region, and the first semiconductor device region is located outside the well region.

[0031] It can be seen that the second semiconductor device region is fabricated in the area surrounded by the well region, and when the first through-glass via is fabricated, the metal in the first through-glass via is connected to the second source electrode, which is a grounding state. Thus, in various working states of the circuit, the substrate potential isolation between the first semiconductor device region and the second semiconductor device region can be achieved.

[0032] To achieve the second objective, the present invention provides a method for manufacturing the above-mentioned integrated chip, the manufacturing method comprising a substrate manufacturing step and an epitaxial structure manufacturing step; the substrate manufacturing step comprises forming a well region on a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a schematic cross-sectional view of the integrated chip according to the first embodiment of the present invention, showing two equivalent diodes A1 and A2.

[0034] Figure 2 It is a schematic diagram of the top view of the integrated chip of the first embodiment of the present invention.

[0035] Figure 3 It is a schematic diagram of forming an N-type silicon epitaxial layer on a P-type silicon substrate in the first embodiment of the integrated chip of the present invention.

[0036] Figure 4 It is a schematic diagram of forming a well region on an N-type silicon epitaxial layer in the first embodiment of the integrated chip of the present invention.

[0037] Figure 5 It is a schematic diagram of forming a P-type silicon epitaxial layer on an N-type silicon epitaxial layer in the first embodiment of the integrated chip of the present invention.

[0038] Figure 6 It is a schematic diagram of the integrated chip in the first embodiment of the present invention after a channel layer, a barrier layer and a dielectric layer are formed on a P-type silicon epitaxial layer.

[0039] Figure 7 It is a schematic diagram of forming a metal layer on a dielectric layer in the first embodiment of the integrated chip of the present invention.

[0040] Figure 8 It is a schematic diagram of forming a P-type gate dielectric layer and a gate metal layer in the first embodiment of the integrated chip of the present invention.

[0041] Fig. 9 It is a schematic diagram of forming an EPI passivation layer in the first embodiment of the integrated chip of the present invention.

[0042] Fig.10 It is a schematic diagram of the integrated chip in the first embodiment of the present invention after an ohmic contact hole is formed on the EPI passivation layer.

[0043] Fig.11It is a schematic diagram of the integrated chip after the ohmic metal layer is formed in the first embodiment of the present invention.

[0044] Fig.12 It is a schematic diagram of the integrated chip after the ILD layer is formed in the first embodiment of the present invention.

[0045] Fig.13 Schematic diagram of the integrated chip after the first through-glass via is formed in the first embodiment of the present invention.

[0046] Fig.14 It is a schematic diagram of the integrated chip in the first embodiment of the present invention after an oxide layer is formed on the side wall of the first through-glass via.

[0047] Fig.15 It is a schematic diagram of the integrated chip after the contact holes are formed in the first embodiment of the present invention.

[0048] Fig.16 It is a schematic diagram of the contact hole and the first through-glass via in the first embodiment of the integrated chip of the present invention after being filled with tungsten plugs.

[0049] Fig.17 It is a schematic diagram of the integrated chip after the first metal layer is formed in the first embodiment of the present invention.

[0050] Fig.18 It is a schematic diagram of the integrated chip after the IMD layer is formed in the first embodiment of the present invention.

[0051] Fig.19 It is a schematic diagram of the integrated chip after a through hole is opened in the IMD layer in the first embodiment of the present invention.

[0052] Fig. 20 It is a schematic diagram of the integrated chip in the first embodiment of the present invention after the through hole is filled with a tungsten plug.

[0053] Fig.21 It is a schematic diagram of the integrated chip after the second through-glass via and the third through-glass via are formed in the first embodiment of the present invention.

[0054] Fig. 22 It is a schematic diagram of the integrated chip after the second metal layer is formed in the first embodiment of the present invention.

[0055] Fig.23 It is a schematic diagram of the integrated chip after the passivation protection layer is formed in the first embodiment of the present invention.

[0056] Fig.24 FIG. 1 is a schematic cross-sectional view of the integrated chip according to the second embodiment of the present invention, showing two equivalent diodes B1 and B2.

[0057] Fig.25FIG. 1 is a schematic cross-sectional view of the fourth embodiment of the integrated chip of the present invention, showing two equivalent diodes C1 and C2.

[0058] Fig.26 A schematic top view of the structure of a fourth embodiment of an integrated chip of the present invention.

[0059] Fig. 27 The cross-sectional structure diagram of the fifth embodiment of the integrated chip of the present invention shows two equivalent diodes D1 and D2.

[0060] Fig.28 A schematic top view of the structure of a sixth embodiment of the integrated chip of the present invention.

[0061] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0062] Integrated chip with junction isolation structure and manufacturing method thereof First embodiment:

[0063] See also Figure 1 and Figure 2 The integrated chip with a junction isolation structure of this embodiment includes a substrate 20 and an epitaxial structure 30 arranged in a longitudinal direction.

[0064] The substrate 20 is a PNP three-layer structure, and the substrate 20 includes a P-type silicon substrate 21 and an N-type silicon epitaxial layer 22 and a P-type silicon epitaxial layer 23 formed by epitaxy from the P-type silicon substrate 21 in sequence. A rectangular ring-shaped N-type well region (N+well) 24 is provided on the N-type silicon epitaxial layer 22. The N-type well region 24 divides the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in the horizontal direction. The first semiconductor device region is Figure 1 The E-mode GaN HEMT Q1 device area in the middle is referred to as the upper tube Q1, and the second semiconductor device area is Figure 1 The E-mode GaN HEMT Q2 device region in the embodiment is referred to as the lower tube Q2 hereinafter. In this embodiment, the N-type well region 24 surrounds the upper tube Q1 , and the lower tube Q2 is located outside the N-type well region 24 .

[0065] The upper side of the epitaxial structure 30 is provided with a first drain 11, a first gate 12, a first source 13, a second drain 14, a second gate 15 and a second source 16 arranged in sequence along the lateral direction. The first drain 11, the first gate 12 and the first source 13 are all located in the upper tube Q1 part, and the second drain 14, the second gate 15 and the second source 16 are all located in the lower tube Q2 part.

[0066] The epitaxial structure 30 includes an AlN nucleation layer (not shown), a stress buffer layer (not shown), a channel layer 3, a barrier layer 4, an EPI passivation layer 5, an interlayer dielectric (ILD) layer 6, a first metal layer 7, an intermetallic dielectric (IMD) layer 8, a second metal layer 9 and a passivation protection layer 10 stacked in sequence from bottom to top, and the AlN nucleation layer is connected to the P-type silicon epitaxial layer 23. An ohmic metal layer 51 is arranged on the EPI passivation layer 5, the upper end of the ohmic metal layer 51 is located in the ILD layer 6, and the lower end of the ohmic metal layer 51 is connected to the barrier layer 4. A vertically stacked P-type gate dielectric layer 52 and a gate metal layer 53 are also arranged in the EPI passivation layer 5, and the P-type gate dielectric layer 52 is connected above the barrier layer 4. The material of the channel layer 3 is GaN, the material of the barrier layer 4 is AlGaN, the material of the P-type gate dielectric layer 52 is GaN, and the material of the EPI passivation layer 5 is Si3N4.

[0067] A first contact hole 61 (contact) and a second contact hole 62 are provided in the ILD layer 6. The metal filled in the first contact hole 61 electrically connects the ohmic metal layer 51 with the first metal layer 7. The second contact hole 62 penetrates the ILD layer 6 and the EPI passivation layer 5 in the vertical direction. The metal filled in the second contact hole 62 electrically connects the gate metal layer 53 with the first metal layer 7. A through hole 81 (via) is provided in the IMD layer 8. The metal filled in the through hole 81 electrically connects the second metal layer 9 with the first metal layer 7. The passivation protection layer 10 is provided with a plurality of openings 101 in the vertical direction. The first drain 11, the first gate 12, the first source 13, the second drain 14, the second gate 15 and the second source 16 are all located on the second metal layer 9 and leak out from the corresponding openings 101 respectively.

[0068] The epitaxial structure 30 is provided with a first through glass via 31 (TGV), a second through glass via 32 and a third through glass via 33 extending longitudinally. The second through glass via 32 is located at the upper tube Q1 part, and the third through glass via 33 is located at the lower tube Q2 part. A first electrical interconnection 311 is provided in the first through glass via 31, and the first drain 11 is electrically connected to the N-type well region 24 through the first electrical interconnection 311. Specifically, the upper end of the first electrical interconnection 311 is connected to the first metal layer 7, and the lower end of the first electrical interconnection 311 is in ohmic contact with the N-type well region 24. An isolation dielectric layer 312 is provided on the side wall of the first through glass via 31. The material of the isolation dielectric layer 312 is oxide or silicon nitride. The side wall of the first through glass via 31 is protected by the isolation dielectric layer 312, so as to avoid leakage between the metal in the first through glass via 31 and the P-type silicon epitaxial layer 23.

[0069] A second electrical interconnection 321 is provided in the second through-glass via 32, the first source 13 is electrically connected to the portion of the P-type silicon epitaxial layer 23 located in the upper tube Q1 through the second electrical interconnection 321, and the second drain 14 is short-circuited to the first source 13 through the second metal layer 9. The upper end of the second electrical interconnection 321 is connected to the first source 13 of the second metal layer 9, and the lower end of the second electrical interconnection 321 extends to the portion of the P-type silicon epitaxial layer 23 located in the upper tube Q1.

[0070] A third electrical interconnection 331 is disposed in the third through-glass via 33, and the second source 16 is electrically connected to the portion of the P-type silicon epitaxial layer 23 located in the lower tube Q2 through the third electrical interconnection 331. The upper end of the third electrical interconnection 331 is connected to the second source 16 of the second metal layer 9, and the lower end of the third electrical interconnection 331 extends to the portion of the P-type silicon epitaxial layer 23 located in the lower tube Q2.

[0071] The manufacturing method of the integrated chip includes a substrate manufacturing step and an epitaxial structure manufacturing step.

[0072] The steps of substrate preparation include:

[0073] First, a P-type silicon substrate 21 is provided.

[0074] Then, if Figure 3 As shown, an N-type silicon epitaxial layer 22 is epitaxially formed on a P-type silicon substrate 21 .

[0075] Then, if Figure 4 As shown, the N-type silicon epitaxial layer 22 is well doped by ion implantation to form an N-type well region 24 .

[0076] Then, if Figure 5 As shown, a P-type silicon epitaxial layer 23 is epitaxially formed on the N-type silicon epitaxial layer 22 .

[0077] The steps of epitaxial structure fabrication include:

[0078] First, if Figure 6 As shown, a channel layer 3 , a barrier layer 4 and a dielectric layer 520 are epitaxially grown in sequence on the P-type silicon epitaxial layer 23 of the substrate 20 .

[0079] Then, if Figure 7 As shown, metal deposition is performed on the dielectric layer 520 to form a metal layer 530 .

[0080] Next, semiconductor photolithography and etching techniques are used to pattern the dielectric layer 520 and the metal layer 530 to form Figure 8 A P-type gate dielectric layer 52 and a gate metal layer 53 are shown.

[0081] Then, if Fig. 9 As shown, deposition is performed to form an EPI passivation layer 5 .

[0082] Then, if Fig.10 As shown, an ohmic contact hole 510 is formed on the EPI passivation layer 5 by using photolithography technology and etching technology.

[0083] Then, if Fig.11 As shown, after ohmic metal deposition is performed on the EPI passivation layer 5, an ohmic metal layer 51 is formed by using photolithography technology and etching technology.

[0084] Then, if Fig.12 As shown, the ILD layer 6 is formed by deposition and planarization processes.

[0085] Then, if Fig.13 As shown, a first through-glass via 31 extending into the N-type well region 24 in the vertical direction is formed by using photolithography technology and etching technology.

[0086] Then, if Fig.14 As shown, an oxide layer serving as an isolation dielectric layer 312 is deposited on the sidewall of the first through-glass hole 31 .

[0087] Then, if Fig.15 As shown, a first contact hole 61 penetrating the ILD layer 6 in the vertical direction is formed above the ohmic metal layer 51 by using photolithography technology and etching technology, and a second contact hole 62 penetrating the ILD layer 6 and the EPI passivation layer 5 in the vertical direction is formed above the gate metal layer 53 .

[0088] Then, if Fig.16 As shown, tungsten plugs are filled in the first contact hole 61 , the second contact hole 62 and the first through-glass via 31 , and excess tungsten on the surface of the ILD layer 6 is removed.

[0089] Then, if Fig.17 As shown, metal is deposited on the ILD layer 6 to form a first metal layer 7, and the first metal layer 7 is patterned using photolithography and etching techniques.

[0090] Next, a deposition and planarization process is used to form Fig.18 The IMD layer 8 is shown.

[0091] Then, if Fig.19 As shown, a via 81 (via) penetrating the IMD layer 8 in the vertical direction is formed by using photolithography technology and etching technology.

[0092] Then, if Fig. 20 As shown, a tungsten plug is filled in the through hole 81, and excess tungsten on the surface of the IMD layer 8 is removed.

[0093] Then, photolithography and etching techniques are used to form Fig.21The second TSV 32 and the third TSV 33 are shown extending into the P-type silicon epitaxial layer 23 in the longitudinal direction.

[0094] Then, if Fig. 22 As shown, metal is deposited on the IMD layer 8, and the second metal layer 9 is patterned using photolithography and etching techniques.

[0095] Finally, if Fig.23 As shown, a passivation protection layer 10 is deposited on the second metal layer 9, and the passivation protection layer 10 is patterned using photolithography and etching techniques to expose the first drain 11, the first gate 12, the first source 13, the second drain 14, the second gate 15 and the second source 16.

[0096] The present invention changes the traditional P-type silicon substrate into a PNP three-layer substrate structure, and performs N-type well (N+Well) doping on the N-type silicon epitaxial layer 22, and the N-type well region 24 surrounds the area where the upper tube Q1 is located. The N-type well region 24 is connected to the first drain 11 of the upper tube Q1 through a first through-glass via 31, and the metal in the first through-glass via 31 forms an ohmic contact with the N-type well region 24, and the first drain 11 of the upper tube Q1 is connected to the Vdd of the system. In addition, the uppermost P-type silicon epitaxial layer 23 in the PNP three-layer substrate surrounding the inner side of the N-type well region 24 is connected to the first source 13 of the upper tube Q1 through a second through-glass via 32, and the upper P-type silicon epitaxial layer 23 in the PNP three-layer substrate in the outer side of the N-type well region 24 is connected to the second source 16 of the lower tube Q2 through a third through-glass via 33, so that the upper P-type silicon epitaxial layer 23 in the substrate of the upper tube Q1 and the lower tube Q2 is connected to the first through-glass via 31 surrounding the upper tube Q1. The through hole 31 is divided into two parts, so that the second through-glass through hole 32 in the upper tube Q1 and the third through-glass through hole 33 in the lower tube Q2 are connected to the substrates of the upper tube Q1 and the lower tube Q2 respectively. Since the metal in the first through-glass through hole 31 provides a positive voltage to the N-type epitaxial layer, the diode formed by the N-type epitaxial layer and the P-type silicon epitaxial layer 23 of the substrate is reverse biased to form a high-resistance depletion region, thereby achieving isolation of the substrate potentials of the upper tube Q1 and the lower tube Q2, and achieving different substrate potentials for the upper tube Q1 and the lower tube Q2.

[0097] Due to the existence of the first through-glass via 31 and the N-type well region 24, PN junctions are formed in the substrate region of the upper tube Q1 and the substrate region of the lower tube Q2, thereby forming Figure 1The equivalent diodes A1 and A2 are shown, and both PN junctions are located between the N-type silicon epitaxial layer 22 and the P-type silicon epitaxial layer 23. When the circuit is working, the first drain 11 of the upper tube Q1 is connected to the high voltage Vdd, the second source 16 of the lower tube Q2 is grounded (0V), and the first source 13 of the upper tube Q1 and the second drain 14 of the lower tube Q2 are short-circuited through metal interconnection and serve as output terminals. The metal in the first through-glass via 31 is short-circuited with the first drain 11 of the upper tube Q1 and then connected to the high voltage Vdd, the first source 13 of the upper tube Q1 is connected to the upper P-type silicon epitaxial layer 23 of the substrate region of the upper tube Q1 through the metal in the second through-glass via 32, and the second source 16 of the lower tube Q2 is connected to the upper P-type silicon epitaxial layer 23 of the substrate region of the lower tube Q2 through the metal in the third through-glass via 33.

[0098] When the upper tube Q1 is turned on and the lower tube Q2 is turned off, the output end outputs a high potential. At this time, the first source 13 of the upper tube Q1 is a high potential close to Vdd (Vdd minus the turn-on voltage of the upper tube Q1), the Source of the lower tube Q2 is 0 potential, A1 is in a zero bias state, A2 is in a reverse bias state, and A2 forms a depletion region to bear the Vdd voltage, so that the P-type silicon epitaxial layer 23 on the substrate of the upper tube Q1 is at a high potential, and most of the P-type silicon epitaxial layer 23 on the substrate of the lower tube Q2 (except the depletion region of A2) is at zero potential.

[0099] When the upper tube Q1 is turned off and the lower tube Q2 is turned on, the output end outputs a low potential. At this time, the Source of the upper tube Q1 is a low potential close to 0 potential (the turn-on voltage of the lower tube Q2), the Source of the lower tube Q2 is 0 potential, A1 and A2 are both in reverse biased state, and the depletion region formed by the two diodes bears the Vdd voltage brought by TGV1. Most areas of the P-type silicon epitaxial layer 23 on the substrate of the upper tube Q1 and the lower tube Q2 (except the depletion regions of A1 and A2) are close to 0 potential.

[0100] In this case, the substrate isolation of the upper tube Q1 and the lower tube Q2 is achieved, that is, the upper tube Q1 and the lower tube Q2 can have independent substrate potentials according to different device working states, and the influence of the back gate effect caused by the substrates of the upper tube Q1 and the lower tube Q2 being at 0 potential is avoided when the upper tube Q1 is turned on, thereby reducing the increase in system power consumption caused by the increase in the on-resistance of the upper tube Q1 due to the back gate effect.

[0101] Integrated chip with junction isolation structure and manufacturing method thereof Second embodiment:

[0102] As an explanation of the second embodiment of the integrated chip and the manufacturing method thereof of the present invention, only the differences from the first embodiment of the integrated chip and the manufacturing method thereof are explained below.

[0103] See also Fig.24In this embodiment, in the substrate manufacturing step, the doping of the N-type well region can also be performed after the epitaxy of the PNP structure is completed, that is, the N-type silicon epitaxial layer 222 is first epitaxially formed on the P-type silicon substrate 221, and then the P-type silicon epitaxial layer 223 is epitaxially formed on the N-type silicon epitaxial layer 222, and then the well doping is performed on the substrate of the PNP three-layer structure to form the N-type well region 224. The N-type well region 224 passes through the P-type silicon epitaxial layer 223 and extends downward into the N-type silicon epitaxial layer 222, and the second electrical interconnection 2321 and the third electrical interconnection 2331 also extend downward into the P-type silicon epitaxial layer 223.

[0104] It can be seen that the metal in the first through-glass via 231 does not directly contact the upper P-type silicon epitaxial layer 223, and forms two PN junctions with the upper P-type silicon epitaxial layer 223 through the N-type well region 224, thereby forming a Fig.24 Therefore, the solution in this embodiment can omit the process step of forming an isolation dielectric layer on the side wall of the first through-glass via 231.

[0105] Integrated chip with junction isolation structure and manufacturing method thereof Third embodiment:

[0106] As a description of the third embodiment of the integrated chip and the manufacturing method thereof of the present invention, only the differences from the first embodiment of the integrated chip and the manufacturing method thereof are described below.

[0107] In this embodiment, the substrate is a NP two-layer structure, and the substrate includes a P-type silicon substrate and an N-type silicon epitaxial layer formed by epitaxy upward from the P-type silicon substrate. The well region is located on the P-type silicon substrate, and the second electrical interconnection and the third electrical interconnection both extend downward into the N-type silicon epitaxial layer.

[0108] In this embodiment, the substrate manufacturing step includes first providing a P-type silicon substrate, then performing well doping on the P-type silicon substrate by ion implantation to form a P-type well region, and then epitaxially forming an N-type silicon epitaxial layer on the P-type silicon substrate.

[0109] Integrated chip with junction isolation structure and manufacturing method thereof Fourth embodiment:

[0110] As a description of the fourth embodiment of the integrated chip and the manufacturing method thereof of the present invention, only the differences from the third embodiment of the integrated chip and the manufacturing method thereof are described below.

[0111] See also Fig.25 and Fig.26 In this embodiment, the P-type well region 424 surrounds the lower tube Q2, and the upper tube Q1 is located outside the P-type well region 424. The second source 416 is electrically connected to the P-type well region 424 through the first electrical interconnection 4311.

[0112] In this embodiment, the substrate region of the upper tube Q1 and the substrate region of the lower tube Q2 also form two PN junctions, thereby forming Fig.25 The equivalent diodes C1 and C2 shown have similar working principles to those of the first embodiment, but the types and working states of the related diodes are opposite. When the circuit is working, the first drain 411 of the upper tube Q1 is connected to the high voltage Vdd, the second source 416 of the lower tube Q2 is grounded (0V), and the first source 413 of the upper tube Q1 and the second drain 414 of the lower tube Q2 are short-circuited through metal interconnection and serve as output terminals. The first through-glass via 431 is short-circuited with the second source 416 of the lower tube Q2 and then grounded, the first source 413 of the upper tube Q1 is connected to the upper N-type silicon epitaxial layer 422 of the substrate region of the upper tube Q1 through the second through-glass via 432, and the second source 416 of the lower tube Q2 is connected to the upper N-type silicon epitaxial layer 422 of the substrate region of the lower tube Q2 through the third through-glass via 433.

[0113] When the upper tube Q1 is turned on and the lower tube Q2 is turned off, the output end outputs a high potential. At this time, the first source 413 of the upper tube Q1 is a high potential close to Vdd (Vdd minus the on-voltage of the upper tube Q1), the second source 416 of the lower tube Q2 is 0 potential, C1 is in a reverse bias state, C2 is in a zero bias state, and C1 forms a depletion region to bear the high voltage, so that most of the N-type silicon epitaxial layer 422 on the substrate of the upper tube Q1 (except the depletion region of C1) is at a high potential, and the N-type silicon epitaxial layer 422 on the substrate of the lower tube Q2 is at a zero potential.

[0114] When the upper tube Q1 is turned off and the lower tube Q2 is turned on, the output end outputs a low potential. At this time, the first source 413 of the upper tube Q1 is a low potential close to 0 potential (the turn-on voltage of the lower tube Q2), the second source 416 of the lower tube Q2 is 0 potential, C1 is in a weak reverse bias state, C2 is in a zero bias state, and the N-type silicon epitaxial layer 422 on the substrate of the upper tube Q1 and the lower tube Q2 are both close to 0 potential.

[0115] In this case, the substrate isolation of the upper tube Q1 and the lower tube Q2 is achieved, that is, the upper tube Q1 and the lower tube Q2 can have independent substrate potentials according to different device working states, and the influence of the back gate effect caused by the substrates of the upper tube Q1 and the lower tube Q2 being at 0 potential is avoided when the upper tube Q1 is turned on, thereby reducing the increase in system power consumption caused by the increase in the on-resistance of the upper tube Q1 due to the back gate effect.

[0116] Integrated chip with junction isolation structure and manufacturing method thereof Fifth embodiment:

[0117] As an explanation of the fifth embodiment of the integrated chip and the manufacturing method thereof of the present invention, only the differences from the fourth embodiment of the integrated chip and the manufacturing method thereof are explained below.

[0118] See also Fig. 27In this embodiment, in the substrate manufacturing step, the doping of the P-type well region 524 can also be performed after the NP structure epitaxy is completed, that is, the N-type silicon epitaxial layer 522 is first formed on the P-type silicon substrate 521 by epitaxy, and then, the well doping is performed on the substrate of the NP two-layer structure to form the P-type well region 524. The P-type well region 524 passes through the N-type silicon epitaxial layer 522 and extends downward into the P-type silicon substrate 521, and the second electrical interconnection 5321 and the third electrical interconnection 5331 also extend downward into the N-type silicon epitaxial layer 522.

[0119] It can be seen that the metal in the first through-glass via 531 does not directly contact the upper N-type silicon epitaxial layer 522, but forms two PN junctions with the upper N-type silicon epitaxial layer 522 through the P-type well region 524, thereby forming a Fig. 27 Therefore, the solution in this embodiment can also omit the process step of forming an isolation dielectric layer on the side wall of the first through-glass via 531.

[0120] Integrated chip with junction isolation structure and manufacturing method thereof Sixth embodiment:

[0121] As an explanation of the sixth embodiment of the integrated chip and the manufacturing method thereof of the present invention, only the differences from the first embodiment of the integrated chip and the manufacturing method thereof are explained below.

[0122] See also Fig.28 The N-type well region 624 may also be in the shape of a ring with a polygonal cross section.

[0123] In addition, the upper ends of the first electrical interconnect, the second electrical interconnect, and the third electrical interconnect can also be connected to the first metal layer. The upper ends of the first electrical interconnect, the second electrical interconnect, and the third electrical interconnect can also be connected to the second metal layer. The process flow of device manufacturing and the number of metal layers and interconnection methods of the upper layer can be modified according to the design. The well region can also extend in a straight line and run through the cells of the integrated chip. The shape of the well region can also be other irregular shapes to achieve isolation of the upper tube Q1 and the lower tube Q2. In the above embodiments, the structure of the substrate is designed based on a P-type silicon substrate. If there is a suitable N-type substrate, the PNP and NP structures in the above embodiments can be changed to PN and NPN structures, and even a combination of substrates of various types and doping concentrations can be used, as long as the partial structure of the substrate can achieve the junction isolation effect mentioned in the present invention. The formation of the well region can also be formed by a diffusion process or by a combination of ion implantation and diffusion process. The integrated chip may further include a field plate, which covers the top of the gate and extends toward the drain, and covers a portion of the drift region. The field plate may be a single-layer or multi-layer structure, and the field plate is electrically connected to the gate or the source. The field plate is used to regulate the electric field distribution in the drift region of the device to improve the voltage resistance and reliability of the device. The above changes can also achieve the purpose of the present invention.

[0124] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An integrated chip with a junction isolation structure, characterized in that: including a substrate and an epitaxial structure arranged in a longitudinal direction; A well region is provided on the substrate, and the well region divides the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in a lateral direction; The substrate comprises an N-type region and a P-type region, two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the first semiconductor device region and the second semiconductor device region; A first drain, a first gate, a first source, a second drain, a second gate and a second source are disposed on the upper side of the epitaxial structure, the first drain, the first gate and the first source are all located in the first semiconductor device region, and the second drain, the second gate and the second source are all located in the second semiconductor device region; The epitaxial structure is provided with a first through-glass via, a second through-glass via and a third through-glass via extending longitudinally, wherein the second through-glass via is located in the first semiconductor device region, and the third through-glass via is located in the second semiconductor device region; A first electrical interconnection is disposed in the first through-glass via, and the first drain or the second source is electrically connected to the well region through the first electrical interconnection; A second electrical interconnection is provided in the second through-glass via, the first source is electrically connected to the N-type region or the P-type region through the second electrical interconnection, and the second drain is short-circuited with the first source; A third electrical interconnection is provided in the third through-glass via, and the second source is electrically connected to the N-type region or the P-type region through the third electrical interconnection; An isolation dielectric layer is disposed on the side wall of the first through-glass hole; The well region surrounds the first semiconductor device region, and the second semiconductor device region is located outside the well region; or The well region surrounds the second semiconductor device region, and the first semiconductor device region is located outside the well region.

2. The integrated chip according to claim 1, characterized in that: The substrate includes a P-type silicon substrate and an N-type silicon epitaxial layer formed by epitaxial growth upward from the P-type silicon substrate. The P-type silicon substrate serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

3. The integrated chip according to claim 2, characterized in that: The well region is located on the P-type silicon substrate, and the second electrical interconnection and the third electrical interconnection both extend downward into the N-type silicon epitaxial layer.

4. The integrated chip according to claim 2, characterized in that: The well region passes through the N-type silicon epitaxial layer and extends downward into the P-type silicon substrate, and the second electrical interconnection and the third electrical interconnection both extend downward into the N-type silicon epitaxial layer.

5. The integrated chip according to claim 1, characterized in that: The substrate includes a P-type silicon substrate and an N-type silicon epitaxial layer and a P-type silicon epitaxial layer sequentially formed upward by epitaxy from the P-type silicon substrate, the P-type silicon epitaxial layer serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

6. The integrated chip according to claim 5, characterized in that: The well region is located on the N-type silicon epitaxial layer, and the second electrical interconnection and the third electrical interconnection both extend downward into the P-type silicon epitaxial layer.

7. The integrated chip according to claim 5, characterized in that: The well region passes through the P-type silicon epitaxial layer and extends downward into the N-type silicon epitaxial layer, and the second electrical interconnection and the third electrical interconnection both extend downward into the P-type silicon epitaxial layer.

8. The integrated chip according to any one of claims 1 to 7, characterized in that: The material of the isolation dielectric layer is oxide or silicon nitride.

9. The integrated chip according to any one of claims 1 to 7, characterized in that: The epitaxial structure includes a channel layer, a barrier layer, an EPI passivation protection layer, an ILD layer, a first metal layer, an IMD layer, a second metal layer and a passivation protection layer stacked in sequence from bottom to top; An ohmic metal layer is disposed on the EPI passivation protection layer, the upper end of the ohmic metal layer is located in the ILD layer, and the lower end of the ohmic metal layer is connected to the barrier layer.

10. The integrated chip according to claim 9, characterized in that: A vertically stacked P-type gate dielectric layer and a gate metal layer are also provided in the EPI passivation protection layer, and the P-type gate dielectric layer is connected to the top of the barrier layer; A first contact hole and a second contact hole are formed in the ILD layer, the metal filled in the first contact hole electrically connects the ohmic metal layer with the first metal layer, the second contact hole penetrates the ILD layer and the EPI passivation protection layer in a vertical direction, and the metal filled in the second contact hole electrically connects the gate metal layer with the first metal layer; A through hole is provided in the IMD layer, and the metal filled in the through hole electrically connects the second metal layer with the first metal layer; The passivation protection layer is provided with a plurality of openings extending therethrough in the longitudinal direction, and the first drain, the first gate, the first source, the second drain, the second gate and the second source are all located on the second metal layer and leak out from the corresponding openings respectively.

11. The integrated chip according to claim 9, characterized in that: An upper end of the first electrical interconnection is connected to the first metal layer, and upper ends of the second electrical interconnection and the third electrical interconnection are both connected to the second metal layer.

12. The integrated chip according to claim 9, characterized in that: Upper ends of the first electrical interconnection, the second electrical interconnection, and the third electrical interconnection are connected to the first metal layer.

13. The integrated chip according to claim 9, characterized in that: Upper ends of the first electrical interconnection, the second electrical interconnection, and the third electrical interconnection are connected to the second metal layer.

14. A method for manufacturing an integrated chip, characterized in that: The integrated chip is the integrated chip as claimed in any one of claims 1 to 13, and the manufacturing method includes a substrate manufacturing step and an epitaxial structure manufacturing step; the substrate manufacturing step includes forming the well region on a substrate.

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