An optimized digital wireless communication chip system

Abstract

The present invention relates to the field of digital wireless communication chips, and in particular to an optimized digital wireless communication chip system. The system comprises a radio frequency controller and an EEPROM, a data cache FIFO, an SPI interface, an IO controller, an RSSI detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO and a QFN16 package connected thereto. The SPI interface is a logic master SPI interface, which is connected to the radio frequency controller via four lines of CSB, FCSB, SCLK and SDIO; the IO controller comprises a logic input and output circuit, which is connected to the chip package pins GPIO1, GPIO2 and GPIO3; the RSSI detector is connected to the radio frequency controller, the IQ demodulator is connected to the radio frequency controller via an IPC channel, the LNA is directly connected to the antenna input end, the mixer is connected to the LNA and the VCO via a chip internal shielded line, and the PA is connected to the antenna output end and the VCO. The present invention greatly simplifies the layout and wiring rules of chip applications.

Description

Technical Field

[0001] The present invention relates to the field of digital wireless communication chips, and in particular to an optimized digital wireless communication chip system. Background Art

[0002] The existing digital communication chips are a kind of highly integrated and intelligent integrated circuits. Digital communication chips are key devices widely used in various smart home products, industrial safety products, aerospace, military facilities, and police equipment in modern society. They are the premise and foundation of social modernization.

[0003] There are many digital wireless communication chip products on the market, with different manufacturers and great product differentiation, but there is a common problem of application threshold. Whether it is a foreign manufacturer or a domestic chip, it is necessary to consider the layout and routing when designing to minimize crosstalk and unnecessary electromagnetic radiation.

[0004] When designing chips, most manufacturers generally consider the optimization of the internal structure, while ignoring some practical difficulties in application testing. However, in the final analysis, application design is based on the layout and wiring of the chip pin definition, and the peripheral requirements are very strict to achieve the design purpose. Therefore, the shortcomings of these existing technical solutions are: design, optimization, and packaging only consider the internal side of the chip. Although the chip performance has been improved, due to factors such as excessively high layout and wiring requirements on the peripheral side and the increase in peripheral devices, the system's functions are affected and the cost is increased. Summary of the invention

[0005] In order to overcome the defects of existing digital wireless communication chips, such as high application threshold, sophisticated layout and routing, complex algorithms and difficulty in building a stable wireless communication system, which greatly affect the performance of digital wireless communication chips, the purpose of the present invention is to provide an improved digital wireless communication chip system that can overcome the defects of the prior art.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] An optimized digital wireless communication chip system comprises a radio frequency controller and an EEPROM, a data buffer FIFO, an SPI interface, an IO controller, an RSSI detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO and a QFN16 package connected thereto.

[0008] The SPI interface is a logic master SPI interface, which is connected to the RF controller through four lines: CSB, FCSB, SCLK, and SDIO; the IO controller includes logic input and output circuits, which are connected to the chip package pins GPIO1, GPIO2, and GPIO3; the RSSI detector is connected to the RF controller, the IQ demodulator is connected to the RF controller through the IPC channel, the LNA is directly connected to the antenna input, the mixer is connected to the LNA and the VCO through the internal shielded line of the chip, the PA is connected to the antenna output and the VCO, the PLL is a digital phase-locked loop with a loop filter, the QFN16 package includes a chip package pin 1 for the RF signal input P connected to the LNA, and a chip package pin 2 for the RF The signal input N is connected to the LNA, the chip package pin 3 is the PA output connected to the PA, the chip package pin 4 is the analog VDD, the chip package pin 5 is the analog GND, the chip package pin 6 is the digital GND, the chip package pin 7 is the digital VDD, the chip package pin 8 is GPIO3, the chip package pin 9 is the SPI clock, the chip package pin 10 is the data input and output of the SPI interface, the chip package pin 11 is the SPI access register chip select, the chip package pin 12 is the SPI access FIFO chip select, the chip package pin 13 is the crystal circuit input, the chip package pin 14 is the crystal circuit output, the chip package pin 15 is GPIO2, the chip package pin 16 is GPIO1, and the chip package substrate is the analog GND, defined as pin 17.

[0009] The package pins 1 (RFIP), 2 (RFIN), 3 (PA), and 4 (AVDD) are sequentially placed on the left side of the QFN16 package sheet.

[0010] The package pins 5 (AGND), 6 (DGND), 7 (DVDD), and 8 (GPIO3) are sequentially placed on the lower side of the QFN16 package sheet.

[0011] The package pins 9 (SCLK), 10 (SDIO), 11 (CSB), and 12 (FCSB) are sequentially placed on the right side of the QFN16 package sheet.

[0012] The package pins 13 (XI), 14 (XO), 15 (GPIO2), and 16 (GPIO1) are sequentially placed on the upper side of the QFN16 package sheet.

[0013] The package pin 17 (GND) is placed at the bottom of the chip.

[0014] In the above solution, the radio frequency controller uses an FPGA, the EEPROM is an 8*128-bit power-off storage and electrically erasable memory array, and the data cache FIFO is an 8*64-bit RAM.

[0015] The radio frequency controller described in the above technical solution may be composed of an FPGA and a crystal oscillator, a capacitor, a resistor and built-in firmware connected to the periphery.

[0016] The VCO circuit described in the above technical solution can be composed of correspondingly connected transistors, varactor diodes, resistors, inductors, and capacitors.

[0017] The PLL described in the above technical solution can be composed of a digital PLL module, a capacitor, and a resistor.

[0018] The beneficial effects of the present invention are as follows: first, through clever module placement and carefully arranged package pin distribution by type and distance, the layout and wiring rules of chip applications are greatly simplified, making the design and application more intelligent and flexible and effectively lowering the design threshold; second, module isolation measures are adopted inside the chip system package to effectively provide RF performance with low cost; third, the chip system has a built-in FPGA IQ demodulator, which can overcome the defects of amplitude imbalance, phase imbalance, DC offset, etc. caused by analog technology IQ demodulation, and the FPGA IQ demodulator has high stability.

[0019] The present invention is further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a block diagram of an embodiment of the present invention.

[0021] Figure 2 It is a block diagram of another embodiment of the present invention.

[0022] Figure 3 yes Figure 1 or Figure 2 Schematic diagram of the package top view.

[0023] Figure 4 yes Figure 1 or Figure 2 Schematic diagram of the package side view.

[0024] Figure 5 yes Figure 1 or Figure 2 Schematic diagram of the package viewed from above. DETAILED DESCRIPTION

[0025] Reference Figure 1The digital wireless communication chip system includes a radio frequency controller and an EEPROM, a data cache FIFO, an SPI interface, an IO controller, an RSSI detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO, and a QFN16 package connected thereto.

[0026] The RF controller uses an FPGA, the EEPROM is an 8*128-bit power-off storage and electrically erasable memory array, the data cache FIFO is an 8*64-bit RAM, the SPI interface is a logic master SPI interface, connected to the RF controller through four lines of CSB, FCSB, SCLK, and SDIO. The four-line routing of CSB, FCSB, SCLK, and SDIO is not specially processed, and the connection only serves as a connection; the IO controller includes logic input and output circuits, which are connected to the chip package pins GPIO1, GPIO2, and GPIO3; the RSSI detector is connected to the RF controller, the IQ demodulator is connected to the RF controller through the IPC channel, the LNA is directly connected to the antenna input, the mixer is connected to the LNA and the VCO through the internal shielded line of the chip, the PA is connected to the antenna output and the VCO, and the PLL is a The chip digital phase-locked loop is provided with a loop filter. The QFN16 package includes a chip package pin 1 for RF signal input P connected to the LNA, a chip package pin 2 for RF signal input N connected to the LNA, a chip package pin 3 for PA output, i.e. connected to the PA, a chip package pin 4 for analog VDD, a chip package pin 5 for analog GND, a chip package pin 6 for digital GND, a chip package pin 7 for digital VDD, a chip package pin 8 for GPIO3, a chip package pin 9 for SPI clock, a chip package pin 10 for data input and output of the SPI interface, a chip package pin 11 for SPI access register chip select, a chip package pin 12 for SPI access FIFO chip select, a chip package pin 13 for crystal circuit input, a chip package pin 14 for crystal circuit output, a chip package pin 15 for GPIO2, a chip package pin 16 for GPIO1, and a chip package substrate for analog GND, defined as pin 17.

[0027] The package pins 1 (RFIP), 2 (RFIN), 3 (PA), and 4 (AVDD) are sequentially placed on the left side of the QFN16 package sheet.

[0028] The package pins 5 (AGND), 6 (DGND), 7 (DVDD), and 8 (GPIO3) are sequentially placed on the lower side of the QFN16 package sheet.

[0029] The package pins 9 (SCLK), 10 (SDIO), 11 (CSB), and 12 (FCSB) are sequentially placed on the right side of the QFN16 package sheet.

[0030] The package pins 13 (XI), 14 (XO), 15 (GPIO2), and 16 (GPIO1) are sequentially placed on the upper side of the QFN16 package sheet.

[0031] The package pin 17 (GND) is placed at the bottom of the chip.

[0032] The internal structure layout optimized by the present invention is strictly in accordance with the functional layout of the package pins, so as to improve the RF parameters with the simplest and shortest lines possible, and effectively reduce the crosstalk and wiring difficulty of the application link. The modular structured compact layout of the present invention increases the wafer unit density, can reduce the wafer area, and effectively reduce the chip cost.

[0033] Reference Figure 2 The digital wireless communication chip system includes a radio frequency controller and an EEPROM, a data cache FIFO, an SPI interface, an IO controller, an RSSI detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO, and a QFN16 package connected thereto.

[0034] The RF controller uses an FPGA, the EEPROM is an 8*128-bit power-off storage and electrically erasable memory array, the data cache FIFO is an 8*64-bit RAM, the SPI interface is a logic master SPI interface, connected to the RF controller through four lines of CSB, FCSB, SCLK, and SDIO, the CSB, FCSB, SCLK, and SDIO four-line routing is not specially processed, and the connection only serves as a connection; the IO controller includes logic input and output circuits, the RSSI detector is connected to the RF controller, the IQ demodulator is connected to the RF controller through the IPC channel, the LNA is directly connected to the antenna input, the mixer is connected to the LNA and the VCO through the internal shielded line of the chip, the PA is connected to the antenna output and the VCO, the PLL is a digital phase-locked loop with a loop filter, and the QFN16 package includes a chip Package pin 1 is RF signal input P connected to the LNA, chip package pin 2 is RF signal input N connected to the LNA, and the connection lengths of the chip package pin 1 and pin 2 to the LNA module are equal; chip package pin 3 is PA output, i.e. connected to the PA, chip package pin 4 is analog VDD, chip package pin 5 is analog GND, chip package pin 6 is digital GND, chip package pin 7 is digital VDD, chip package pin 8 is GPIO3, chip package pin 9 is SPI clock, chip package pin 10 is data input and output of SPI interface, chip package pin 11 is SPI access register chip select, chip package pin 12 is SPI access FIFO chip select, chip package pin 13 is crystal circuit input, chip package pin 14 is crystal circuit output, chip package pin 15 is GPIO2, chip package pin 16 is GPIO1, and the chip package substrate is analog GND, defined as pin 17.

[0035] In this implementation mode, the layout of the internal functional modules of the chip does not consider the function of the package pins. The layout of the internal functional modules is based on internal optimization and the priority is given to the most favorable improvement of the RF parameters. Finally, when the functional modules are connected to the package pins, the connection lines from the PA, RF signal P and RF signal N pins to the functional modules PA and LNA use special process connection lines with shielding and impedance functions. This connection method is equivalent to Figure 1 Implementation method, but due to the use of special process chips, the cost is slightly higher than Figure 1 Implementation method.

[0036] Reference Figure 3 , 4 , 5. The characteristic parameters of the package are shown in Table 1.

[0037] Table 1

[0038]

Claims

1. An optimized digital wireless communication chip system, characterized in that: It includes a radio frequency controller and its connected EEPROM, data buffer FIFO, SPI interface, IO controller, RSSI detector, IQ demodulator, LNA, mixer, PA, PLL, VCO and QFN16 package; The SPI interface is a logic master SPI interface, which is connected to the RF controller through four lines of CSB, FCSB, SCLK, and SDIO. The IO controller includes logic input and output circuits, which are connected to the chip package pins GPIO1, GPIO2, and GPIO3. The RSSI detector is connected to the RF controller, and the IQ demodulator is connected to the RF controller through the IPC channel. The LNA is directly connected to the antenna input end. The mixer connects the LNA and the VCO through the internal shielded line of the chip. The PA connects the antenna output end and the VCO. The PLL is a digital phase-locked loop with a loop filter. The QFN16 package includes a chip package pin 1 that is an RF signal input P connected to the LNA, and a chip package pin 2 that is an RF The signal input N is connected to the LNA, the chip package pin 3 is the PA output connected to the PA, the chip package pin 4 is the analog VDD, the chip package pin 5 is the analog GND, the chip package pin 6 is the digital GND, the chip package pin 7 is the digital VDD, the chip package pin 8 is GPIO3, the chip package pin 9 is the SPI clock, the chip package pin 10 is the data input and output of the SPI interface, the chip package pin 11 is the SPI access register chip select, the chip package pin 12 is the SPI access FIFO chip select, the chip package pin 13 is the crystal circuit input, the chip package pin 14 is the crystal circuit output, the chip package pin 15 is GPIO2, the chip package pin 16 is GPIO1, the chip package substrate is the analog GND, defined as pin 17, The package pins 1 (RFIP), 2 (RFIN), 3 (PA), and 4 (AVDD) are sequentially placed on the left side of the QFN16 package sheet; The package pins 5 (AGND), 6 (DGND), 7 (DVDD), and 8 (GPIO3) are sequentially placed on the lower side of the QFN16 package sheet; The package pins 9 (SCLK), 10 (SDIO), 11 (CSB), and 12 (FCSB) are sequentially placed on the right side of the QFN16 package sheet; The package pins 13 (XI), 14 (XO), 15 (GPIO2), and 16 (GPIO1) are sequentially placed on the upper side of the QFN16 package sheet; The package pin 17 (GND) is placed at the bottom of the chip; The radio frequency controller uses an FPGA, the EEPROM is an 8*128-bit power-off storage and electrically erasable memory array, and the data cache FIFO is an 8*64-bit RAM; The VCO circuit is composed of a correspondingly connected triode, a varactor diode, a resistor, an inductor, and a capacitor; The PLL is composed of a digital PLL module, a capacitor and a resistor.

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