A memory security detection method and system on chip
By using the detection algorithm of security policy controller and off-chip memory to configure the detection circuit in the memory security detection method, the high power consumption and complexity problems in traditional methods are solved, and the flexibility and low Memory detection of power consumption.
Patent Information
- Application Number
- CN202110448527.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-04-25
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2041-04-25
AI Technical Summary
Traditional memory detection methods cannot be flexibly updated to detect multiple memory failures and attacks, resulting in large system overhead, high power consumption and complex detection circuits and difficult to manage.
Design a memory security detection method, use the security policy controller to receive external detection signals, obtain corresponding detection algorithms from off-chip memory according to the fault or attack identifier, configure the detection circuit to judge memory failure or attack, and realize online configuration and replacement. Reduce power consumption and improve detection coverage.
It realizes detection of multiple memory failures and attacks, reduces power consumption, improves detection efficiency and coverage, and eliminates the need to deploy multiple detection solutions and complex circuits simultaneously.
Smart Images
Figure CN113157509B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of hardware security technology, and in particular to a memory security detection method and a system on chip. Background Art
[0002] With the rapid development of IoT technology, IoT devices are widely used. Users use IoT devices to make life more convenient and fast. IoT devices rely on users to collect their personal information and provide users with various services.
[0003] The system on a chip is the hardware foundation of IoT devices, and memory is an important component of the system on a chip. If the memory fails or is attacked by hardware Trojans, it will cause the function of the IoT device to change, or leak the user's personal information, or even cause losses to the user.
[0004] In order to ensure the security of memory, memory security detection is required to detect faults and issue alarms in a timely manner. However, most traditional memory detection methods cannot be flexibly updated according to different faults and / or attacks, and can only detect a certain type of fault or attack. If a detection scheme for multiple memory faults is to be deployed, the system overhead will be increased, the power consumption will be high, and the multiple detection circuits deployed simultaneously for multiple memory faults and / or attack detections will be complex and difficult to manage.
[0005] Therefore, how to detect multiple memory failures and / or attacks with low power consumption is a technical problem that needs to be solved urgently in this field. Summary of the invention
[0006] In order to solve the above technical problems, the present application provides a memory security detection method and a system on chip, which can detect various memory faults with low power consumption.
[0007] In a first aspect, an embodiment of the present application provides a memory security detection method, which is applied to a system on chip, wherein the system on chip is connected to an off-chip memory; the system on chip includes a security policy controller and a memory to be detected; the security policy controller is used to perform fault and / or attack detection on the memory to be detected, and the security policy controller includes a detection module; the method includes:
[0008] Receiving a detection signal sent from outside the system on chip, the detection signal carrying a to-be-detected fault and / or an attack identifier of the to-be-detected memory;
[0009] According to the fault and / or attack identifier to be detected, a detection algorithm corresponding to the fault and / or attack identifier to be detected is obtained from the off-chip memory; the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifiers, respectively, and different faults and / or attack identifiers correspond to different detection algorithms;
[0010] The detection module is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the to-be-detected fault and / or attack occurs in the to-be-detected memory.
[0011] Optionally, configuring the detection module according to the obtained detection algorithm to obtain a detection circuit includes:
[0012] Decomposing the detection algorithm into a circuit element algorithm and a connection relationship algorithm;
[0013] Obtaining corresponding circuit elements according to the circuit element algorithm configuration;
[0014] The circuit elements are connected according to the connection relationship algorithm to obtain the detection circuit.
[0015] Optionally, the detection algorithm includes a detection circuit bit stream; and obtaining the detection algorithm corresponding to the fault to be detected and / or the attack identifier from the off-chip memory according to the fault to be detected and / or the attack identifier includes:
[0016] Obtaining a detection circuit bit stream corresponding to the to-be-detected fault and / or attack identifier from the off-chip memory according to the to-be-detected fault and / or attack identifier; the detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream;
[0017] The circuit element bit stream is used to configure the corresponding circuit element; the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit;
[0018] The off-chip memory stores detection circuit bit streams corresponding to a plurality of fault and / or attack identifiers, respectively. Different fault and / or attack identifiers correspond to different detection circuit bit streams.
[0019] Optionally, the system on chip further includes a memory wrapper circuit; after configuring the detection module according to the obtained detection algorithm to obtain the detection circuit, and before using the detection circuit to determine whether the to-be-detected memory has the to-be-detected fault and / or attack identifier, the method further includes:
[0020] The address of the memory to be detected is transferred to the address register of the memory wrapper circuit, and after the detection circuit is used to determine whether the memory to be detected has the fault and / or attack to be detected, the address of the memory to be detected is transferred back to the memory to be detected;
[0021] The data of the memory to be detected is transferred into the data register of the memory wrapper circuit, and after the detection circuit is used to determine whether the memory to be detected has the fault and / or attack to be detected, the data of the memory to be detected is transferred back to the memory to be detected.
[0022] Optionally, in the process of using the detection circuit to determine whether the to-be-detected memory has the to-be-detected fault and / or attack, if the system accesses the memory, the method further includes:
[0023] When the memory address accessed by the system is the address of the memory to be detected, the system access is input into the address register and the data register to complete the system access to the memory;
[0024] When the memory address accessed by the system is not the address of the memory to be detected, the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected is suspended, and after the system access is completed, the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected is continued.
[0025] In a second aspect, an embodiment of the present application provides a system on chip for memory security detection, wherein the off-chip system is connected to an off-chip memory, and the system on chip includes: a memory to be detected and a security policy controller; the security policy controller is used to perform fault and / or attack detection on the memory to be detected, and the security policy controller includes a detection module;
[0026] The security policy controller is connected to the memory to be detected;
[0027] The security policy controller is used to receive a detection signal sent from the outside of the on-chip system, the detection signal carries the fault and / or attack identifier to be detected of the memory to be detected, and obtains a detection algorithm corresponding to the fault and / or attack identifier to be detected from an off-chip memory according to the fault and / or attack identifier to be detected, the off-chip memory stores detection algorithms corresponding to a plurality of fault and / or attack identifiers, respectively, and different fault and / or attack identifiers correspond to different detection algorithms, the detection module is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the fault and / or attack to be detected occurs in the memory to be detected.
[0028] Optionally, the security policy controller includes: an internal configuration access port;
[0029] The internal configuration access port is used to decompose the detection algorithm into a circuit element algorithm and a connection relationship algorithm, obtain corresponding circuit elements according to the circuit element algorithm configuration, and connect the circuit elements according to the connection relationship algorithm to obtain the detection circuit.
[0030] Optionally, the security policy controller comprises: a partially reconfigurable controller; the detection algorithm comprises a detection circuit bit stream;
[0031] The partially reconfigurable controller is connected to the internal configuration access port;
[0032] The partially reconfigurable controller is used to obtain a detection circuit bit stream corresponding to the to-be-detected fault and / or attack identifier from the off-chip memory according to the to-be-detected fault and / or attack identifier, wherein the detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream;
[0033] The circuit element bit stream is used to configure the corresponding circuit element; the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit;
[0034] The off-chip memory stores detection circuit bit streams corresponding to a plurality of fault and / or attack identifiers, respectively. Different fault and / or attack identifiers correspond to different detection circuit bit streams.
[0035] Optionally, the system on chip further comprises: a memory wrapper circuit; the memory wrapper circuit comprises an address register and a data register;
[0036] The memory wrapper circuit is connected to the security policy controller;
[0037] The address register is used to store the address of the memory to be detected;
[0038] The data register is used to store the data of the memory to be detected.
[0039] Optionally, the security policy controller includes: a detection process controller;
[0040] The detection process controller is used for inputting the system access into the address register and the data register to complete the system access to the memory when the system accesses the memory and the memory address accessed by the system is the address of the memory to be detected;
[0041] The detection process controller is also used to suspend the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected when the system accesses the memory and the memory address accessed by the system is not the address of the memory to be detected. After the system access ends, the detection circuit is continued to be used to determine whether the memory to be detected has the fault and / or attack to be detected.
[0042] Compared with the prior art, this application has at least the following advantages:
[0043] The present application provides a memory security detection method and a system on chip, wherein the system on chip includes a security policy controller and a memory to be detected, the security policy controller is used to perform fault detection on the memory to be detected, and the security policy controller includes a detection module. The security policy controller can receive a detection signal sent from the outside of the system on chip, the detection signal carries the fault to be detected and / or attack identification of the memory to be detected, and obtains a detection algorithm corresponding to the fault to be detected and / or attack identification from an off-chip memory according to the fault to be detected and / or attack identification, the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifications, respectively, different faults and / or attack identifications correspond to different detection algorithms, the detection module is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the fault to be detected and / or attack identification appears in the memory to be detected. The security detection of the corresponding faults and / or attack identifications of the memory to be detected is realized, so there is no need to deploy multiple memory fault detection schemes in the system at the same time, and there is no need to deploy multiple complex detection circuits at the same time. They can be replaced through online configuration, which is equivalent to realizing different functions in one resource space. According to the different detection signals, the corresponding detection algorithm can be called from the off-chip memory to configure the corresponding detection circuit, thereby reducing power consumption, and configuring different detection methods can improve detection coverage, among which the specific detection collision mechanism improves detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0045] Figure 1 A flow chart of a memory security detection method provided by an embodiment of the present application is shown;
[0046] Figure 2 A framework diagram of a system on chip provided by an embodiment of the present application is shown;
[0047] Figure 2A An internal structure design diagram of a security policy controller provided in an embodiment of the present application is shown;
[0048] Figure 3 A framework diagram of another system on chip provided by an embodiment of the present application is shown;
[0049] Figure 4 A framework diagram of another system on chip provided by an embodiment of the present application is shown;
[0050] Figure 4A The internal structure design diagram of another security policy controller provided in an embodiment of the present application is shown;
[0051] Figure 5 A framework diagram of another system on chip provided by an embodiment of the present application is shown;
[0052] Figure 5A An internal structure diagram of a memory wrapper circuit provided by an embodiment of the present application is shown;
[0053] Figure 6 A flowchart of a complete memory security detection provided by an embodiment of the present application is shown. DETAILED DESCRIPTION
[0054] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.
[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0056] As described in the background technology, with the rapid development of Internet of Things technology, Internet of Things devices are widely used. Users use Internet of Things devices to make life convenient and fast. Internet of Things devices rely on users to collect user personal information and provide users with various services.
[0057] The system on a chip is the hardware foundation of IoT devices, and memory is an important component of the system on a chip. If the memory fails or is attacked by hardware Trojans, it will cause the function of the IoT device to change, or leak the user's personal information, or even cause losses to the user.
[0058] In order to ensure the security of memory, memory security detection is required to detect faults and issue alarms in a timely manner. However, most traditional memory detection methods cannot be flexibly updated according to different faults and / or attacks, and can only detect a certain type of fault or attack. If a detection scheme for multiple memory faults is to be deployed, the system overhead will be increased, the power consumption will be high, and the multiple detection circuits deployed simultaneously for multiple memory fault detections will be complex and difficult to manage.
[0059] Therefore, how to detect multiple memory failures and / or attacks with low power consumption is a technical problem that needs to be solved urgently in this field.
[0060] Based on this, the present application provides a memory security detection method and a system on chip, the system on chip includes a security policy controller and a memory to be detected, the security policy controller is used to perform fault detection on the memory to be detected, and the security policy controller includes a detection module. The security policy controller can receive a detection signal sent from the outside of the system on chip, the detection signal carries the fault to be detected and / or attack identification of the memory to be detected, and obtains a detection algorithm corresponding to the fault to be detected and / or attack identification from an off-chip memory according to the fault to be detected and / or attack identification, the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifications, respectively, different faults and / or attack identifications correspond to different detection algorithms, the detection module is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the fault to be detected and / or attack identification appears in the memory to be detected. The security detection of the corresponding faults and / or attack identifications of the memory to be detected is realized, so there is no need to deploy multiple memory fault detection schemes in the system at the same time, and there is no need to deploy multiple complex detection circuits at the same time. They can be replaced through online configuration, which is equivalent to realizing different functions in one resource space. According to the different detection signals, the corresponding detection algorithm can be called from the off-chip memory to configure the corresponding detection circuit, thereby reducing power consumption, and configuring different detection methods can improve detection coverage, among which the specific detection collision mechanism improves detection efficiency.
[0061] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
[0062] Exemplary Methods
[0063] refer to Figure 1 As shown, it is a flowchart of a memory security detection method provided in an embodiment of the present application, comprising the following steps:
[0064] S01: receiving a detection signal sent from outside the system on chip, wherein the detection signal carries a failure to be detected and / or an attack identifier of a memory to be detected.
[0065] refer to Figure 2 As shown, it is a framework diagram of the system on chip provided in an embodiment of the present application. A memory security detection method provided in an embodiment of the present application is applied to a system on chip 201. The system on chip refers to a complete system integrated on a single chip. The system on chip 201 is connected to an off-chip memory 202. The system on chip 201 may include a security policy controller 203 and a memory to be detected 204. The security policy controller 203 is used to perform fault and / or attack detection on the memory to be detected. The security policy controller includes a detection module 205.
[0066] The security policy controller 203 provided in the embodiment of the present application can receive a detection signal sent from the outside of the system on chip 201, and the detection signal can carry a fault to be detected and / or an attack identifier of the memory to be detected. It should be noted that the embodiment of the present application does not specifically limit the fault to be detected and / or the attack identifier. For example, the detection fault identifier can be, for example, an address decoding fault (Address Decoder Fault, AF), a stuck-at fault (Stuck-at Fault, SAF), a transition fault (Transition Fault, TF) and / or a coupling fault (Coupling Fault, CF), etc.
[0067] Optional, see Figure 2A As shown, the security policy controller 203 may further include a partially reconfigurable controller 2031 , and the partially reconfigurable controller 2031 receives the detection signal. The partially reconfigurable controller 2031 may also send the detection signal to the off-chip memory 202 .
[0068] S02: obtaining a detection algorithm corresponding to the fault and / or attack identifier to be detected from the off-chip memory according to the fault and / or attack identifier to be detected; the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifiers, respectively, and different faults and / or attack identifiers correspond to different detection algorithms;
[0069] refer to Figure 3 As shown, when the security policy controller 203 receives a detection signal sent from the outside of the on-chip system 201, since the detection signal carries the fault to be detected and / or attack identifier of the memory to be detected, a detection algorithm corresponding to the fault and / or attack identifier to be detected can be obtained from the off-chip memory 202 according to the fault and / or attack identifier to be detected, wherein the off-chip memory 202 stores detection algorithms corresponding to a plurality of faults and / or attack identifiers, and different faults and / or attack identifiers correspond to different detection algorithms.
[0070] Optional, see Figure 2AAs shown, the partially reconfigurable controller 2031 in the security policy controller 203 may also receive a detection algorithm corresponding to the fault to be detected and / or the attack identifier sent by the off-chip memory 202 .
[0071] Optionally, the security policy controller 203 can send a detection signal to the communication bus 206, and the communication bus 206 forwards the detection signal to the central processing unit 207, and the central processing unit 207 forwards the detection signal to the off-chip memory 202. When the off-chip memory 202 receives the detection signal, the corresponding detection algorithm stored therein is returned to the security policy controller 203 through the central processing unit 207 and the communication bus 206 according to the fault to be detected and / or attack identification carried by the detection signal.
[0072] Optionally, the detection algorithm may include a detection circuit bit stream, and the detection circuit bit stream corresponding to the fault to be detected and / or the attack identifier may be obtained from the off-chip memory 202 according to the fault to be detected and / or the attack identifier, and the detection circuit bit stream may include a circuit element bit stream and a connection relationship bit stream. The detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream, the circuit element bit stream is used to configure the corresponding circuit element, and the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit.
[0073] S03: configuring the detection module according to the obtained detection algorithm to obtain a detection circuit, and using the detection circuit to determine whether the memory to be detected has a fault to be detected and / or an attack to be detected.
[0074] In the examples of this application, refer to Figure 4 As shown, after the security policy controller 203 obtains the detection algorithm, the detection module 205 can be configured according to the detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the memory 204 to be detected has a fault and / or attack to be detected.
[0075] Optional, see Figure 4A As shown, after receiving the detection algorithm sent by the off-chip memory 202, the partially reconfigurable controller 2031 in the security policy controller 203 can transmit the detection algorithm to the internal configuration access port 2032. The internal configuration access port 2032 can configure the detection module 205 according to the detection algorithm to obtain a detection circuit. The detection module 205, see Figure 4A , that is, the reconfigurable partition 2033, that is, the internal configuration access port 2032 can configure the reconfigurable partition 2033 according to the detection algorithm to obtain the detection circuit, and the reconfigurable partition 2033 uses the detection circuit to determine whether the memory to be detected has a fault and / or attack to be detected, that is, after the detection circuit is configured, the memory to be detected 204 is performed with fault and attack detection.
[0076] Optionally, the security policy controller 203 may also include a detection process controller 2034, which can output a detection control signal according to the current detection state and system state to assist the reconfigurable partition 2033 to complete the detection task without reducing system performance as much as possible.
[0077] Optionally, the security policy controller 203 may also include an error recording register 2035, which may be responsible for recording faults and attacks discovered during the detection of the memory to be detected 204, and may notify the central processor 207 of the discovered faults and attacks through the communication bus 206 so that the central processor 207 may take corresponding defensive measures.
[0078] Optionally, the detection module is configured according to the obtained detection algorithm to obtain the detection circuit. Specifically, the detection algorithm can be decomposed into a circuit element algorithm and a connection relationship algorithm. The corresponding circuit elements are configured according to the circuit element algorithm, and the circuit elements are connected according to the connection relationship algorithm to obtain the detection circuit.
[0079] In addition, in the embodiments of the present application, optionally, see Figure 5 As shown, the system on chip 201 may also include a memory wrapper circuit 208, which is wrapped around the outside of the memory to be detected 204 and is responsible for receiving control signals from the security policy controller 203, read and write detection information of the security policy controller 203 and read and write information of the communication bus 206, and selecting the read and write information of the security policy controller or the bus according to the detection and operation status of the system, and inputting it into the wrapped memory to be detected 204.
[0080] Specifically, the memory wrapper circuit 208 may include a memory wrapper control circuit 2081, which may receive a control signal from the security policy controller 203, and output a corresponding routing selection signal according to the input control signal and the internal state. The memory wrapper control circuit 2081 may include an address register 20811, which may store the address information of the memory to be detected; the memory wrapper circuit 208 may also include a memory access selection module 2082, which may receive a routing selection signal from the memory wrapper control circuit 2081, and select the memory access information of the communication bus or the security policy controller to enter the memory according to the input selection signal. The memory access selection module 2082 may include a data register 20822, which is responsible for storing the backed-up data in the memory to be detected.
[0081] Since the March algorithm is generally used to detect the memory to be detected, specifically, the MarchC-algorithm has a moderate time complexity and can detect multiple and / or attacks, therefore, optionally, the embodiment of the present application can adopt the MarchC-algorithm, which writes different values to different memory cells and reads them out to compare with the expected values to determine whether there is a fault and / or attack in the memory cell, that is, in the process of detecting the memory to be detected, the value in the memory to be detected will be changed. It should be noted that the embodiment of the present application does not specifically limit the memory detection algorithm, and those skilled in the art can set it according to the actual situation.
[0082] Therefore, after configuring the detection module 205 according to the obtained detection algorithm to obtain the detection circuit, before using the detection circuit to determine whether the memory to be detected has a fault to be detected and / or an attack to be detected, see Figure 5A As shown, the address of the memory to be detected 204 can also be transferred to the address register 20811 of the memory wrapper circuit 208, and after the detection circuit is used to determine whether the memory to be detected has the fault to be detected and / or the attack, the address of the memory to be detected 204 is transferred back to the memory to be detected 204; the data of the memory to be detected 204 is transferred to the data register 20822 of the memory wrapper circuit 208, and after the detection circuit is used to determine whether the memory to be detected 204 has the fault to be detected and / or the attack, the data of the memory to be detected is transferred back to the memory to be detected 204.
[0083] Optionally, when using the detection circuit to determine whether the memory to be detected 204 has a fault to be detected and / or an attack, if the system accesses the memory, the address of the memory accessed by the system can be determined first. When the memory address accessed by the system is the address of the memory to be detected 204, the system access is input into the address register 20811 and the data register 20822 to complete the system access to the memory; when the memory address accessed by the system is not the address of the memory to be detected, the use of the detection circuit to determine whether the memory to be detected 204 has a fault to be detected and / or an attack is suspended, and after the system access is completed, the detection circuit is continued to be used to determine whether the memory to be detected 204 has a fault to be detected and / or an attack. This can prevent the loss of the original data before the detection in the memory to be detected.
[0084] Optionally, in an embodiment of the present application, when it is detected that the memory 204 to be detected has a fault and / or attack to be detected, an alarm can be issued. It should be noted that the embodiment of the present application does not specifically limit the specific method of the alarm, and technical personnel in this field can set it according to actual conditions.
[0085] Optionally, when the on-chip system does not receive a detection signal from outside the chip within a preset period of time, it can automatically perform a memory security check, thereby promptly detecting faults, notifying the central processor and taking corresponding defensive measures to ensure the safe operation of the memory.
[0086] Optionally, in the embodiment of the present application, the process of performing a complete memory detection process can be referred to Figure 6 As shown:
[0087] (1) Idle state IDLE: The memory to be tested wrapped in the memory wrapper circuit responds to the system access sent from the communication bus, the memory wrapper control circuit selects the bus signal to the path of the memory to be tested, and the system performs normal operation;
[0088] (2) Backup state Copy_MEM: The security policy controller sends a request detection signal, and the state machine enters the Copy_MEM state, writes the address information of the memory to be detected into the address register, and allows the security policy controller to read the value in the memory to be detected;
[0089] (3) Write data state Write_Reg: After the data in the memory to be detected is successfully read out, the security policy controller sends a request transfer signal, and the state machine enters the Write_Reg state, allowing the security policy controller to transfer the data in the read memory unit to be detected to the data register;
[0090] (4) Checking state: After the data in the memory to be tested is transferred to the data register, the security policy controller sends a signal requesting formal testing, and the state machine enters the Checking state, allowing the security policy controller to input testing information into the tested unit of the memory to be tested;
[0091] (5) Checking collision processing state 1Check_Reg: During the detection process of the security policy controller, if the memory wrapper circuit receives a system access signal from the communication bus, it will trigger the jump of the state machine. First, it determines whether the address accessed by the system is the address stored in the address register. If it is equal, the state machine enters the Check_Reg state, and the state machine control circuit redirects the system access signal sent by the communication bus to the data register, that is, it selects the path from the communication bus signal to the data register, and continues to select the path from the signal sent by the security policy control to the memory to be detected. This operation allows the memory wrapper circuit to receive and process the system access signal while the memory to be detected is being detected, thereby minimizing the impact of memory detection on system performance. When the memory wrapper circuit responds to the system access signal, the state machine jumps back to the Checking state from the Check_Reg state;
[0092] (6) Checking collision processing state 2 Check_MEM: After the memory wrapper circuit receives the system access signal from the communication bus, if it is determined that the system access address is not equal to the address stored in the address register, the state machine jumps from the Checking state to the Check_MEM state. The memory wrapper circuit selects the path of the system access signal to the memory to be tested, sends the system access signal of the communication bus to the memory to be tested, and requests the security policy controller to temporarily suspend the memory security test. The security policy controller receives the request to terminate the signal, saves the test scene and terminates the test. When the memory wrapper circuit responds to the system access signal, the state machine jumps from the Check_MEM state back to the Checking state;
[0093] (7) Recopy_Reg: When the memory security check is completed, the security policy controller sends a check completion signal, and the state machine jumps from the Checking state to the Recopy_Reg state, allowing the security policy controller to read the data in the data register;
[0094] (8) Write_MEM: When the data in the data register is successfully read out, the security policy controller sends a write-back request signal, and the state machine enters the Write_MEM state, allowing the security policy controller to write the read data back to the memory to be detected;
[0095] (10) Idle state IDLE: When the data is written back, the security policy controller sends a write-back completion signal, the state machine enters the IDLE state, and the system performs normal operations.
[0096] The present application provides a memory security detection method, wherein the system on chip includes a security policy controller and a memory to be detected, the security policy controller is used to perform fault detection on the memory to be detected, and the security policy controller includes a detection module. The security policy controller can receive a detection signal sent from the outside of the system on chip, the detection signal carries the fault type to be detected and / or the attack identifier of the memory to be detected, and obtains a detection algorithm corresponding to the fault type to be detected and / or the attack identifier from the off-chip memory according to the fault type to be detected and / or the attack identifier, the off-chip memory stores detection algorithms corresponding to multiple fault types and / or attack identifiers, and different fault types and / or attack identifiers correspond to different detection algorithms, and the detection module is configured to obtain a detection circuit according to the obtained detection algorithm, and the detection circuit is used to determine whether the fault type to be detected and / or the attack identifier appear in the memory to be detected. The security detection of the corresponding fault type and / or attack identifier of the memory to be detected is realized, so that there is no need to deploy multiple memory fault detection schemes in the system at the same time, and there is no need to deploy multiple complex detection circuits at the same time, and they can be replaced by online configuration, which is equivalent to realizing different functions in a resource space, and calling the corresponding detection algorithm from the off-chip memory according to the different detection signals to configure the corresponding detection circuit, which reduces power consumption and improves detection efficiency. This reduces power consumption, and configuring different detection methods improves detection coverage, among which the specific collision detection mechanism improves detection efficiency.
[0097] Exemplary System on Chip
[0098] See also Figure 2 , is a system on chip for memory security detection provided by an embodiment of the present application, the system on chip 201 is connected to an off-chip memory 202, the system on chip 201 comprises: a memory to be detected 204 and a security policy controller 203; the security policy controller 203 is used to perform fault and / or attack detection on the memory to be detected 204, and the security policy controller 203 comprises a detection module 205;
[0099] The security policy controller 203 is connected to the memory to be detected 204;
[0100] The security policy controller 203 is used to receive a detection signal sent from the outside of the on-chip system 201, the detection signal carries the fault to be detected and / or attack identification of the memory to be detected, and obtains a detection algorithm corresponding to the fault to be detected and / or attack identification from the off-chip memory 202 according to the fault to be detected and / or attack identification, the off-chip memory 202 stores detection algorithms corresponding to multiple fault and / or attack identifications, different fault and / or attack identifications correspond to different detection algorithms, the detection module 205 is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the fault to be detected and / or attack occurs in the memory to be detected 204.
[0101] Optionally, the security policy controller 203 includes: an internal configuration access port;
[0102] The internal configuration access port is used to decompose the detection algorithm into a circuit element algorithm and a connection relationship algorithm, obtain corresponding circuit elements according to the circuit element algorithm configuration, and connect the circuit elements according to the connection relationship algorithm to obtain the detection circuit.
[0103] Optionally, the security policy controller 203 includes: a partially reconfigurable controller; the detection algorithm includes a detection circuit bit stream;
[0104] The partially reconfigurable controller is connected to the internal configuration access port;
[0105] The partially reconfigurable controller is used to obtain a detection circuit bit stream corresponding to the to-be-detected fault and / or attack identifier from the off-chip memory according to the to-be-detected fault and / or attack identifier, wherein the detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream;
[0106] The circuit element bit stream is used to configure the corresponding circuit element; the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit;
[0107] The off-chip memory stores detection circuit bit streams corresponding to a plurality of fault and / or attack identifiers, respectively. Different fault and / or attack identifiers correspond to different detection circuit bit streams.
[0108] Optionally, the system on chip 201 further includes: a memory wrapper circuit; the memory wrapper circuit includes an address register and a data register;
[0109] The memory wrapper circuit is connected to the security policy controller;
[0110] The address register is used to store the address of the memory to be detected;
[0111] The data register is used to store the data of the memory to be detected.
[0112] Optionally, the security policy controller 203 includes: a detection process controller;
[0113] The detection process controller is used for inputting the system access into the address register and the data register to complete the system access to the memory when the system accesses the memory and the memory address accessed by the system is the address of the memory to be detected;
[0114] The detection process controller is also used to suspend the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected when the system accesses the memory and the memory address accessed by the system is not the address of the memory to be detected. After the system access ends, the detection circuit is continued to be used to determine whether the memory to be detected has the fault and / or attack to be detected.
[0115] The present application provides a memory security detection system on chip, the system on chip includes a security policy controller and a memory to be detected, the security policy controller is used to perform fault detection on the memory to be detected, and the security policy controller includes a detection module. The security policy controller can receive a detection signal sent from the outside of the system on chip, the detection signal carries the fault to be detected and / or attack identification of the memory to be detected, and obtains a detection algorithm corresponding to the fault to be detected and / or attack identification from an off-chip memory according to the fault to be detected and / or attack identification, the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifications, different faults and / or attack identifications correspond to different detection algorithms, the detection module is configured according to the obtained detection algorithm to obtain a detection circuit, and the detection circuit is used to determine whether the fault to be detected and / or attack identification appears in the memory to be detected. The security detection of the corresponding faults and / or attack identifications of the memory to be detected is realized, so there is no need to deploy multiple memory fault detection schemes in the system at the same time, and there is no need to deploy multiple complex detection circuits at the same time. They can be replaced through online configuration, which is equivalent to realizing different functions in one resource space. According to the different detection signals, the corresponding detection algorithm can be called from the off-chip memory to configure the corresponding detection circuit, thereby reducing power consumption, and configuring different detection methods can improve detection coverage, among which the specific detection collision mechanism improves detection efficiency.
[0116] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system-on-chip embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0117] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.
Claims
1. A memory security detection method, characterized in that: Applied to a system on chip, the system on chip is connected to an off-chip memory; the system on chip includes a security policy controller and a memory to be detected; the security policy controller is used to perform fault and / or attack detection on the memory to be detected, and the security policy controller includes a detection module; the method includes: Receiving a detection signal sent from outside of the system on chip, the detection signal carrying a to-be-detected fault and / or an attack identifier of the to-be-detected memory; According to the fault and / or attack identifier to be detected, a detection algorithm corresponding to the fault and / or attack identifier to be detected is obtained from the off-chip memory; the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifiers, respectively, and different faults and / or attack identifiers correspond to different detection algorithms; Configuring the detection module according to the obtained detection algorithm to obtain a detection circuit; The step of configuring the detection module according to the obtained detection algorithm to obtain the detection circuit includes: decomposing the detection algorithm into a circuit element algorithm and a connection relationship algorithm, and obtaining corresponding circuit elements according to the circuit element algorithm configuration; and connecting the circuit elements according to the connection relationship algorithm to obtain the detection circuit; The detection circuit is used to determine whether the memory to be detected has the fault and / or attack to be detected.
2. The method according to claim 1, characterized in that The detection algorithm includes a detection circuit bit stream; the detection algorithm corresponding to the fault to be detected and / or the attack identifier to be detected is obtained from the off-chip memory according to the fault to be detected and / or the attack identifier, including: Obtaining a detection circuit bit stream corresponding to the to-be-detected fault and / or attack identifier from the off-chip memory according to the to-be-detected fault and / or attack identifier; the detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream; The circuit element bit stream is used to configure the corresponding circuit element; the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit; The off-chip memory stores detection circuit bit streams corresponding to a plurality of fault and / or attack identifiers, respectively. Different fault and / or attack identifiers correspond to different detection circuit bit streams.
3. The method according to claim 1 or 2, characterized in that: The system on chip further includes a memory wrapper circuit; after configuring the detection module according to the obtained detection algorithm to obtain the detection circuit, and before using the detection circuit to determine whether the to-be-detected memory has the to-be-detected fault and / or attack, the method further includes: The address of the memory to be detected is transferred to the address register of the memory wrapper circuit, and after the detection circuit is used to determine whether the memory to be detected has the fault and / or attack to be detected, the address of the memory to be detected is transferred back to the memory to be detected; The data of the memory to be detected is transferred into the data register of the memory wrapper circuit, and after the detection circuit is used to determine whether the memory to be detected has the fault and / or attack to be detected, the data of the memory to be detected is transferred back to the memory to be detected.
4. The method according to claim 3, characterized in that In the process of using the detection circuit to determine whether the to-be-detected memory has the to-be-detected fault and / or attack, if the system accesses the memory, the method further includes: When the memory address accessed by the system is the address of the memory to be detected, the system access is input into the address register and the data register to complete the system access to the memory; When the memory address accessed by the system is not the address of the memory to be detected, the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected is suspended, and after the system access is completed, the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected is continued.
5. A system on chip for memory security detection, characterized in that: The system on chip is connected to an off-chip memory, and the system on chip includes: a memory to be detected and a security policy controller; the security policy controller is used to perform fault and / or attack detection on the memory to be detected, and the security policy controller includes a detection module; The security policy controller is connected to the memory to be detected; The security policy controller is used to receive a detection signal sent from the outside of the system on chip, the detection signal carries the fault to be detected and / or attack identifier of the memory to be detected, obtain a detection algorithm corresponding to the fault to be detected and / or attack identifier from the off-chip memory according to the fault to be detected and / or attack identifier, the off-chip memory stores detection algorithms corresponding to a plurality of faults and / or attack identifiers, different faults and / or attack identifiers correspond to different detection algorithms, configure the detection module according to the obtained detection algorithm to obtain a detection circuit, and use the detection circuit to determine whether the fault to be detected and / or attack occurs in the memory to be detected; Wherein, the security policy controller includes: an internal configuration access port; The internal configuration access port is used to decompose the detection algorithm into a circuit element algorithm and a connection relationship algorithm, obtain corresponding circuit elements according to the circuit element algorithm configuration, and connect the circuit elements according to the connection relationship algorithm to obtain the detection circuit.
6. The system on chip according to claim 5, characterized in that: The security policy controller includes: a partially reconfigurable controller; the detection algorithm includes a detection circuit bit stream; The partially reconfigurable controller is connected to the internal configuration access port; The partially reconfigurable controller is used to obtain a detection circuit bit stream corresponding to the to-be-detected fault and / or attack identifier from the off-chip memory according to the to-be-detected fault and / or attack identifier, wherein the detection circuit bit stream includes a circuit element bit stream and a connection relationship bit stream; The circuit element bit stream is used to configure the corresponding circuit element; the connection relationship bit stream is used to connect the circuit elements to obtain the detection circuit; The off-chip memory stores detection circuit bit streams corresponding to a plurality of fault and / or attack identifiers, respectively. Different fault and / or attack identifiers correspond to different detection circuit bit streams.
7. The system on chip according to claim 5 or 6, characterized in that: The system on chip also includes: a memory wrapper circuit; the memory wrapper circuit includes an address register and a data register; The memory wrapper circuit is connected to the security policy controller; The address register is used to store the address of the memory to be detected; The data register is used to store the data of the memory to be detected.
8. The system on chip according to claim 7, characterized in that: The security policy controller includes: a detection process controller; The detection process controller is used for inputting the system access into the address register and the data register to complete the system access to the memory when the system accesses the memory and the memory address accessed by the system is the address of the memory to be detected; The detection process controller is also used to, when the system accesses the memory, when the memory address accessed by the system is not the address of the memory to be detected, suspend the use of the detection circuit to determine whether the memory to be detected has the fault and / or attack identification to be detected, and after the system access ends, continue to use the detection circuit to determine whether the memory to be detected has the fault and / or attack to be detected.