Hybrid Memory Cell

Abstract

The present invention discloses a hybrid memory cell, comprising a read / write element group, a storage circuit and a selection circuit. The read / write element group is electrically coupled to a word line and a two-bit line, wherein the two-bit lines transmit two data signals respectively. The storage circuit is electrically coupled to the read / write element group. The selection circuit is electrically coupled to the read / write element group and the storage circuit, and is used to control the storage circuit to present a volatile storage mode or a non-volatile storage mode according to a selection voltage.

Description

Technical Field

[0001] The present invention relates to a memory cell, and more particularly to a hybrid memory cell. Background Art

[0002] Static random access memory (SRAM) is a type of random access memory. The so-called static means that the data stored in it can be kept constant as long as the power is kept on. In contrast, the data stored in dynamic random access memory (DRAM) will be updated periodically. Compared with DRAM, SRAM has advantages such as fast speed and low power consumption. However, when the power supply stops, whether it is SRAM or DRAM, the data stored will disappear, so it is called volatile memory. Summary of the invention

[0003] In view of the above, the present invention provides a hybrid memory cell, which can selectively provide a volatile storage mode or a non-volatile storage mode through a special circuit architecture.

[0004] A hybrid memory cell according to an embodiment of the present invention comprises a read / write element group, a storage circuit and a selection circuit. The read / write element group is electrically coupled to a word line and a two-bit line, wherein the two-bit lines transmit two data signals respectively. The storage circuit is electrically coupled to the read / write element group. The selection circuit is electrically coupled to the read / write element group and the storage circuit, and is used to control the storage circuit to present a volatile storage mode or a non-volatile storage mode according to a selection voltage.

[0005] With the above structure, the hybrid memory unit disclosed in this case can be set to a volatile storage mode or a non-volatile storage mode as required, and has high adaptability. In addition, the memory composed of the hybrid memory units disclosed in this case can be matched with a variety of computing devices or other electronic devices with different requirements for storage modes by adjusting the setting of the selection voltage corresponding to each memory unit, without changing the circuit design of the memory, thereby reducing the development cost.

[0006] The above description of the present disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the claims of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of a hybrid memory cell according to an embodiment of the present invention.

[0008] Figure 2It is a schematic diagram of electrical coupling terminals of a hybrid memory cell according to an embodiment of the present invention.

[0009] Figure 3 FIG. 4 is a schematic diagram of an equivalent circuit of a volatile storage mode of a hybrid memory cell according to an embodiment of the present invention.

[0010] Figure 4 It is a schematic diagram of an equivalent circuit of a non-volatile storage mode of a hybrid memory cell according to an embodiment of the present invention.

[0011] Figure 5 is a circuit diagram of a hybrid memory cell according to another embodiment of the present invention.

[0012] Description of reference numerals:

[0013] 1 Hybrid Memory Cell

[0014] 11 Storage circuit

[0015] 13. Selecting the circuit

[0016] 15 Read and write component group

[0017] 17 Controller

[0018] R1 First variable resistor

[0019] R2 Second variable resistor

[0020] M1 first transistor

[0021] M2 Second transistor

[0022] M3 The third transistor

[0023] M4 The fourth transistor

[0024] M5 Fifth transistor

[0025] M6 Sixth transistor

[0026] BL1 First line

[0027] BL2 Second bit line

[0028] WL Character Line

[0029] VC control voltage

[0030] VSL Select voltage

[0031] n11~n61 First end

[0032] n12~n62 Second end

[0033] n13~n63 Control terminal DETAILED DESCRIPTION

[0034] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the contents, claims and drawings disclosed in this specification, any person skilled in the art can easily understand the relevant purposes and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

[0035] The present invention proposes a mixed-mode memory cell that can operate in multiple storage modes, including a volatile storage mode and a non-volatile storage mode. Figure 1 and Figure 2 , Figure 1 FIG. 1 is a circuit diagram of a hybrid memory cell 1 according to an embodiment of the present invention. Figure 2 A plurality of electrical coupling terminals of the hybrid memory cell 1 are exemplarily illustrated.

[0036] The hybrid memory cell 1 includes a storage circuit 11, a selection circuit 13 and a read / write element group 15. The storage circuit 11 can present a volatile storage mode or a non-volatile storage mode according to the electrical coupling status of the internal elements, that is, it can store data temporarily or permanently, wherein the composition and coupling relationship of the internal elements will be described later. In the volatile storage mode, when the power supplied to the hybrid storage cell 1 is interrupted, the data originally stored in the storage circuit 11 will disappear; and in the non-volatile storage mode, when the power supplied to the hybrid storage cell 1 is interrupted, the data stored in the storage circuit 11 will not disappear. The selection circuit 13 is electrically coupled to the storage circuit 11, and is used to control the electrical coupling status of the internal elements of the aforementioned storage circuit 11 according to the selection voltage VSL, so as to control the storage circuit 11 to present a volatile storage mode or a non-volatile storage mode. The read / write element group 15 is electrically coupled to the storage circuit 11 and the selection circuit 13, and is used to be controlled by the word line WL to transmit two data signals from two bit lines (hereinafter referred to as the first bit line BL1 and the second bit line BL2) to the storage circuit 11. The storage circuit 11 can be controlled by the selection circuit 13 as described above to store the data signals from the first and second bit lines BL1 and BL2 in a volatile storage mode or a non-volatile storage mode.

[0037] Let's further explain the components contained in each circuit, such as Figure 1As shown, the storage circuit 11 includes two variable resistors, hereinafter referred to as the first variable resistor R1 and the second variable resistor R2, and includes two transistors, hereinafter referred to as the first transistor M1 and the second transistor M2. The first and second variable resistors R1 and R2 are used as pull-up elements, and the first transistor M1 and the second transistor M2 are used as pull-down elements. In particular, the first and second variable resistors R1 and R2 can each include a phase change element or a resistive variable element. The phase change element can be composed of a phase change material (PCM) and a conductive material (such as a metal), and the two are structurally close. When a high current passes through the conductive material, the conductive material will heat up the phase change material, and the phase state of the phase change material can be adjusted accordingly. When the phase change material is in an amorphous state, the resistance of the resistor will be higher than the resistance when the phase change material is in a crystalline state. The first and second transistors M1 and M2 can be metal oxide semiconductor field effect transistors, especially N-type metal oxide semiconductor field effect transistors (NMOS). The resistive switching element is, for example, an element generally constituting a resistive random-access memory (RRAM).

[0038] The selection circuit 13 includes a third transistor M3 and a fourth transistor M4, wherein the third and fourth transistors M3 and M4 may be metal oxide semiconductor field effect transistors, and the present invention does not limit them to be N-type or P-type. As mentioned above, the selection circuit 13 can control the electrical coupling state of the internal components of the storage circuit 11 according to the selection voltage VSL. Further, the selection circuit 13 can control the electrical coupling state between the first and second variable resistors R1 and R2 of the storage circuit 11 and the first and second transistors M1 and M2 to be conductive or non-conductive according to the selection voltage VSL. The read-write element group 15 includes a fifth transistor M5 and a sixth transistor M6, which are controlled by the word line WL to transmit data signals from the first and second bit lines BL1 and BL2 respectively. The fifth and sixth transistors M5 and M6 may be metal oxide semiconductor field effect transistors, in particular, N-type metal oxide semiconductor field effect transistors (NMOS).

[0039] like Figure 1 and Figure 2 As shown, each resistor has two terminals, and each transistor has three terminals. For the convenience of explanation, Figure 2The three terminals of the first transistor M1 are respectively a first terminal n11, a second terminal n12 and a control terminal n13; the three terminals of the second transistor M2 are respectively a first terminal n21, a second terminal n22 and a control terminal n23; the three terminals of the third transistor M3 are respectively a first terminal n31, a second terminal n32 and a control terminal n33; the three terminals of the fourth transistor M4 are respectively a first terminal n41, a second terminal n42 and a control terminal n43; the three terminals of the fifth transistor M5 are respectively a first terminal n51, a second terminal n52 and a control terminal n53; and the three terminals of the sixth transistor M6 are respectively a first terminal n61, a second terminal n62 and a control terminal n63.

[0040] The following is based on Figure 2 To further illustrate the electrical coupling relationship of the internal components of the storage circuit 11, as shown in the figure, the two ends of the first variable resistor R1 of the storage circuit 11 are respectively used to receive a control voltage VC and electrically coupled to the control terminal n23 of the second transistor M2; the two ends of the second variable resistor R2 are respectively used to receive the control voltage VC and electrically coupled to the control terminal n13 of the first transistor M1. The first variable resistor R1 and the second variable resistor R2 can be electrically coupled to two voltage sources that can provide the control voltage VC, or electrically coupled to the same voltage source, which is not limited by the present invention. In addition, the second ends n12 and n22 of the first and second transistors M1 and M2 are grounded.

[0041] The electrical coupling relationship between the storage circuit 11 and the selection circuit 13 is further described. The first terminal n31 of the third transistor M3 of the selection circuit 13 is electrically coupled to one terminal of the first variable resistor R1 of the storage circuit 11 and the control terminal n23 of the second transistor M2; the second terminal n32 of the third transistor M3 of the selection circuit 13 is coupled to the first terminal n11 of the first transistor M1 of the storage circuit 11; and the control terminal n33 of the third transistor M3 of the selection circuit 13 is used to receive the selection voltage VSL. Symmetrical to the coupling relationship between the third transistor M3 and the elements in the storage circuit 11, the first terminal n41 of the fourth transistor M4 of the selection circuit 13 is electrically coupled to one terminal of the second variable resistor R2 of the storage circuit 11 and the control terminal n13 of the first transistor M1; the second terminal n42 of the fourth transistor M4 of the selection circuit 13 is coupled to the first terminal n21 of the second transistor M2 of the storage circuit 11; and the control terminal n43 of the fourth transistor M4 of the selection circuit 13 is also used to receive the selection voltage VSL. The control terminal n33 of the third transistor M3 and the control terminal n43 of the fourth transistor M4 can be electrically coupled to two voltage sources capable of providing the selection voltage VSL, or electrically coupled to the same voltage source, which is not limited by the present invention. The voltage source can be driven according to the user's selection, or the hybrid memory unit 1 can further include a microprocessor or a microcontroller to drive the voltage source to provide the selection voltage VSL according to a preset selection.

[0042] By virtue of the above coupling relationship, when the selection voltage VSL turns on the third and fourth transistors M3 and M4, the third and fourth transistors M3 and M4 can make the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 conductive, so that the storage circuit 11 is in a volatile storage mode; and when the selection voltage VSL turns off the third and fourth transistors M3 and M4, the third and fourth transistors M3 and M4 make the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 non-conductive, so that the storage circuit 11 is in a non-volatile storage mode. The voltage value of the selection voltage VSL that turns on or off the third and fourth transistors M3 and M4 can be designed by a person skilled in the art according to the types of the third and fourth transistors M3 and M4, and will not be described in detail herein.

[0043] Next, the relationship between the read / write element group 15 and other circuits is further described. As shown in the figure, the first end n51 of the fifth transistor M5 of the read / write element group 15 is electrically coupled to the first end n31 of the third transistor M3 of the selection circuit 13, that is, the first end n51 of the fifth transistor M5 is also electrically coupled to the first variable resistor R1 of the storage circuit 11. The second end n52 of the fifth transistor M5 is used to be electrically coupled to the first bit line BL1, and the control end n53 is used to be electrically coupled to the word line WL. Symmetrically, the first end n61 of the sixth transistor M6 of the read / write element group 15 is electrically coupled to the first end n41 of the fourth transistor M3 of the selection circuit 13, that is, the first end n61 of the sixth transistor M6 is also electrically coupled to the first variable resistor R1 of the storage circuit 11. The second end n62 of the sixth transistor M6 is used to be electrically coupled to the second bit line BL2, and the control end n63 is used to be electrically coupled to the word line WL. When the voltage provided by the word line WL turns on the fifth and sixth transistors M5 and M6, the fifth transistor M5 can transmit the data signal from the first bit line BL1, and the sixth transistor M6 can transmit the data signal from the second bit line BL2. The voltage value that turns on the fifth and sixth transistors M5 and M6 can be designed by technicians in the field of the present invention according to the types of the fifth and sixth transistors M5 and M6, and will not be elaborated here.

[0044] The objects to which the fifth and sixth transistors M5 and M6 transmit data signals are determined by the selection voltage VSL, and more specifically, by whether the third and fourth transistors M3 and M4 are turned on or off. Figure 1 , Figure 3 and Figure 4 ,in Figure 3 and Figure 4The equivalent circuit diagrams of the volatile storage mode and the non-volatile storage mode of the hybrid memory cell 1 are respectively shown according to an embodiment of the present invention. Figure 3 In the implementation scenario of the volatile storage mode shown, the third and fourth transistors M3 and M4 of the selection circuit 13 are turned on according to the selection voltage VSL, so the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 can be equivalent to being electrically coupled to each other by wires. Figure 3 The equivalent circuit shown is similar to the circuit of a volatile memory, namely, a static random access memory (SRAM). In this implementation scenario, the writing and reading operations of the hybrid memory cell 1 are the same as those of the SRAM, and thus will not be described in detail.

[0045] At Figure 4 In the implementation scenario of the non-volatile storage mode shown, the third and fourth transistors M4 and M5 of the selection circuit 13 are turned off according to the selection voltage VSL, so that the first and second transistors M1 and M2 are also turned off. In this implementation scenario, the hybrid storage unit can use the first and second variable resistors R1 and R2 to store one bit together, or the first and second variable resistors R1 and R2 can store two bits respectively. Further, in the example of storing one bit together, the first and second bit lines BL1 and BL2 can be used as complementary bit lines (BLB) and bit lines (BL), respectively, and the data signals transmitted are a set of complementary signals, including a reset signal Vreset and a set signal Vset. As mentioned above, the first and second variable resistors R1 and R2 include phase change materials, which can be crystalline or amorphous according to the voltage or current waveform carried, so as to have a relatively low resistance value or a relatively high resistance value. For example, the reset signal Vreset can be a voltage or current waveform with high amplitude and short duration. Such a voltage or current waveform can make the phase change material non-crystalline and the corresponding resistor have a relatively high resistance; while the set signal Vset can be a voltage or current waveform with lower amplitude and longer duration than the reset signal Vreset. Such a voltage or current waveform can make the phase change material crystalline and the corresponding resistor have a relatively low resistance.

[0046] In this example, it can be assumed that when the first variable resistor R1 has a relatively low resistance and the second variable resistor R2 has a relatively high resistance, it represents bit 0, and vice versa, it represents bit 1. Therefore, when writing bit 0, a setting signal Vset can be transmitted to the first variable resistor R1 through the first bit line BL1 and a reset signal Vreset can be transmitted to the second variable resistor R2 through the second bit line BL2; and when writing bit 1, a reset signal Vreset can be transmitted to the first variable resistor R1 through the first bit line BL1 and a setting signal Vset can be transmitted to the second variable resistor R2 through the second bit line BL2. In the reading stage, a predetermined voltage can be applied to the first and second bit lines BL1 and BL2 and the current values ​​of the two lines can be measured, and the resistance values ​​of the first and second variable resistors R1 and R2 can be determined based on the magnitude relationship of the current values ​​of the two lines to determine the stored bit. Alternatively, a predetermined current can be applied to the first and second bit lines BL1 and BL2 and the voltage values ​​of the two lines can be measured, and the resistance values ​​of the first and second variable resistors R1 and R2 can be determined based on the magnitude relationship of the voltage values ​​of the two lines to determine the stored bit.

[0047] In the example of storing two bits respectively, the first variable resistor R1 and the second variable resistor R2 are independent storage elements. In this example, it can be assumed that when the variable resistor has a relatively low resistance, it represents bit 0, and vice versa, it represents bit 1. Transmitting a set signal Vset to the first variable resistor R1 through the first bit line BL1 can make the first variable resistor R1 store bit 0, and transmitting a reset signal Vreset to the first variable resistor R1 through the first bit line BL1 can make the first variable resistor R1 store bit 1, and the writing operation of the second variable resistor R2 is similar. In the reading stage, a predetermined voltage can be applied to the first and second bit lines BL1 and BL2 respectively and the current value can be measured, and the first and second variable resistors R1 and R2 can be judged to store bit 0 or 1 respectively based on the magnitude relationship between the measured current value and a reference current. Alternatively, a predetermined current can be applied to the first and second bit lines BL1 and BL2 respectively and the voltage value can be measured, and the first and second variable resistors R1 and R2 can be judged to store bit 0 or 1 respectively based on the magnitude relationship between the measured voltage value and a reference voltage.

[0048] By programming the resistance values ​​of the first and second variable resistors R1 and R2 with voltage or current waveforms, even if the power supply is interrupted, the first and second variable resistors R1 and R2 can still maintain the state before the power failure, and thus can be used as non-volatile storage elements. In particular, the first and second bit lines BL1 and BL2 can be controlled by a read-write control circuit (not shown). The read-write control circuit can perform the above-mentioned operations of providing a write signal or providing a read signal, and can also perform the judgment of the stored bit.

[0049] The present invention also proposes a hybrid memory unit, which, in addition to the circuit structure described in the above embodiments, further includes a controller. Figure 1 and Figure 5 ,in Figure 5 FIG. 1 is a circuit diagram of a hybrid memory cell 1' according to another embodiment of the present invention. Figure 1 and Figure 5 As shown, the hybrid memory cell 1' has the same electronic components and electrical coupling relationship as the hybrid memory cell 1, so the circuits and functional operations composed of the various electronic components are not repeated here. In addition to the electronic components and electrical coupling relationship of the hybrid memory cell 1, the hybrid memory cell 1' also includes a controller 17. The controller 17 is electrically coupled to the storage circuit 11 and the selection circuit 13, and is used to detect the selection voltage VSL, and selectively adjust the voltage value of the control voltage VC according to the selection voltage VSL. Among them, the controller 17 can be a control circuit electrically coupled between the first and second variable resistors R1 and R2 of the storage circuit 11 and the voltage source providing the control voltage VC, or can be a device including a voltage source providing the control voltage VC, and the present invention is not limited thereto.

[0050] When the selection voltage VSL turns on the third and fourth transistors M3 and M4 of the selection circuit 13 and the storage circuit 11 presents a volatile storage mode, the controller 17 makes the control voltage VC have a first voltage value; and when the selection voltage VSL turns off the third and fourth transistors M3 and M4 of the selection circuit 13 and the storage circuit 11 presents a non-volatile storage mode, the controller 17 makes the control voltage VC have a second voltage value. The absolute value of the first voltage value is greater than the absolute value of the second voltage value. For example, when the storage circuit 11 presents a volatile storage mode, the controller 17 can make the control voltage VC the working voltage (VDD). When the storage circuit 11 presents a non-volatile storage mode, the controller 17 can make the control voltage VC zero, that is, make the first and second variable resistors R1 and R2 of the storage circuit 11 grounded; or when the storage circuit 11 presents a non-volatile storage mode, the controller 17 can make the control voltage VC the working voltage (VDD) or other voltage values. Compared to the embodiment in which the working voltage (VDD) is used as the control voltage VC in the non-volatile storage mode, in the embodiment in which the control voltage VC is set to zero in the non-volatile storage mode, the waveform design difficulty of the write signal (the aforementioned reset signal Vreset and setting signal Vset) is lower.

[0051] With the above structure, the hybrid memory unit disclosed in this case can be set to a volatile storage mode or a non-volatile storage mode as required, and has high adaptability. In addition, the memory composed of the hybrid memory units disclosed in this case can be matched with a variety of computing devices or other electronic devices with different requirements for storage modes by adjusting the setting of the selection voltage corresponding to each memory unit, without changing the circuit design of the memory, thereby reducing the development cost.

Claims

1. A hybrid memory cell, characterized in that: Include: A read / write element set is electrically coupled to a word line and two bit lines, and the two bit lines transmit two data signals respectively; a storage circuit electrically coupled to the read / write element set; and a selection circuit electrically coupled to the read / write element group and the storage circuit, the selection circuit being used to control the storage circuit to present a volatile storage mode or a non-volatile storage mode according to a selection voltage; The storage circuit includes a first variable resistor, a second variable resistor, a first transistor and a second transistor; when the read / write element group transmits the two data signals to the storage circuit and the storage circuit presents the non-volatile storage mode, the first variable resistor and the second variable resistor selectively change resistance values ​​according to the two data signals respectively; wherein the selection circuit is used to control an electrical coupling state among the first variable resistor, the second variable resistor, the first transistor, and the second transistor according to the selection voltage; when the selection circuit controls the electrical coupling state to be conductive according to the selection voltage, the storage circuit presents the volatile storage mode; and when the selection circuit controls the electrical coupling state to be non-conductive according to the selection voltage, the storage circuit presents the non-volatile storage mode; The selection circuit comprises: a third transistor, wherein a first terminal of the third transistor is electrically coupled to one terminal of the first variable resistor, the control terminal of the second transistor and the read / write element group, a second terminal of the third transistor is electrically coupled to the first terminal of the first transistor, and the control terminal of the third transistor is used to receive the selection voltage; and A fourth transistor, a first end of the fourth transistor is electrically coupled to one end of the second variable resistor, the control end of the first transistor and the read-write element group, a second end of the fourth transistor is electrically coupled to the first end of the second transistor, and the control end of the fourth transistor is used to receive the selection voltage. 2 . The hybrid memory cell as claimed in claim 1 , wherein the variable resistors comprise phase change elements or resistance change elements.

3. The hybrid memory cell of claim 1 , wherein the read / write element set comprises: a fifth transistor, wherein a first terminal of the fifth transistor is electrically coupled to the first terminal of the third transistor, a second terminal of the fifth transistor is electrically coupled to one of the two bit lines, and a control terminal of the fifth transistor is electrically coupled to the word line; A sixth transistor, a first terminal of the sixth transistor is electrically coupled to the first terminal of the fourth transistor, a second terminal of the sixth transistor is electrically coupled to the other of the two bit lines, and a control terminal of the sixth transistor is electrically coupled to the word line. 4 . The hybrid memory cell as claimed in claim 1 , wherein one end of the two variable resistors is electrically coupled to the read / write element group, and the other end of the two variable resistors is used to receive a control voltage. 5 . The hybrid memory cell as claimed in claim 4 , further comprising a controller, the controller being electrically coupled to the storage circuit and the selection circuit and configured to detect the selection voltage and control the control voltage according to the selection voltage.

6. The hybrid memory cell as claimed in claim 5, wherein the controller controls the control voltage according to the selection voltage comprises: When the selection voltage causes the storage circuit to present the volatile storage mode, controlling the control voltage to have a first voltage value; and When the selection voltage causes the storage circuit to present the non-volatile storage mode, controlling the control voltage to have a second voltage value; The absolute value of the first voltage value is greater than the absolute value of the second voltage value.

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