Chip-on-film packaging structure

Abstract

The present invention provides a chip-on-film packaging structure, comprising a flexible circuit carrier and a chip. The flexible circuit carrier comprises a flexible substrate and a circuit structure. The circuit structure is arranged on the flexible substrate and comprises a plurality of first pins, a plurality of second pins and at least one dummy pin. The first pin is arranged on the first surface of the flexible substrate and comprises a plurality of inner pin portions located in a chip bonding area. The second pin and the dummy pin are arranged on the second surface of the flexible substrate. The dummy pin extends into the chip bonding area. The chip comprises a plurality of bumps respectively connected to the inner pin portions and at least one dummy bump. The dummy pin extends along a first direction and divides the width of the orthographic projection of the dummy bump on the flexible substrate in a second direction perpendicular to the first direction within an allowable tolerance. The chip-on-film packaging structure of the present invention can provide confirmation of alignment during pin bonding and pin offset after bonding, so as to improve the reliability of the packaging structure.

Description

Technical Field

[0001] The invention relates to a packaging structure, in particular to a chip-on-film packaging structure. Background Art

[0002] The chip on film (COF) packaging structure is a common packaging type for driver chips of liquid crystal displays. With the increase in the number of bumps on the chip, the increase in the number of pins and the miniaturization of the pin spacing, the layout of the bumps and pins is increasingly limited. Therefore, in order to increase the pin layout space, double-sided copper foil substrates have begun to be favored. Since the front and back of the double-sided copper foil substrate are covered with circuits, if there is no obvious alignment mark, it is easy to cause the problem of pin offset when the pin and the bump are joined. Furthermore, if the alignment pin is set on the front of the double-sided copper foil substrate and eutectic bonded with the alignment bump, the gold-tin eutectic alloy layer is easy to affect the image interpretation, and the alignment and offset confirmation cannot be effectively performed. Summary of the invention

[0003] The present invention is directed to a film flip chip packaging structure, which can provide confirmation of alignment during pin bonding and pin offset after bonding, so as to improve the reliability of the packaging structure.

[0004] According to an embodiment of the present invention, a thin film chip package structure includes a flexible circuit carrier and a chip. The flexible circuit carrier includes a flexible substrate and a circuit structure. The flexible substrate has a first surface and a second surface opposite to each other and a chip bonding area. The circuit structure is configured on the flexible substrate and includes a plurality of first pins, a plurality of second pins and at least one dummy pin. The first pin is configured on the first surface and includes a plurality of inner pin portions located in the chip bonding area. The second pin and at least one dummy pin are configured on the second surface. At least one dummy pin extends into the chip bonding area. The chip is configured on the first surface and is located in the chip bonding area. The chip includes a plurality of bumps and at least one dummy bump, and the bumps are respectively connected to the inner pin portions. The at least one dummy pin extends along a first direction and divides the width of the orthographic projection of the at least one dummy bump on the flexible substrate in a second direction perpendicular to the first direction within an allowable tolerance.

[0005] In the thin film chip package structure according to an embodiment of the present invention, the chip has two opposite long sides and two opposite short sides. The chip bonding area has two first sides corresponding to the two long sides and two second sides corresponding to the two short sides. The two long sides and the two short sides constitute a plurality of chip corners. The two first sides and the two second sides constitute a plurality of bonding area corners.

[0006] In the chip-on-film package structure according to an embodiment of the present invention, the at least one dummy bump is located at at least one of the corners of the chip, and the at least one dummy lead extends into at least one of the corners of the bonding area.

[0007] In the chip-on-film package structure according to an embodiment of the present invention, the at least one dummy bump includes a first dummy bump and a second dummy bump. The first dummy bump and the second dummy bump are respectively located at two of the corners of the chip.

[0008] In the thin film chip package structure according to an embodiment of the present invention, the at least one dummy pin includes a first dummy pin and a second dummy pin. The first dummy pin extends through one of the two first sides of the chip bonding area. The first dummy pin divides the width of the orthogonal projection of the first dummy bump on the flexible substrate on one of the two parallel first sides within an allowable tolerance. The second dummy pin extends through one of the two second sides of the chip bonding area. The second dummy pin divides the width of the orthogonal projection of the second dummy bump on the flexible substrate on one of the two parallel second sides within an allowable tolerance.

[0009] In the thin film chip package structure according to an embodiment of the present invention, the above-mentioned flexible circuit carrier also includes a first solder mask and a second solder mask. The first solder mask is arranged on the first surface of the flexible substrate and is located outside the chip bonding area. The first solder mask partially covers the first pin. The second solder mask is arranged on the second surface of the flexible substrate and at least partially covers the second pin and exposes at least one of the chip corners where at least one virtual bump is located at the orthographic projection on the flexible substrate.

[0010] In the chip-on-film packaging structure according to the embodiment of the present invention, the area of ​​the at least one dummy bump is larger than the area of ​​each of the bumps.

[0011] In the chip-on-film package structure according to an embodiment of the present invention, the at least one dummy pin divides the width of the orthographic projection of the at least one dummy bump on the flexible substrate in the second direction into a first distance and a second distance. The first pins arranged along the second direction have an offset tolerance, and the absolute value of the difference between the first distance and the second distance is less than or equal to the offset tolerance.

[0012] In the chip-on-film package structure according to the embodiment of the present invention, the first pin and the second pin do not overlap the orthographic projection of at least one virtual bump on the flexible substrate.

[0013] In the Chip-on-Through Package structure according to an embodiment of the present invention, the Chip-on-Through Package structure further includes a packaging colloid disposed between the flexible circuit carrier and the chip, wherein the packaging colloid covers the bump, at least one dummy bump and the inner lead portion.

[0014] Based on the above, in the film flip chip packaging structure of the present invention, the virtual pin located on the second surface of the flexible substrate can extend along the first direction, and the width of the orthographic projection of the virtual bump of the chip located on the first surface of the flexible substrate on the flexible substrate in the second direction perpendicular to the first direction can be evenly divided within the allowable tolerance. In this way, it can be used as a judgment of whether the pin and the bump are aligned during the pin bonding operation, and it can also provide a machine or personnel to directly confirm whether the pin and the bump are offset after the bonding operation, so as to improve the bonding yield of the pin and the bump, and the film flip chip packaging structure of the present invention can have better structural reliability. In addition, since the virtual pin located on the second surface of the flexible substrate does not contact the virtual bump of the chip located on the first surface of the flexible substrate, the problem of difficult image interpretation caused by eutectic bonding of the virtual pin and the virtual bump can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention;

[0016] Figure 2A is along Figure 1 A schematic cross-sectional view of line AA;

[0017] Figure 2B is along Figure 1 A schematic cross-sectional view of line BB;

[0018] Figure 3 and Figure 4 They are Figure 1 An enlarged schematic diagram of area A and area B in FIG.

[0019] Description of Reference Numerals

[0020] 10: Chip-on-film packaging structure

[0021] 100: Flexible circuit board

[0022] 110: Flexible substrate

[0023] 112: First surface

[0024] 114: Second surface

[0025] 116: Chip bonding area

[0026] 120: Line structure

[0027] 122: First pin

[0028] 123, 123': Inner pin part

[0029] 123a: pad

[0030] 124: Second pin

[0031] 125: Conductive via

[0032] 126: First virtual pin

[0033] 128: Second virtual pin

[0034] 130: First solder mask

[0035] 140: Second solder mask

[0036] 200: Chip

[0037] 201, 203: long side

[0038] 205, 207: Short side

[0039] 210, 240: Bump

[0040] 220: first virtual bump

[0041] 230: Second virtual bump

[0042] 300: Encapsulation colloid

[0043] CC: Chip Corner

[0044] BC: Corner of the junction area

[0045] D1: First direction

[0046] D2: Second direction

[0047] L1: First distance

[0048] L2: Second distance

[0049] L3: The third distance

[0050] L4: The fourth distance

[0051] S1, S2: First side

[0052] S3, S4: Second side

[0053] P1, P2: total spacing

[0054] W1, W2: Width DETAILED DESCRIPTION

[0055] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Figure 1FIG. 4 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. Figure 2A is along Figure 1 Schematic cross-sectional view of line AA. Figure 2B is along Figure 1 A schematic cross-sectional view of line BB. Figure 3 and Figure 4 They are Figure 1 For the convenience of explanation, Figure 1 Some components, such as solder mask and packaging colloid, are omitted, and the chip and bumps are presented in a perspective manner.

[0057] Please refer to Figure 1 and Figure 2A In this embodiment, the chip-on-film package structure 10 includes a flexible circuit carrier 100 and a chip 200. The flexible circuit carrier 100 includes a flexible substrate 110 and a circuit structure 120. The flexible substrate 110 has a first surface 112 and a second surface 114 opposite to each other and a chip bonding area 116. The circuit structure 120 is configured on the flexible substrate 110 and includes a plurality of first pins 122, a plurality of second pins 124, and at least one dummy pin (schematically showing a first dummy pin 126 and a second dummy pin 128). The first pin 122 is configured on the first surface 112 and includes a plurality of inner pin portions 123 located in the chip bonding area 116. The second pin 124, the first dummy pin 126, and the second dummy pin 128 are configured on the second surface 114, and the first dummy pin 126 and the second dummy pin 128 extend into the chip bonding area 116. Here, the flexible circuit carrier 100 is embodied as a double-sided circuit substrate. In this embodiment, only a few second pins 124 are schematically shown to indicate that the flexible circuit carrier 100 is a double-sided circuit substrate.

[0058] The chip 200 is disposed on the first surface 112 and is located in the chip bonding area 116. The chip 200 includes a plurality of bumps 210, 240 and at least one dummy bump (schematically showing a first dummy bump 220 and a second dummy bump 230), and the bumps 210 are respectively connected to the inner pin portions 123. The bumps 240 are electrically connected to the second pins 124 through the conductive vias 125. In detail, some of the first pins 122 have inner pin portions 123 and extension portions and outer pin portions extending outward from the chip bonding area 116, and another portion of the first pins 122 only have inner pin portions 123' located in the chip bonding area 116, and the inner pin portions 123' extend toward the center of the chip bonding area 116 and form a pad 123a of a larger size. The conductive vias 125 are located within the pad 123a and electrically connect the pad 123a and the second pin 124. In other words, the bump 240 is electrically connected to the second pin 124 by connecting the inner pin portion 123' and the pad 123a and the conductive through hole 125. In this embodiment, only a few of the bumps 240, the inner pin portion 123' and the pad 123a are schematically shown. In addition, the first dummy pin 126 extends along the first direction D1 and the width W1 (indicated by Figure 3 Similarly, the second dummy pin 128 extends along the second direction D2 and the width W2 (indicated by Figure 4 Here, the first direction D1 is parallel to the Y direction, and the second direction D2 is parallel to the X direction.

[0059] More specifically, the chip 200 of the present embodiment has two opposite long sides 201, 203 and two opposite short sides 205, 207. The chip bonding area 116 has two first sides S1, S2 corresponding to the two long sides 201, 203 and two second sides S3, S4 corresponding to the two short sides 205, 207. The two long sides 201, 203 and the two short sides 205, 207 constitute a plurality of chip corners CC. The two first sides S1, S2 and the two second sides S3, S4 constitute a plurality of bonding area corners BC. The first dummy bump 220 and the second dummy bump 230 are respectively located at the two chip corners CC. The first dummy pin 126 and the second dummy pin 128 extend into the two bonding area corners BC corresponding to the two chip corners CC where the first dummy bump 220 and the second dummy bump 230 are located. Here, the first side S1 is an output end, and the first side S2 is an input end, and the spacing between the first pins 122 on the first side S1 is smaller than the spacing between the first pins 122 on the second side S2. In other embodiments, the width of the first pins 122 on the first side S1 may be smaller than the width of the first pins 122 on the second side S2.

[0060] It should be noted that if Figure 1 As shown, for the sake of clarity, the orthographic projection of the first pin 122 on the flexible substrate 110 of this embodiment does not overlap the orthographic projection of the second pin 124 on the flexible substrate 110, but the present invention is not limited thereto. In other embodiments, the orthographic projection of the first pin 122 on the flexible substrate 110 may also overlap the orthographic projection of the second pin 124 on the flexible substrate 110 as much as possible, thereby making the stress of the first surface 112 and the second surface 114 of the flexible substrate 110 more even, which still falls within the scope of the invention.

[0061] Please also refer to Figure 1 and Figure 3 In the present embodiment, the first dummy lead 126 extends through the first side S1 of the chip bonding area 116. The first dummy lead 126 divides the width W1 of the orthographic projection of the first dummy bump 220 on the flexible substrate 110 parallel to the first side S1 within the allowable tolerance. More specifically, the first dummy lead 126 divides the width W1 of the orthographic projection of the first dummy bump 220 on the flexible substrate 110 in the second direction D2 (i.e., the direction parallel to the first side S1) into a first distance L1 and a second distance L2. The plurality of first leads 122 arranged along the second direction D2 have an offset allowable tolerance. For example, in the present embodiment, the offset allowable tolerance is 0.02% multiplied by the total pitch P1, and the absolute value of the difference between the first distance L1 and the second distance L2 is less than or equal to (i.e., not greater than) the offset allowable tolerance. That is, |L1-L2|≦0.02%*P1. Specifically, the total pitch P1 is the distance (center to center) between two first leads 122 located at two opposite outermost sides of the plurality of first leads 122 arranged along the second direction D2 .

[0062] Also, please refer to Figure 1 and Figure 4In the present embodiment, the second dummy pin 128 extends through the second side S4 of the chip bonding area 116. The second dummy pin 128 divides the width W2 of the orthographic projection of the second dummy bump 230 on the flexible substrate 110 on the second side S4 evenly within the allowable tolerance. More specifically, the second dummy pin 128 divides the width W2 of the orthographic projection of the second dummy bump 230 on the flexible substrate 110 in the first direction D1 (i.e., the direction parallel to the second side S4) into a third distance L3 and a fourth distance L4. The plurality of first pins 122 arranged along the first direction D1 have an offset tolerance. For example, in the present embodiment, the offset tolerance is 0.02% multiplied by the total pitch P2, and the absolute value of the difference between the third distance L3 and the fourth distance L4 is less than or equal to (i.e., not greater than) the offset tolerance. That is, |L3-L4|≦0.02%*P2. Specifically, the total pitch P2 is the distance (center to center) between two first leads 122 located at two opposite outermost sides of the plurality of first leads 122 arranged along the first direction D1 .

[0063] Furthermore, please refer to Figure 1 , Figure 2A and Figure 2B The flexible circuit carrier 100 of the present embodiment further includes a first solder mask 130 and a second solder mask 140. The first solder mask 130 is disposed on the first surface 112 of the flexible substrate 110 and is located outside the chip bonding area 116. The first solder mask 130 partially covers the first lead 122. The second solder mask 140 is disposed on the second surface 114 of the flexible substrate 110 and at least partially covers the second lead 124 and exposes the orthographic projection of the chip corner CC where the first dummy bump 220 and the second dummy bump 230 are located on the flexible substrate 110. In other words, the chip corner CC where the first dummy bump 220 and the second dummy bump 230 are located will not be covered by the second solder mask 140, so the machine or personnel can observe the alignment of the first dummy lead 126 and the first dummy bump 220 and the second dummy lead 128 and the second dummy bump 230 from the second surface 114 of the flexible substrate 110. Here, the area of ​​the first dummy bump 220 and the second dummy bump 230 is larger than the area of ​​each bump 210 , 240 . The first lead 122 and the second lead 124 do not overlap the orthographic projections of the first dummy bump 220 and the second dummy bump 230 on the flexible substrate 110 .

[0064] In addition, please also refer to Figure 1 , Figure 2A and Figure 2B The chip-on-film packaging structure 10 of the present embodiment further includes a packaging colloid 300 disposed between the flexible circuit substrate 100 and the chip 200 , wherein the packaging colloid 300 covers the bumps 210 , 240 , the first dummy bump 220 , the second dummy bump 230 and the inner pins 123 , 123 ′.

[0065] In short, when the first surface 112 and the second surface 114 of the flexible substrate 110 are both provided with circuits (i.e., the first pin 122 and the second pin 124), in this embodiment, the first dummy pin 126 provided on the second surface 114 extends along the first direction D1 and the width W1 of the orthogonal projection of the first dummy bump 220 on the flexible substrate 110 in the second direction D2 is evenly divided within the allowable tolerance to determine whether the bonding between the first pin 122 and the bumps 210 and 240 is offset in the X direction. Similarly, the second dummy pin 128 extends along the second direction D2 and the width W2 of the orthogonal projection of the second dummy bump 230 on the flexible substrate 110 in the first direction D1 is evenly divided within the allowable tolerance to determine whether the bonding between the first pin 122 and the bumps 210 and 240 is offset in the Y direction. Thus, it can be confirmed whether there is an offset problem between the inner pins 123, 123' and the bumps 210, 240 after bonding, so as to improve the bonding yield of the inner pins 123, 123' and the bumps 210, 240, so that the TFCP structure 10 of this embodiment can have better structural and electrical reliability.

[0066] In summary, in the film flip chip packaging structure of the present invention, the virtual pins located on the second surface of the flexible substrate can extend along the first direction, and the width of the orthographic projection of the virtual bumps of the chip located on the first surface of the flexible substrate on the flexible substrate in the second direction perpendicular to the first direction can be evenly divided within the allowable tolerance. In this way, it can be used as a judgment of whether the pins and the bumps are aligned during the pin bonding operation, and it can also be provided to the machine or personnel to directly confirm whether the pins and the bumps are offset after the bonding operation, so as to improve the bonding yield of the pins and the bumps, and the film flip chip packaging structure of the present invention can have better structural reliability. In addition, since the virtual pins located on the second surface of the flexible substrate do not contact the virtual bumps of the chip located on the first surface of the flexible substrate, the problem of difficult image interpretation caused by eutectic bonding of the virtual pins and the virtual bumps can be avoided.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip-on-film packaging structure, characterized in that: include: Flexible circuit board, including: A flexible substrate having a first surface and a second surface opposite to each other and a chip bonding area; and a circuit structure, disposed on the flexible substrate, and comprising a plurality of first pins, a plurality of second pins, and at least one dummy pin, wherein the plurality of first pins are disposed on the first surface and include a plurality of inner pin portions located in the chip bonding area, the plurality of second pins and the at least one dummy pin are disposed on the second surface, and the at least one dummy pin extends into the chip bonding area; and A chip is configured on the first surface and located in the chip bonding area, and includes a plurality of bumps and at least one virtual bump, wherein the plurality of bumps are respectively connected to the plurality of inner pin portions, and the at least one virtual pin extends along a first direction and divides the width of the orthographic projection of the at least one virtual bump on the flexible substrate in a second direction perpendicular to the first direction within an allowable tolerance.

2. The chip-on-film packaging structure according to claim 1, characterized in that: The chip has two opposite long sides and two opposite short sides, the chip bonding area has two first sides corresponding to the two long sides and two second sides corresponding to the two short sides, the two long sides and the two short sides constitute multiple chip corners, and the two first sides and the two second sides constitute multiple bonding area corners.

3. The chip-on-film packaging structure according to claim 2, characterized in that: The at least one dummy bump is located at at least one of the plurality of chip corners, and the at least one dummy lead extends into at least one of the plurality of bonding area corners.

4. The chip-on-film packaging structure according to claim 3, characterized in that: The at least one dummy bump includes a first dummy bump and a second dummy bump, and the first dummy bump and the second dummy bump are respectively located at two of the corners of the plurality of chips.

5. The chip-on-film packaging structure according to claim 4, characterized in that: The at least one dummy pin includes a first dummy pin and a second dummy pin, the first dummy pin extends through one of the two first sides of the chip bonding area, and the first dummy pin divides the width of the orthographic projection of the first dummy bump on the flexible substrate on one of the two first sides within an allowable tolerance, and the second dummy pin extends through one of the two second sides of the chip bonding area, and the second dummy pin divides the width of the orthographic projection of the second dummy bump on the flexible substrate on one of the two second sides within an allowable tolerance.

6. The chip-on-film packaging structure according to claim 3, characterized in that: The flexible circuit carrier further comprises: A first solder resist layer is disposed on the first surface of the flexible substrate and is located outside the chip bonding area, wherein the first solder resist layer partially covers the plurality of first pins; and The second solder mask is disposed on the second surface of the flexible substrate and at least partially covers the plurality of second pins and exposes the orthographic projection of at least one of the plurality of chip corners where the at least one virtual bump is located on the flexible substrate.

7. The chip-on-film packaging structure according to claim 1, characterized in that: The area of ​​the at least one virtual bump is greater than the area of ​​each of the plurality of bumps.

8. The chip-on-film packaging structure according to claim 1, characterized in that: The at least one virtual pin divides the width of the orthographic projection of the at least one virtual bump on the flexible substrate in the second direction into a first distance and a second distance. The multiple first pins arranged along the second direction have an offset tolerance, and the absolute value of the difference between the first distance and the second distance is less than or equal to the offset tolerance.

9. The chip-on-film packaging structure according to claim 1, wherein: The plurality of first pins and the plurality of second pins do not overlap the orthographic projection of the at least one virtual bump on the flexible substrate.

10. The chip-on-film packaging structure according to claim 1, wherein: Also includes: The packaging colloid is disposed between the flexible circuit carrier and the chip, wherein the packaging colloid covers the plurality of bumps, the at least one dummy bump and the plurality of inner pins.

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