Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same, wherein the semiconductor device comprises: a substrate; fins, which are located on the substrate separately; a gate structure, which spans the fins, wherein the gate structure comprises a first region and a second region, wherein the first region covers the sidewalls of the fins and is located at the junction of the gate structure and the fins, and the second region is located on the substrate and the distance from the second region to the fins is greater than the distance from the first region to the fins, and along the extension direction of the fins, the size of the first region is smaller than the size of the second region. The semiconductor device of this structure, on the one hand, allows the gate structure located on the second region on the substrate to maintain its original characteristics, and on the other hand, the size of the first region of the gate structure is small, so that the gate residue is reduced, and the distance between the gate structure and the source and drain doping region is increased, so that the first region of the gate structure is not easily connected to the source and drain doping region, thereby avoiding the generation of leakage current.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current has weakened, resulting in serious leakage current. Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the fin, and source and drain doped regions in the fin on both sides of the gate structure.

[0003] The gate structure is formed by performing a multi-step etching process on the gate dielectric material layer and the gate electrode material layer located on the surface of the gate dielectric material. However, due to the relatively small space at the junction of the gate structure and the fin, the etching process cannot completely remove the gate structure at the junction due to space limitations, resulting in the remnants of the gate structure material, and the performance of the semiconductor device needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

[0005] In order to solve the above technical problems, the present invention provides a semiconductor device, comprising: a substrate; fins, which are separately located on the substrate; a gate structure, which spans the fins, and the gate structure comprises a first region and a second region, the first region covers the side walls of the fins and is located at the junction of the gate structure and the fins, the second region is located on the substrate and the distance from the second region to the fins is greater than the distance from the first region to the fins, and along the extension direction of the fins, the size of the first region is smaller than the size of the second region.

[0006] Optionally, a cross-sectional shape of the first region of the gate structure along a direction parallel to an extension direction of the fin and perpendicular to a surface of the substrate is an inverted trapezoid.

[0007] Optionally, a cross-sectional shape of the second region of the gate structure along a direction parallel to an extension direction of the fin and perpendicular to a surface of the substrate is a rectangle.

[0008] Optionally, the method further includes: a protective layer on the surface of the gate structure and the surface of the fin located outside the first region.

[0009] Optionally, the protective layer is a nitrogen-containing polymer, a carbon-containing polymer, or a sulfur-containing polymer.

[0010] Optionally, the gate structure includes: a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer; the material of the gate electrode layer includes: polysilicon or polycrystalline germanium, and the gate dielectric layer covers part of the top surface and part of the side wall surface of the fin.

[0011] Optionally, the gate structure further includes: a third region, the third region is located on the top surface of the fin, and a size of the first region is smaller than a size of the third region along an extension direction of the fin.

[0012] Optionally, it also includes: an isolation structure located on the surface of the substrate, the isolation structure covers a portion of the side wall of the fin, and the top surface of the isolation structure is lower than the top surface of the fin; the first region and the second region of the gate structure are located on a portion of the surface of the isolation structure.

[0013] Optionally, it also includes: source and drain doping regions within the fins located on both sides of the gate structure.

[0014] Correspondingly, the present invention also provides a method for forming a semiconductor device, comprising: providing a substrate, wherein the surface of the substrate has a fin; forming an initial gate structure spanning the fin, wherein the initial gate structure comprises an initial first region and an initial second region, wherein the initial first region covers the side wall of the fin and is located at the junction of the initial gate structure and the fin, wherein the initial second region is located on the substrate and the distance from the initial first region to the fin is smaller than the distance from the initial second region to the fin, and along the extension direction of the fin, the size of the initial first region is larger than the size of the initial second region; forming a protective layer on the surface of the initial gate structure outside the initial first region and on the surfaces of the fin on both sides of the initial gate structure; using the protective layer as a mask, performing an etching process on the side wall of the initial first region to form a gate structure, wherein the gate structure comprises a first region formed by etching the initial first region, and a second region formed by etching the initial second region, and along the extension direction of the fin, the size of the first region is smaller than the size of the second region.

[0015] Optionally, a cross-sectional shape of the first region of the gate structure along a direction parallel to an extension direction of the fin and perpendicular to a surface of the substrate is an inverted trapezoid.

[0016] Optionally, a cross-sectional shape of the second region of the gate structure along a direction parallel to an extension direction of the fin and perpendicular to a surface of the substrate is a rectangle.

[0017] Optionally, the etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power, and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power, and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off, and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source is turned off, and the bias power source is turned off; the first source power is equal to the second source power, the first bias power is greater than the second bias power, and the third bias power is greater than the first bias power.

[0018] Optionally, the etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned off and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source is turned off; performing a third stage etching, in which the plasma source provides a third source power and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source provides a fourth source power and the bias power source provides a fourth bias power; the third source power is equal to the fourth source power, the first bias power is greater than the third bias power, and the third bias power is greater than the fourth bias power.

[0019] Optionally, the etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned on and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off and the bias power source is turned off, and the first bias power is less than the second bias power.

[0020] Optionally, the etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power, and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power, and the bias power source provides a second bias power, the first source power is equal to the second source power, and the first bias power is greater than the second bias power.

[0021] Optionally, the pulse duty cycle of the asynchronous pulse etching process is 1% to 80%.

[0022] Optionally, the reaction gas used includes a mixed gas of O2, CF4, CH4, Cl2 and He, wherein the flow rate of O2 is 5sccm~500sccm, the flow rate of CF4 is 10sccm~550sccm, the flow rate of CH4 is 5sccm~500sccm, the flow rate of Cl2 is 1sccm~500sccm, and the flow rate of He is 5sccm~450sccm; the pressure is 5 mTorr~100 mTorr, the source RF power is 100 W~1000 W, and the bias RF power is 200 W~2000 W.

[0023] Optionally, the method for forming the initial gate structure includes: forming a gate dielectric material layer and a gate electrode material layer located on the surface of the gate dielectric material layer on the substrate and the fin; patterning the gate dielectric material layer and the gate electrode material layer to form an initial gate dielectric layer and an initial gate electrode layer, the initial gate structure includes an initial gate dielectric layer and an initial gate electrode layer located on the surface of the initial gate dielectric layer, and the initial gate structure covers a portion of the top surface and a portion of the side wall surface of the fin.

[0024] Optionally, the material of the initial gate electrode layer includes: polycrystalline silicon or polycrystalline germanium.

[0025] Optionally, the protective layer is a nitrogen-containing polymer, a carbon-containing polymer, or a sulfur-containing polymer.

[0026] Optionally, before forming the initial gate structure, it also includes: forming an isolation structure on the surface of the substrate, the isolation structure covering a portion of the side wall of the fin, and the top surface of the isolation structure is lower than the top surface of the fin; the initial gate structure is located on the surface of a portion of the isolation structure.

[0027] Optionally, after forming the gate structure, it also includes: forming source-drain doped regions in the fins on both sides of the gate structure; the method for forming the source-drain doped regions includes: forming source-drain openings in the fins on both sides of the gate structure; forming an epitaxial layer in the source-drain openings; and doping source-drain ions into the epitaxial layer to form the source-drain doped regions.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] The size of the gate structure in the first region is smaller than that in the second region, and the first region covers the sidewall of the fin. Since the size of the gate structure on the sidewall of the fin is small, the gate structure can form less gate residue at the junction with the fin, thereby reducing the risk of electrical connection between the subsequent gate structure and the source and drain doping regions, thereby reducing the leakage phenomenon of the semiconductor device and enhancing the performance of the formed semiconductor device.

[0030] After an initial gate structure is formed on the substrate across the fin, an initial first region of the initial gate structure covers the sidewall of the fin and is located at the junction of the initial gate structure and the fin, and a protective layer is formed on the surface of the initial gate structure except for the initial first region and on the fins on both sides of the initial gate structure. The sidewalls of the initial first region are etched using the protective layer as a mask to form the first region of the gate structure. The first region of the gate structure is reduced in size in the direction extending along the fin, so that gate residues that can be formed at the junction with the fin are reduced, thereby reducing the probability of electrical connection between the first region of the gate structure and the source and drain doping regions in subsequent processes, thereby reducing leakage and improving the performance of the formed semiconductor device; at the same time, a protective layer is formed on the surface of the initial gate structure except for the initial first region and on the fins on both sides of the initial gate structure, and the protective layer is used to protect the formed fins and the performance of the initial gate structure except for the initial first gate, so that its performance is not affected, which is beneficial to improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 4 It is a structural schematic diagram of each step of a method for forming a semiconductor device;

[0032] Figures 5 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of semiconductor devices is poor.

[0034] Now, combined with a method for forming a semiconductor device, the reasons why the performance of the semiconductor device is poor are analyzed:

[0035] Figures 1 to 4 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor device.

[0036] Please refer to Figure 1 , a substrate 100 is provided, and a surface of the substrate 100 has a plurality of mutually discrete fins 110 .

[0037] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 Top view along the Z direction, Figure 3 yes Figure 2 In the cross-sectional view along the A-A1 direction, a gate structure 120 is formed across the plurality of mutually separated fins 110 , and the gate structure 120 covers a portion of the top surface and the sidewall surface of the fin 110 .

[0038] Please refer to Figure 4 , Figure 4 and Figure 3 The viewing direction is the same, and source-drain doped regions 130 are formed in the fins 110 on both sides of the gate structure 120 .

[0039] In the above-mentioned method for forming a semiconductor device, the method for forming the gate structure 120 includes: forming a gate dielectric material layer and a gate electrode material layer located on the surface of the gate dielectric material layer on the substrate 100, wherein the gate dielectric layer covers the top surface and the side wall surface of the fin; through a multi-step etching process, patterning the gate dielectric material layer and the gate electrode material layer to form a gate dielectric layer and a gate electrode layer, wherein the gate structure 120 includes a gate dielectric layer and a gate electrode layer.

[0040] refer to Figure 2 The gate structure 120 has more gate residues at a, so that the gate structure 120 is easily connected to the subsequently formed source-drain doped region 130, thereby generating leakage current, thereby affecting the performance of the formed semiconductor device.

[0041] In order to solve the technical problem, the present invention provides a method for forming a semiconductor device, comprising: forming an initial gate structure across the fin, the initial gate structure comprising an initial first region and an initial second region, the initial first region covering the sidewall of the fin and being located at the junction of the initial gate structure and the fin, the initial second region being located on the substrate and the distance from the initial first region to the fin being greater than the distance from the initial second region to the fin, and the size of the initial first region being greater than the size of the initial second region along the extension direction of the fin; forming a protective layer on the surface of the initial gate structure outside the initial first region and on the surface of the fin on both sides of the initial gate structure; using the protective layer as a mask, performing an etching process on the sidewall of the initial first region to form a gate structure, the gate structure comprising a first region formed by etching the initial first region and a second region formed by the initial second region, and the size of the first region being smaller than the size of the second region along the extension direction of the fin. The semiconductor device formed by the method has good performance.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Please refer to Figure 5 , providing a substrate 200, wherein the surface of the substrate 200 has a fin 210.

[0044] For the convenience of expression, Figure 5 Only one fin is shown.

[0045] In this embodiment, the material of the substrate 200 is single crystal silicon. The substrate may also be polycrystalline silicon or amorphous silicon. The substrate material may also be a semiconductor material such as germanium, silicon germanium, gallium arsenide, etc. The substrate may also be a semiconductor-on-insulator structure, wherein the semiconductor-on-insulator structure includes an insulator and a semiconductor material layer located on the insulator, wherein the material of the semiconductor material layer includes a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or indium gallium arsenide.

[0046] In this embodiment, the substrate 200 and the fin 210 located on the surface of the substrate 200 are formed by etching an initial substrate. In other embodiments, a fin material layer is formed on a substrate, and then the fin material layer is patterned to form the fin 210.

[0047] In this embodiment, a mask protection layer (not shown) is formed on the top surface of the fin 210 .

[0048] The material of the mask protection layer includes: silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the mask protection layer is silicon oxide.

[0049] The mask protection layer is used to prevent the fin 210 from being damaged in a subsequent etching process.

[0050] Please refer to Figure 6 An isolation structure 220 is formed on the surface of the substrate 200 , wherein the isolation structure 220 covers a portion of the sidewall of the fin 210 , and a top surface of the isolation structure 220 is lower than a top surface of the fin 210 .

[0051] In this embodiment, the isolation structure 220 is a shallow trench isolation structure.

[0052] The material of the isolation structure 220 includes silicon oxide, oxynitride or silicon nitride. In this embodiment, the material of the isolation structure 220 is silicon oxide, which can adhere well to the silicon substrate.

[0053] The isolation structure 220 is used to achieve electrical isolation between different semiconductor devices.

[0054] refer to Figure 7 , Figure 8 and Fig. 9 , forming an initial gate structure 230 across the fin 210. Figure 8 yes Figure 7 A top view of Fig. 9 yes Figure 8 In the section view along section line AA, Fig.10 yes Figure 8 Section view along section line BB.

[0055] After forming the isolation structure 220, an initial gate structure 230 is formed across the fin 210. The initial gate structure 230 includes an initial first region 231 and an initial second region 232. The initial first region 231 is located along the AA section line, and the initial second region 232 is located along the BB section line. The initial first region 231 covers the side wall of the fin 210 and is located at the junction of the initial gate structure 230 and the fin 210. The initial second region 232 is located on the substrate 200 and the distance from the initial first region 231 to the fin 210 is smaller than the distance from the initial second region 232 to the fin 210. In the extension direction along the fin 210, the size of the initial first region 231 is larger than the size of the initial second region 232.

[0056] Please refer to Figure 8 , the initial gate structure 230 forms a gate residue at a.

[0057] In this embodiment, the initial gate structure 230 includes an initial gate dielectric layer 234 and an initial gate electrode layer 235 . The initial gate electrode layer 235 is located on the surface of the initial gate dielectric layer 234 . The initial gate dielectric layer 234 is located on a portion of the top surface of the fin 210 .

[0058] In this embodiment, the method for forming the initial gate structure 230 includes: forming a gate dielectric material layer on the substrate 200 and the fin 210, and a gate electrode material layer located on the surface of the gate dielectric material layer; patterning the gate dielectric material layer and the gate electrode material layer to form the initial gate dielectric layer 234 and the initial gate electrode layer 235, and the initial gate structure 2430 spans the fin 210 and covers part of the side wall of the fin 210 and part of the top of the fin.

[0059] The material of the gate dielectric material layer includes silicon oxide or high-K dielectric material, such as HfO2, La2O3, HfSiON, HfAlO2, ZrO2, Al2O3 or HfSiO4. In this embodiment, the material of the initial gate dielectric material layer 234 is silicon oxide.

[0060] The material of the gate electrode material layer includes: polysilicon or polycrystalline germanium. In this embodiment, the material of the gate electrode material layer is polysilicon.

[0061] The process for forming the gate dielectric material layer includes: a chemical vapor deposition process or a physical vapor deposition process.

[0062] The process for forming the gate electrode material layer includes: a chemical vapor deposition process or a physical vapor deposition process.

[0063] In this embodiment, the initial gate structure 230 includes an initial first region 231 (I) and an initial second region 232 (II). Fig. 9 , the initial first region 231 covers the sidewall of the fin 210 and is located at the junction of the initial gate structure 230 and the fin 210, and the size of the initial first region 231 is d1; please refer to Fig.10 , the initial second region 232 is located on the substrate 200 and the distance from the initial first region 231 to the fin 210 is smaller than the distance from the initial second region 232 to the fin 210, and the size of the initial second region 232 is d2. Fig. 9 and Fig.10 It can be seen that the size d1 of the initial first region 231 is greater than the size d2 of the initial second region 232 .

[0064] Please continue to refer to Fig. 9The initial gate structure 230 further includes an initial third region 233 , wherein the initial third region 233 (III) is located on the top surface of the fin 210 , and the initial third region 233 is also located on the initial first region 231 .

[0065] In this embodiment, the size of the initial third area 233 is equal to the size of the initial second area 232 .

[0066] Please refer to Fig.11 and Fig.12 A protection layer 240 is formed on the surface of the initial gate structure 230 outside the initial first region 231 and on the surfaces of the fins 210 on both sides of the initial gate structure 230. Fig.11 So Fig. 9 Based on the schematic diagram, Fig.12 So Fig.10 Based on the schematic diagram.

[0067] In this embodiment, the protective layer 240 is a nitrogen-containing polymer; in other embodiments, the protective layer 240 may also be a sulfur-containing polymer or a carbon-containing polymer.

[0068] In this embodiment, the process for forming the protective layer 240 is a plasma excitation process, and specific parameters include the use of N2 gas, the N2 gas flow rate is 10 sccm to 500 sccm, the pressure is 2 mTorr to 200 mTorr, and the bias RF power is 10 W to 500 W.

[0069] In this embodiment, the purpose of forming a protective layer 240 on the surface of the initial gate structure 230 outside the initial first region 231 and on the surface of the fin 210 on both sides of the initial gate structure 230 is to ensure that the surface of the initial gate structure 230 outside the initial first region 231 and on the surface of the fin 210 on both sides of the initial gate structure 230 will not be damaged during the subsequent etching process.

[0070] In this embodiment, since the initial first region 231 is located on the side wall of the fin 210 and at the junction with the fin 210, the space in this region is small and the blocking ability is large. The protective layer 240 is not easy to gather on the surface of the initial first region 231 or cannot gather on the surface of the initial first region 231, and the protective layer 240 will not be formed on the surface of the first region 231.

[0071] Please refer to Fig.13 and Fig.14, an etching process is performed on the sidewall of the initial first region 231 to form a gate structure 250, wherein the gate structure 250 includes a first region 251 formed by etching the initial first region 231, and a second region 252 formed by etching the initial second region 232, and the size of the first region 251 is smaller than the size of the second region 252.

[0072] in Fig.13 is Fig.11 Based on the schematic diagram, Fig.14 It is a schematic diagram based on 12.

[0073] In this embodiment, the initial first region 231 of the initial gate structure 230 is etched to form the first region 251 (I) of the gate structure 250. The size of the first region 251 along the extension direction parallel to the fin 210 becomes smaller, so that the sidewall of the fin 210 covered by the first region 251 and the gate structure 250 at the junction with the fin 210 are reduced. The gate structure 250 is at a (reference Figure 8 ) is reduced, and when source-drain doped regions are subsequently formed in the fins 210 on both sides of the gate structure 250, the distance between the source-drain doped regions and the first region 251 of the gate structure 250 is increased, so that the source-drain doped regions are not easily connected to the first region 251, reducing the risk of leakage, thereby enhancing the performance of the formed semiconductor device and expanding the scope of application.

[0074] In this embodiment, reference Fig.13 The cross-sectional shape of the first region 251 along a direction parallel to the extension direction of the fin 210 and perpendicular to the surface of the substrate 200 is an inverted trapezoid.

[0075] In other embodiments, the cross-sectional shape of the first region 251 along a direction parallel to the extending direction of the fin 210 and perpendicular to the surface of the substrate 200 may also be an inverted triangle.

[0076] In this embodiment, since the protective layer 240 is formed on the surface of the initial second region 232 during the etching process of the initial first area 231, the size of the initial gate structure 230 outside the initial first area 231 and the size of the fins 210 on both sides of the initial gate structure 230 are not easily changed during the etching process, so that the second region 252 of the gate structure 250 and the fins 210 can maintain the original performance and ensure that they are not damaged, thereby improving the performance of the formed semiconductor device.

[0077] In this embodiment, the gate structure 250 includes a first region 251 formed by etching the initial first region 231 , and a second region 252 formed by etching the initial second region 232 , and the size of the first region 251 is smaller than the size of the second region 252 .

[0078] In this embodiment, reference Fig.14 The cross-sectional shape of the second region 252 of the gate structure 250 along a direction parallel to the extending direction of the fin 210 and perpendicular to the surface of the substrate 200 is a rectangle.

[0079] In this embodiment, the gate structure 250 further includes: a third region 253 , wherein the third region 253 is located on the top surface of the fin 210 , and along the extension direction of the fin 210 , the size of the first region 251 is smaller than the size of the third region 253 .

[0080] In this embodiment, the etching process used to etch the sidewall of the initial first region is a deep trench isotropic etching process.

[0081] The asynchronous pulse etching process can adopt four different etching methods during the etching process.

[0082] In this embodiment, the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power and the bias power source provides a second bias power, the first source power is equal to the second source power, and the first bias power is greater than the second bias power.

[0083] In another embodiment, the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source is turned off and the bias power source is turned off; the first source power is equal to the second source power, the first bias power is greater than the second bias power, and the third bias power is greater than the first bias power.

[0084] In another embodiment, the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned off and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source is turned off; performing a third stage etching, in which the plasma source provides a third source power and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source provides a fourth source power and the bias power source provides a fourth bias power; the third source power is equal to the fourth source power, the first bias power is greater than the third bias power, and the third bias power is greater than the fourth bias power.

[0085] In other embodiments, the etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned on and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off and the bias power source is turned off; the first bias power is less than the second bias power. In this embodiment, the pulse duty cycle of the asynchronous pulse etching process is 1% to 80%.

[0086] In this embodiment, the parameters of the asynchronous pulse etching process include: the reaction gas used includes a mixed gas of O2, CF4, CH4, Cl2 and He, wherein the flow rate of O2 is 5sccm~500sccm, the flow rate of CF4 is 10sccm~550sccm, the flow rate of CH4 is 5sccm~500sccm, the flow rate of Cl2 is 1sccm~500sccm, and the flow rate of He is 5sccm~450sccm; the pressure is 5 mTorr~100 mTorr, the source RF power is 100 W~1000 W, and the bias RF power is 200 W~2000 W.

[0087] In the present embodiment, in the method of the asynchronous pulse etching process, the source power provided by the plasma source is to excite the plasma, and the bias power provided by the bias power source is to directionally accelerate the plasma. In the first stage etching process, the first bias power provided by the bias power source is relatively large, so that the plasma has a large acceleration, so that it can quickly gather on the side wall of the initial first region 231, which is more conducive to removing the initial gate structure 230 at the junction with the fin 210, thereby reducing the gate residue formed at a; in the second stage etching process, the second bias power is reduced, and at this time the plasma has Most of them are concentrated on the side walls of the initial first region 231. At this time, the etching ability is enhanced, and it is easier to remove the initial gate structure 230 on the side walls of the initial first region 231. After the first stage etching and the second stage etching are performed alternately, the size of the first region 251 of the formed gate structure 250 along the extension direction of the fin 210 is smaller than the size of the second region 252, thereby reducing the formation of gate residues at the junction of the gate structure 250 and the fin 210, thereby avoiding the gate structure 250 and the subsequently formed source and drain doping regions from being connected, thereby avoiding the generation of leakage current, and making the formed semiconductor device have better performance.

[0088] Please refer to Fig.15 and Fig.16 , Fig.15 For Fig.13 Based on the schematic diagram, Fig.16 yes Fig.15 After the gate structure 250 is formed, source and drain doped regions 260 are formed in the fins 210 on both sides of the gate structure 250.

[0089] The method for forming the source-drain doped region 260 includes: forming source-drain openings (not shown in the figure) in the fins 210 on both sides of the gate structure 250; forming an epitaxial layer (not shown in the figure) in the source-drain openings; and doping source-drain ions into the epitaxial layer to form the source-drain doped region 260.

[0090] The material of the epitaxial layer and the conductivity type of the source and drain ions are related to the type of transistor. In this embodiment, the semiconductor device is used to form an NMOS transistor, the material of the epitaxial layer includes silicon carbide or silicon, and the source and drain ions are N-type ions, such as phosphorus ions or arsenic ions.

[0091] In other embodiments, the semiconductor device is used to form a PMOS transistor, the material of the epitaxial layer includes silicon germanium or silicon, and the source and drain ions are P-type ions, such as boron ions.

[0092] In this embodiment, the protective layer 240 is removed before forming the source-drain doping region 260 ; in other embodiments, the protective layer 240 is removed after forming the source-drain doping region 260 .

[0093] Please refer to Fig.15 and Fig.16 , the size of the gate structure 250 at the first region 251 is reduced, the gate residue formed at a of the gate structure 250 is eliminated, and the distance between the first region 251 of the gate structure 250 and the source-drain doping layer 260 is increased, so that the probability of connection between the gate structure 250 and the source-drain doping layer 260 is reduced, thereby reducing the leakage phenomenon and enhancing the performance of the formed semiconductor device.

[0094] Correspondingly, the present invention also provides a semiconductor device, comprising a substrate 200; fins 210, which are separately located on the substrate 200; and a gate structure 250, which spans the fins 210. The gate structure 250 includes a first region 251 and a second region 252. The first region 251 covers the side walls of the fins 210 and is located at the junction of the gate structure 250 and the fins 210. The second region 252 is located on the substrate 200 and the distance from the second region 252 to the fins 210 is greater than the distance from the first region 251 to the fins 210. In the extension direction of the fins, the size of the first region 251 is smaller than the size of the second region 252.

[0095] In this embodiment, the size of the gate structure 250 in the first region 251 is smaller than the size of the second region 252, wherein the first region 251 is located on the side wall of the fin 210 and at the junction with the fin 210, and the second region 262 is located on the substrate 200, and the distance from the second region 252 to the fin 210 is greater than the distance from the first region 251 to the fin 210, so that the coverage area of ​​the gate structure 250 located on the side wall of the fin 210 is reduced, and the gate residue that can be formed at the junction of the fin 210 is reduced, so that the distance between the source and drain doped regions subsequently formed in the fin 210 on both sides of the first region 251 of the gate structure 250 and the first region 261 is increased, and the probability of leakage due to connection between the first region 251 and the source and drain doped regions is reduced, so that the performance of the formed semiconductor device is improved and the scope of use of the semiconductor device is expanded.

[0096] The cross-sectional shape of the first region 251 of the gate structure 250 along a direction parallel to the extending direction of the fin 210 and perpendicular to the surface of the substrate 200 is an inverted trapezoid.

[0097] The cross-sectional shape of the second region 252 of the gate structure 250 along a direction parallel to the extending direction of the fin 210 and perpendicular to the surface of the substrate 200 is a rectangle.

[0098] It also includes: a protective layer 240 on the surface of the gate structure 250 and the surface of the fin 210 located outside the first area 251. The protective layer 240 can ensure that during the etching process, only the initial gate structure 230 located in the initial first area 231 will be etched, and the surface of the gate structure 250 and the surface of the fin 210 located outside the first area 251 will not be damaged during the etching process, which is beneficial to improving the performance of the formed semiconductor device.

[0099] In this embodiment, the protective layer 240 is a nitrogen-containing polymer; in other embodiments, the protective layer 240 may also be a carbon-containing polymer or a sulfur-containing polymer.

[0100] In this embodiment, the gate structure 250 includes: a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer; the material of the gate electrode layer includes: polysilicon or polycrystalline germanium, and the gate dielectric layer covers part of the sidewall and part of the top surface of the fin.

[0101] The gate structure further includes: a third region 253 , wherein the third region 253 is located on the top surface of the fin 210 , and along the extending direction of the fin, the size of the first region 251 is smaller than the size of the third region 253 .

[0102] In this embodiment, the semiconductor device also includes: an isolation structure 220 located on the surface of the substrate 200, the isolation structure 220 covers a portion of the side wall of the fin 210, and the top surface of the isolation structure 220 is lower than the top surface of the fin 210; the first region 251 and the second region 252 of the gate structure 250 are located on a portion of the surface of the isolation structure 220.

[0103] In this embodiment, the semiconductor device further includes: source-drain doped regions 260 located in the fins 210 on both sides of the gate structure 250 .

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; Fins are located separately from each other on the substrate; An isolation structure located on the surface of the substrate, the isolation structure covers a portion of the sidewall of the fin, and a top surface of the isolation structure is lower than a top surface of the fin; A gate structure spanning the fin, the gate structure comprising a first region, a second region and a third region, the third region being located above the first region, the first region covering the sidewall of the fin and being located at the junction of the gate structure and the fin, the second region being located on the substrate, the first region and the second region of the gate structure being located on a portion of the surface of the isolation structure, the second region being located on a side of the first region away from the fin in the extension direction of the gate structure, the size of the first region being smaller than the size of the second region in the extension direction of the fin, the size of the third region being equal to the size of the second region, the cross-sectional figure of the first region of the gate structure in a direction parallel to the extension direction of the fin and perpendicular to the surface of the substrate being an inverted trapezoid, and the cross-sectional figure of the second region of the gate structure in a direction parallel to the extension direction of the fin and perpendicular to the surface of the substrate being a rectangle.

2. The semiconductor device according to claim 1, wherein Also includes: A protection layer is located on the surface of the gate structure and the surface of the fin outside the first region.

3. The semiconductor device according to claim 2, wherein: The protective layer is a nitrogen-containing polymer, a carbon-containing polymer, or a sulfur-containing polymer.

4. The semiconductor device according to claim 1, wherein The gate structure comprises: a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer; the material of the gate electrode layer comprises: polycrystalline silicon or polycrystalline germanium, and the gate dielectric layer covers part of the sidewall and part of the top surface of the fin.

5. The semiconductor device according to claim 1, wherein: The third region is also located on the top surface of the fin, and along the extending direction of the fin, the size of the first region is smaller than that of the third region.

6. The semiconductor device according to claim 1, wherein: Also includes: Source and drain doped regions are located in the fins on both sides of the gate structure.

7. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein a surface of the substrate has a fin; forming an initial gate structure spanning the fin, the initial gate structure comprising an initial first region and an initial second region, the initial first region covering the sidewall of the fin and being located at the junction of the initial gate structure and the fin, the initial second region being located on the substrate, the initial second region being located on a side of the initial first region away from the fin in the extending direction of the initial gate structure, and the size of the initial first region being larger than the size of the initial second region in the extending direction of the fin; forming a protective layer on the surface of the initial gate structure outside the initial first region and on the surfaces of the fins on both sides of the initial gate structure; Using the protective layer as a mask, an etching process is performed on the sidewall of the initial first region to form a gate structure, wherein the gate structure includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region, wherein the size of the first region is smaller than the size of the second region along the extension direction of the fin.

8. The method for forming a semiconductor device according to claim 7, wherein: The cross-sectional shape of the first region of the gate structure along a direction parallel to the extending direction of the fin and perpendicular to the surface of the substrate is an inverted trapezoid.

9. The method for forming a semiconductor device according to claim 7, wherein: The second region of the gate structure has a rectangular cross-sectional shape along a direction parallel to an extending direction of the fin and perpendicular to a surface of the substrate.

10. The method for forming a semiconductor device according to claim 7, wherein: The etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source is turned off and the bias power source is turned off; the first source power is equal to the second source power, the first bias power is greater than the second bias power, and the third bias power is greater than the first bias power.

11. The method for forming a semiconductor device according to claim 7, wherein: The etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned off and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source is turned off; performing a third stage etching, in which the plasma source provides a third source power and the bias power source provides a third bias power; performing a fourth stage etching, in which the plasma source provides a fourth source power and the bias power source provides a fourth bias power; the third source power is equal to the fourth source power, the first bias power is greater than the third bias power, and the third bias power is greater than the fourth bias power.

12. The method for forming a semiconductor device according to claim 7, wherein: The etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source is turned on and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source is turned off and the bias power source provides a second bias power; performing a third stage etching, in which the plasma source is turned off and the bias power source is turned off; the first bias power is less than the second bias power.

13. The method for forming a semiconductor device according to claim 7, wherein: The etching process is an asynchronous pulse etching process, and the method of the asynchronous pulse etching process includes: providing a plasma source; providing a bias power source; performing a first stage etching, in which the plasma source provides a first source power, and the bias power source provides a first bias power; performing a second stage etching, in which the plasma source provides a second source power, and the bias power source provides a second bias power, the first source power is equal to the second source power, and the first bias power is greater than the second bias power.

14. The method for forming a semiconductor device according to claim 10, 11, 12 or 13, characterized in that: The pulse duty ratio of the asynchronous pulse etching process is 1% to 80%.

15. The method for forming a semiconductor device according to claim 10, 11, 12 or 13, characterized in that: The parameters of the asynchronous pulse etching process include: the reaction gas used includes a mixed gas of O2, CF4, CH4, Cl2 and He, wherein the flow rate of O2 is 5sccm~500sccm, the flow rate of CF4 is 10sccm~550sccm, the flow rate of CH4 is 5sccm~500sccm, the flow rate of Cl2 is 1sccm~500sccm, and the flow rate of He is 5sccm~450sccm; the pressure is 5 mTorr~100 mTorr, the source RF power is 100 W~1000 W, and the bias RF power is 200 W~2000 W.

16. The method for forming a semiconductor device according to claim 7, wherein: The method for forming the initial gate structure includes: forming a gate dielectric material layer and a gate electrode material layer located on the surface of the gate dielectric material layer on the substrate and the fin; patterning the gate dielectric material layer and the gate electrode material layer to form an initial gate dielectric layer and an initial gate electrode layer, wherein the initial gate structure includes an initial gate dielectric layer and an initial gate electrode layer located on the surface of the initial gate dielectric layer, and the initial gate structure covers a portion of the sidewalls of the fin and a portion of the top of the fin.

17. The method for forming a semiconductor device according to claim 16, wherein: The material of the initial gate electrode layer includes: polycrystalline silicon or polycrystalline germanium.

18. The method for forming a semiconductor device according to claim 7, wherein: The protective layer is a nitrogen-containing polymer, a carbon-containing polymer, or a sulfur-containing polymer.

19. The method for forming a semiconductor device according to claim 7, wherein: Before forming the initial gate structure, it also includes: forming an isolation structure on the surface of the substrate, the isolation structure covers part of the sidewall of the fin, and the top surface of the isolation structure is lower than the top surface of the fin; the initial gate structure is located on the surface of part of the isolation structure.

20. The method for forming a semiconductor device according to claim 7, wherein: After the gate structure is formed, it also includes: forming source-drain doped regions in the fins on both sides of the gate structure; the method for forming the source-drain doped regions includes: forming source-drain openings in the fins on both sides of the gate structure; forming an epitaxial layer in the source-drain openings; and doping source-drain ions into the epitaxial layer to form the source-drain doped regions.

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