Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate, wherein the substrate has a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to that of the body region; a gate structure located on the substrate, wherein part of the gate structure is located on the drift region, and part of the gate structure is located on the body region; a barrier layer located on the surface of part of the drift region adjacent to the gate structure; a doped layer located in the substrate or in the barrier layer, wherein the doped layer is located at the interface where the barrier layer and the drift region are in contact, and wherein the doped layer has repair ions. The repair ions can combine with the dangling bonds in the barrier layer, which is beneficial to improving the high voltage resistance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device that forms a lateral current path on the surface of a semiconductor substrate through planar diffusion. It is often used in radio frequency power circuits. In high-voltage power integrated circuits, high-voltage LDMOS is often used to meet the requirements of high-voltage resistance and power control. Compared with traditional MOS transistors, a lightly doped region is usually set between the source and drain regions of LDMOS transistors, which is called the drift region. Therefore, when the LDMOS transistor is connected to a high voltage between the source and drain regions, the drift region has a relatively low impurity concentration and is in a high-resistance state. The drift region can withstand a higher voltage drop, so the LDMOS transistor can have a higher breakdown voltage.

[0003] LDMOS transistors are compatible with complementary metal oxide semiconductor (CMOS) processes, so LDMOS transistors are widely used in power devices. For LDMOS transistors used as power integrated circuits, the on-resistance (R dson ) and breakdown voltage (Breakdown Voltage, BV) are two important indicators to measure the performance of its device.

[0004] However, the performance of existing LDMOS transistors is still poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, wherein the substrate has a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to the conductivity type of the body region; a gate structure located on the substrate, part of the gate structure is located on the drift region, and part of the gate structure is located on the body region; a barrier layer located on the surface of the drift region adjacent to the gate structure; a doping layer located in the substrate or in the barrier layer, the doping layer is located at the interface where the barrier layer and the drift region are in contact, and the doping layer has repair ions.

[0007] Optionally, the barrier layer is also located on the sidewall surface and the top surface of the gate structure.

[0008] Optionally, the barrier layer is doped with the repair ions.

[0009] Optionally, the repair ions include one or more of fluorine ions, carbon ions and nitrogen ions.

[0010] Optionally, the thickness of the doping layer ranges from 3 nanometers to 10 nanometers.

[0011] Optionally, the material of the barrier layer includes silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0012] Optionally, it also includes: a drain region located in the drift region on one side of the barrier layer and the gate structure, and a source region located in the body region on one side of the gate structure.

[0013] Optionally, the drain region and the drift region have the same conductivity type.

[0014] Optionally, the substrate further has a well region, the drift region and the body region are located in the well region, and the conductivity type of the well region is the same as the conductivity type of the drift region.

[0015] Optionally, it also includes: a lightly doped region in the substrate located on both sides of the gate structure.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to the conductivity type of the body region; forming a gate structure on the substrate, wherein part of the gate structure is located on the drift region, and part of the gate structure is located on the body region; forming an initial barrier layer on the surface of the drift region, the side wall surface and the top surface of the gate structure, and the surface of the body region; using a first ion implantation process to form a doped layer in the substrate or in the initial barrier layer, wherein the doped layer is located at the interface where the initial barrier layer and the drift region are in contact, and the doped layer has repair ions.

[0017] Optionally, the first ion implantation process further dopes the initial barrier layer with repair ions.

[0018] Optionally, the method further includes: after forming the doping layer, removing a portion of the initial barrier layer to expose the substrate surface, and forming a barrier layer on a portion of the drift region surface adjacent to the gate structure.

[0019] Optionally, the barrier layer is also located on the sidewall surface and the top surface of the gate structure.

[0020] Optionally, the method for removing part of the initial blocking layer includes: forming a patterned layer on the surface of the initial blocking layer, the patterned layer exposing a portion of the surface of the initial blocking layer on the drift region and the body region; using the patterned layer as a mask, etching the initial blocking layer until the substrate surface is exposed to form the blocking layer.

[0021] Optionally, the first ion implantation process is single-angle implantation, the implantation direction is the direction from the drain region to the source region, and the implantation angle is the direction between the implantation direction and the normal line of the substrate surface.

[0022] Optionally, the single angle ranges from 20 degrees to 45 degrees.

[0023] Optionally, the method further includes: forming a drain region in the drift region on one side of the barrier layer and the gate structure, and forming a source region in the body region on one side of the gate structure.

[0024] Optionally, the method for forming the source region and the drain region includes: using the barrier layer and the gate structure as masks, performing a second ion implantation process on the drift region and the body region to form the source region and the drain region.

[0025] Optionally, the parameters of the second ion implantation process include: an implantation angle range of 0 degrees to 15 degrees, an implantation dose of 1.0e14atom / cm 2 Up to 5.0e15atom / cm 2 , the implantation energy range is 5KeV to 40KeV.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] In the semiconductor structure provided by the technical solution of the present invention, the doped layer is located at the interface where the barrier layer and the drift region are in contact, and the doped layer contains repair ions. Since the repair ions can combine with the large number of dangling bonds existing at the interface between the barrier layer and the drift region, the charge existing in the barrier layer can be effectively reduced, thereby reducing the charge induced in the drift region located at the bottom of the barrier layer. The reduction of the charge induced in the drift region is conducive to reducing the additional electric field in the drift region, and then to increasing the breakdown voltage of the drift region, so that the high voltage resistance of the formed semiconductor structure is improved.

[0028] Furthermore, the barrier layer is doped with repair ions, which can combine with the unsaturated bonds in the barrier layer, further reducing the charge in the barrier layer, thereby further reducing the charge induced in the drift region at the bottom of the barrier layer, thereby further improving the high voltage resistance of the formed semiconductor structure.

[0029] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a doping layer is formed at the interface where the initial barrier layer and the drift region are in contact, and the doping layer contains repair ions. Since the repair ions can combine with the dangling bonds existing on the surface of the barrier layer formed subsequently, the charge existing in the barrier layer can be effectively reduced, thereby reducing the charge induced in the drift region located at the bottom of the barrier layer. The reduction of the charge induced in the drift region is conducive to reducing the additional electric field of the drift region, and then to increasing the breakdown voltage of the drift region, so that the high voltage resistance of the formed semiconductor structure is improved.

[0030] Furthermore, the first ion implantation process also dopes the initial barrier layer with repair ions. The repair ions can combine with the unsaturated bonds in the barrier layer formed subsequently, further reducing the charge in the barrier layer, thereby further reducing the charge induced in the drift region at the bottom of the barrier layer, so that the high voltage resistance of the formed semiconductor structure is further improved.

[0031] Furthermore, the first ion implantation process is a single-angle implantation process. Through the first ion implantation process, while the doping layer is formed and the repair ions are doped in the initial blocking layer, the body region is effectively blocked by the gate structure, and the body region is less doped with repair ions, which is beneficial to maintaining a good carrier mobility in the body region, and is beneficial to increasing the working current, so that the performance of the formed semiconductor structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of a cross-sectional structure of a semiconductor structure;

[0033] Figures 2 to 10 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, semiconductor structures have poor performance.

[0035] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0036] Please refer to Figure 1The semiconductor structure includes: a substrate 100, wherein the substrate 100 has a drift region 101 and a body region 102, and the conductivity type of the drift region 101 is opposite to the conductivity type of the body region 102; a gate structure 110 located on the substrate 100, wherein a portion of the gate structure 110 is located on the drift region 101, and a portion of the gate structure 110 is located on the body region 102; a barrier layer 120 located on a surface of a portion of the drift region 101 adjacent to the gate structure 110, and the barrier layer 120 is located on a top surface and a sidewall surface of the gate structure; a drain region 130 located in the drift region 101 on one side of the barrier layer 120 and the gate structure 110, and a source region 140 located in the body region 102 on one side of the gate structure 110.

[0037] In the above structure, the barrier layer 120 serves to increase the distance between the drain region 130 and the gate structure 110 .

[0038] However, the semiconductor structure is a high voltage resistant device, and when a high voltage is applied to the drain region 130 and the gate structure 110, hot carriers are easily generated in the drain region 130, resulting in unsaturated bonds in the blocking layer 120, and more dangling bonds are easily generated on the surface of the blocking layer 120, that is, charges are generated in the blocking layer 120. The charges in the blocking layer 120 are likely to induce charges in the drift region 101 at the bottom of the blocking layer 120, so that an additional electric field is generated in the drift region 101 due to the charge induction, and thus thermal collisions are easily generated, causing the drift region 101 at the bottom of the blocking layer 120 to be easily burned, resulting in poor performance.

[0039] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: after forming the initial blocking layer, using a first ion implantation process to form a doping layer in the substrate or in the blocking layer, the doping layer is located at the interface where the blocking layer and the drift region are in contact, and the doping layer contains repair ions, the repair ions can combine with a large number of dangling bonds existing at the interface between the blocking layer and the drift region, can effectively reduce the charge existing in the blocking layer, and improve the high voltage resistance of the formed semiconductor structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 10 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0042] A substrate is provided, wherein the substrate has a drift region and a body region, and the conductivity type of the drift region is opposite to the conductivity type of the body region. For the specific process of forming the substrate, the drift region and the body region located in the substrate, please refer to Figures 2 to 4 .

[0043] Please refer to Figure 2 , providing a substrate 200.

[0044] The material of the substrate 200 includes silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also include silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the substrate 200 is silicon.

[0045] In this embodiment, the substrate 200 has a well region 201 therein.

[0046] According to the type of semiconductor device to be formed, the conductivity type of the well region 201 includes: N-type or P-type.

[0047] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the well region 201 is N-type.

[0048] In this embodiment, N-type ions are doped into the substrate 200 by an ion implantation process to form the well region 201. In other embodiments, P-type ions are doped into the substrate 200 by an ion implantation process.

[0049] The N-type ions are one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type ions are one or more of boron ions, indium ions, and gallium ions.

[0050] In this embodiment, the base 200 is a planar substrate.

[0051] In other embodiments, the base includes: a substrate and a fin located on a portion of the surface of the substrate.

[0052] Please refer to Figure 3 , a doped drift region 210 is formed in the substrate 200 .

[0053] The drift region 210 is used to separate the drain region and the channel region formed subsequently, thereby extending the current channel of the semiconductor structure and improving the breakdown voltage.

[0054] The drift region 210 is doped with first ions.

[0055] The method for forming the drift region 210 includes: forming a first mask layer 211 on the surface of the substrate 200, wherein the first mask layer 211 is used to define the position and size of the drift region; performing an ion implantation process on the substrate 200 using the first mask layer 211 as a mask to form the drift region 210 in the substrate 200.

[0056] Specifically, in this embodiment, the drift region 210 is formed in the well region 201 .

[0057] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the first ions are N-type ions, including one or more of phosphorus ions, arsenic ions or antimony ions. That is, the conductivity type of the drift region 210 is N-type.

[0058] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the first ions may also be P-type ions, including: one or more of boron ions, indium ions or gallium ions.

[0059] After forming the drift region 210 , the method further includes: removing the first mask layer 211 .

[0060] In this embodiment, the material of the first mask layer 211 is photoresist, and the first mask layer 211 is removed by an ashing process.

[0061] Please refer to Figure 4 A doped body region 220 is formed in the substrate 200 , and the conductivity type of the drift region 210 is opposite to the conductivity type of the body region 220 .

[0062] The body region 220 is used to separate a source region and a channel region to be formed subsequently.

[0063] The body region 220 is doped with second ions.

[0064] The method for forming the body region 220 includes: forming a second mask layer 221 on the surface of the substrate 200, wherein the second mask layer 221 is used to define the position and size of the body region; performing an ion implantation process on the substrate 200 using the second mask layer 221 as a mask to form the body region 220 in the substrate 200.

[0065] Specifically, in this embodiment, the body region 220 is formed in the well region 201 .

[0066] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the second ions are P-type ions, including one or more of boron ions, indium ions or gallium ions. That is, the conductivity type of the body region 220 is P-type.

[0067] Since the conductivity type of the first ions is opposite to the conductivity type of the second ions, the conductivity types of the drift region 210 and the body region 220 are opposite.

[0068] In this embodiment, the drift region 210 is adjacent to the body region 220. In other embodiments, there is a gap between the drift region and the body region.

[0069] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the second ions may also be N-type ions, including: one or more of phosphorus ions, arsenic ions, or antimony ions.

[0070] After forming the body region 220 , the method further includes: removing the second mask layer 221 .

[0071] In this embodiment, the material of the second mask layer 221 is photoresist, and the second mask layer 221 is removed by an ashing process.

[0072] Please refer to Figure 5 , a gate structure 230 is formed on the substrate 200 , a portion of the gate structure 230 is located on the drift region 210 , and a portion of the gate structure 230 is located on the body region 220 .

[0073] The method for forming the gate structure 230 includes: forming a gate material layer (not shown in the figure) on the substrate 200; forming a third mask layer (not shown in the figure) on the surface of the gate material layer, wherein the third mask layer covers the gate material layer on a portion of the drift region 210 and a portion of the body region 220; using the third mask layer as a mask, etching the gate material layer until the surface of the substrate 200 is exposed, so that the gate material layer forms a gate layer 231, thereby forming the gate structure 230.

[0074] It should be noted that, in this embodiment, the method for forming the gate structure 230 also includes: before forming the gate material layer, forming a gate dielectric material layer (not shown in the figure) on the substrate 200; forming the gate material layer on the surface of the gate dielectric material layer; using the third mask layer as a mask, etching the gate dielectric material layer and the gate material layer until the surface of the substrate 200 is exposed, so that the gate dielectric material layer forms a gate dielectric layer 232, and the gate material layer forms a gate layer 231, thereby forming the gate structure 230.

[0075] The gate structure 230 includes: a gate dielectric layer 232 located on the surface of a portion of the drift region 210 and a portion of the body region 220 , and a gate layer 231 located on the surface of the gate dielectric layer 232 .

[0076] In this embodiment, the gate structure 230 further includes: a sidewall spacer 233 located on the sidewall surfaces of the gate dielectric layer 232 and the gate layer 231 .

[0077] The function of the sidewall 233 is, on the one hand, to protect the sidewall surface of the gate dielectric layer 232 and the gate layer 231 to avoid being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance; on the other hand, to be used for subsequent positioning of the lightly doped area.

[0078] The method for forming the sidewall 233 includes: forming a sidewall material layer (not shown in the figure) on the surface of the substrate 200, the top surface and sidewall surface of the gate layer 231, and the sidewall surface of the gate dielectric layer 232; and etching back the sidewall material layer until the surface of the substrate 200 and the top surface of the gate layer are exposed to form the sidewall 233.

[0079] In this embodiment, the gate structure 230 also includes: a protective layer (not shown in the figure) located on the top surface of the gate layer 231, and the protective layer is used to protect the top surface of the gate layer 231, reduce the impact of subsequent processes on the gate layer 231, and help improve the performance of the formed semiconductor structure.

[0080] Please refer to Figure 6 , a lightly doped region (not shown) is formed in the substrate 200 on both sides of the gate structure 230 .

[0081] The lightly doped region is used to effectively improve the hot carrier injection effect.

[0082] The method for forming the lightly doped region includes: using the gate structure 230 as a mask, performing an ion implantation process on the substrate 200 to form the lightly doped region in the substrate 200 .

[0083] Specifically, the lightly doped region is formed in the drift region 210 and the body region 220 respectively.

[0084] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the lightly doped region is N-type.

[0085] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the conductivity type of the lightly doped region is P-type.

[0086] Please refer to Figure 7 An initial blocking layer 240 is formed on the surface of the drift region 210 , the sidewall surface and the top surface of the gate structure 230 , and the surface of the body region 220 .

[0087] The initial barrier layer 240 provides materials for subsequently forming a barrier layer.

[0088] The material of the initial barrier layer 240 includes silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0089] In this embodiment, the material of the initial barrier layer 240 is silicon oxide.

[0090] The formation process of the initial barrier layer 240 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0091] In this embodiment, an atomic layer deposition process is used to form the initial barrier layer 240. The initial barrier layer 240 formed by the atomic layer deposition process has good step coverage, uniform thickness, and good morphology, which is beneficial to the subsequent etching of the initial barrier layer to form a barrier layer without causing over-etching to the substrate or the gate structure, and is beneficial to improving the stability of the formed semiconductor structure.

[0092] Please refer to Figure 8 A first ion implantation process is used to form a doping layer 250 in the substrate 200 or in the initial barrier layer 240 . The doping layer 250 is located at the interface where the initial barrier layer 240 and the drift region 210 are in contact, and the doping layer 250 contains repair ions.

[0093] The repair ions include: one or more of fluorine ions, carbon ions and nitrogen ions.

[0094] In this embodiment, the implanted repair ions are fluorine ions.

[0095] By forming a doping layer 250 at the interface where the initial barrier layer 240 and the drift region 210 are in contact, and the doping layer 250 contains repair ions, the repair ions can be combined with the dangling bonds existing on the surface of the barrier layer formed subsequently, so that the charge existing in the barrier layer can be effectively reduced, thereby reducing the charge induced in the drift region 210 located at the bottom of the barrier layer. The reduction of the charge induced in the drift region 210 is conducive to reducing the additional electric field of the drift region 210, and further conducive to increasing the breakdown voltage of the drift region 210, so that the high voltage resistance of the formed semiconductor structure is improved.

[0096] The first ion implantation process is a single-angle implantation process, the implantation direction is the direction from the drain region 210 to the source region 220 , and the implantation angle is the direction between the implantation direction and the normal line of the surface of the substrate 200 .

[0097] In this embodiment, the base 200 is a planar substrate, and the normal line refers to a line perpendicular to the surface of the base.

[0098] In other embodiments, the base includes: a substrate and a fin located on a surface of the substrate, and the normal line refers to a line perpendicular to the surface of the substrate.

[0099] The single angle ranges from 20 degrees to 45 degrees.

[0100] The first ion implantation process also dopes repair ions in the initial barrier layer 240. The repair ions can combine with the unsaturated bonds in the barrier layer formed subsequently, further reducing the charge in the barrier layer, thereby further reducing the charge induced in the drift region 210 at the bottom of the barrier layer, so that the high voltage resistance of the formed semiconductor structure is further improved.

[0101] The first ion implantation process is a single-angle implantation process. Through the first ion implantation process, the doping layer 250 is formed, and while the repair ions are doped into the initial blocking layer 240, the body region 220 is effectively blocked by the gate structure 230, so that the body region 220 is less doped with repair ions, which is beneficial to maintaining a good carrier mobility in the body region 220, and is beneficial to increasing the working current, so that the performance of the formed semiconductor structure is better.

[0102] Please refer to Fig. 9 After forming the doping layer 250 , a portion of the initial barrier layer 240 is removed to expose the surface of the substrate 200 , and a barrier layer 241 is formed on a portion of the surface of the drift region 250 adjacent to the gate structure 230 .

[0103] The blocking layer 241 is used to provide a gap between the drain region and the gate structure 230 to be formed subsequently, thereby extending the current channel of the semiconductor structure and improving the breakdown voltage.

[0104] The method for removing part of the initial barrier layer 240 includes: forming a patterned layer (not shown in the figure) on the surface of the initial barrier layer 240, wherein the patterned layer exposes a portion of the surface of the initial barrier layer 240 on the drift region 210 and the body region 220; using the patterned layer as a mask, etching the initial barrier layer 240 until the surface of the substrate 200 is exposed to form the barrier layer 241.

[0105] The barrier layer 241 is formed by etching the initial barrier layer 240 , and the material of the barrier layer 241 includes silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0106] Please refer to Fig.10 A drain region 260 is formed in the drift region 210 on one side of the barrier layer 241 and the gate structure 230 , and a source region 270 is formed in the body region 220 on one side of the gate structure 230 .

[0107] The method for forming the source region 260 and the drain region 270 includes: using the barrier layer 241 and the gate structure 230 as masks, performing a second ion implantation process on the drift region 210 and the body region 220 to form the source region 270 and the drain region 260 .

[0108] The parameters of the second ion implantation process include: an implantation angle range of 0 to 15 degrees, an implantation dose of 1.0e14atom / cm 2 Up to 5.0e15atom / cm 2 , the implantation energy range is 5KeV to 40KeV.

[0109] The angle range of the implantation refers to the angle between the implantation direction and the surface normal of the substrate 200 .

[0110] The drain region 260 is doped with third ions, and the source region 270 is doped with fourth ions, and the third ions and the fourth ions have the same conductivity type.

[0111] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the third ions and the fourth ions are N-type ions, including: one or more of phosphorus ions, arsenic ions or antimony ions. Accordingly, the conductivity types of the drain region 260 and the source region 270 are both N-type.

[0112] In this embodiment, phosphorus ions are implanted into both the drift region 210 and the body region 220 through the second ion implantation process.

[0113] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.10 , including: a substrate 200, wherein the substrate 200 has a doped drift region 210 and a doped body region 220, and the conductivity type of the drift region 210 is opposite to the conductivity type of the body region 220; a gate structure 230 located on the substrate 200, wherein part of the gate structure 230 is located on the drift region 210, and part of the gate structure 239 is located on the body region 220; a barrier layer 241 located on the surface of a portion of the drift region 210 adjacent to the gate structure 230; a doping layer 250 located in the substrate 200 or in the barrier layer 241, wherein the doping layer 250 is located at the interface where the barrier layer 241 and the drift region 210 are in contact, and the doping layer 250 has repair ions.

[0114] Since the doping layer 250 is located at the interface where the barrier layer 241 and the drift region 210 are in contact, and the doping layer 250 contains repair ions. Since the repair ions can combine with the large number of dangling bonds existing at the interface between the barrier layer 241 and the drift region 210, the charge existing in the barrier layer 241 can be effectively reduced, thereby reducing the charge induced in the drift region 210 located at the bottom of the barrier layer 241. The reduction of the charge induced in the drift region 210 is conducive to reducing the additional electric field of the drift region 210, and further conducive to improving the breakdown voltage of the drift region 210, so that the high voltage resistance of the formed semiconductor structure is improved.

[0115] The following is a detailed description with reference to the accompanying drawings.

[0116] In this embodiment, a well region 201 is defined in the substrate 200 , and the drift region 210 and the body region 220 are located in the well region 201 .

[0117] The barrier layer 241 is also located on the sidewall surfaces and the top surface of the gate structure 230 .

[0118] Specifically, in this embodiment, the repair ions are doped in the barrier layer 241. Since the repair ions are doped in the barrier layer 241, the repair ions can be combined with the unsaturated bonds in the barrier layer 241, which can further reduce the charge in the barrier layer 241, thereby further reducing the charge induced in the drift region 210 at the bottom of the barrier layer 241, so that the high voltage resistance of the formed semiconductor structure is further improved.

[0119] The repair ions include: one or more of fluorine ions, carbon ions and nitrogen ions.

[0120] The thickness of the doping layer 250 is in a range of 3 nanometers to 10 nanometers.

[0121] The significance of selecting the thickness range is that: if the thickness is greater than 10 nanometers, the repair ions doped in the doping layer will easily have a certain impact on the mobility of the carriers in the drain region 210, thereby affecting the working current, which is not conducive to the performance of the formed semiconductor structure; if the thickness is less than 3 nanometers, the repair ions still cannot effectively combine with the dangling bonds existing at the interface between the blocking layer 241 and the drift region 210, and thus cannot effectively reduce the charge in the blocking layer 241, which is not conducive to improving the high voltage resistance of the formed semiconductor structure.

[0122] The material of the blocking layer 241 includes silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0123] The drift region 210 is doped with first ions, which are N-type ions or P-type ions; the body region is doped with second ions, which are N-type ions or P-type ions.

[0124] In this embodiment, the semiconductor structure further includes: a drain region 260 located in the drift region 210 on one side of the barrier layer 241 and the gate structure 230 , and a source region 270 located in the body region 220 on one side of the gate structure 230 .

[0125] The drain region 260 is doped with third ions, and the source region 270 is doped with fourth ions, and the third ions and the fourth ions have the same conductivity type.

[0126] The third ion is an N-type ion or a P-type ion.

[0127] The fourth ion is an N-type ion or a P-type ion.

[0128] The drain region 260 and the drift region 210 have the same conductivity type.

[0129] In this embodiment, the semiconductor structure further includes: lightly doped regions (not shown in the figure) in the bottom of the substrate 200 located on both sides of the gate structure 230 .

[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to the conductivity type of the body region; a gate structure located on the substrate, a portion of the gate structure located on the drift region, and a portion of the gate structure located on the body region; a barrier layer located on a surface of a portion of the drift region adjacent to the gate structure; A doping layer located in the substrate, the doping layer is located at the interface where the barrier layer and the drift region are in contact, and the doping layer has repair ions, and the barrier layer is doped with the repair ions; Alternatively, the doping layer is located in the barrier layer, the doping layer is located at the interface where the barrier layer and the drift region are in contact, and the doping layer contains repair ions.

2. The semiconductor structure according to claim 1, wherein: The barrier layer is also located on the sidewall surfaces and the top surface of the gate structure.

3. The semiconductor structure according to claim 1, wherein: When the doping layer is located in the barrier layer, the barrier layer is doped with the repair ions.

4. The semiconductor structure according to claim 3, characterized in that The repair ions include: one or more of fluorine ions, carbon ions and nitrogen ions.

5. The semiconductor structure according to claim 1, wherein: The thickness of the doping layer ranges from 3 nanometers to 10 nanometers.

6. The semiconductor structure according to claim 1, wherein: The material of the barrier layer includes silicon oxide, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

7. The semiconductor structure according to claim 1, wherein: Also includes: A drain region is located in the drift region on one side of the barrier layer and the gate structure, and a source region is located in the body region on one side of the gate structure.

8. The semiconductor structure according to claim 7, wherein: The drain region and the drift region have the same conductivity type.

9. The semiconductor structure according to claim 1, wherein: The substrate also has a well region, the drift region and the body region are located in the well region, and the conductivity type of the well region is the same as the conductivity type of the drift region.

10. The semiconductor structure according to claim 1, wherein: Also includes: Lightly doped regions are located in the substrate on both sides of the gate structure.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to the conductivity type of the body region; forming a gate structure on the substrate, wherein a portion of the gate structure is located on the drift region, and a portion of the gate structure is located on the body region; forming an initial barrier layer on the surface of the drift region, the sidewall surface and the top surface of the gate structure, and the surface of the body region; Using a first ion implantation process to form a doping layer in the substrate; Alternatively, a first ion implantation process is used to form a doped layer in the initial barrier layer; Removing part of the initial barrier layer to expose the substrate surface, and forming a barrier layer on the surface of the drift region adjacent to the gate structure, wherein the barrier layer is doped with repair ions; The doping layer is located at the interface where the barrier layer and the drift region are in contact, and the doping layer contains repair ions.

12. The method for forming a semiconductor structure according to claim 11, wherein: The first ion implantation process further dopes the initial barrier layer with repair ions.

13. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the doping layer, a portion of the initial barrier layer is removed to expose the substrate surface, and a barrier layer is formed on a portion of the drift region surface adjacent to the gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The barrier layer is also located on the sidewall surfaces and the top surface of the gate structure.

15. The method for forming a semiconductor structure according to claim 13, wherein: The method for removing part of the initial barrier layer includes: forming a patterned layer on the surface of the initial barrier layer, wherein the patterned layer exposes the surface of the initial barrier layer on part of the drift region and the body region; using the patterned layer as a mask, etching the initial barrier layer until the substrate surface is exposed to form the barrier layer.

16. The method for forming a semiconductor structure according to claim 13, wherein: The first ion implantation process is single-angle implantation, the implantation direction is the direction from the drain region to the source region, and the implantation angle is the direction between the implantation direction and the normal line of the substrate surface.

17. The method for forming a semiconductor structure according to claim 16, wherein: The single angle ranges from 20 degrees to 45 degrees.

18. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: A drain region is formed in the drift region on one side of the barrier layer and the gate structure, and a source region is formed in the body region on one side of the gate structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the source region and the drain region comprises: using the barrier layer and the gate structure as masks, performing a second ion implantation process on the drift region and the body region to form the source region and the drain region.

20. The method for forming a semiconductor structure according to claim 19, wherein: The parameters of the second ion implantation process include: an implantation angle range of 0 to 15 degrees, an implantation dose of 1.0e14atom / cm 2 Up to 5.0e15atom / cm 2 , the implantation energy range is 5KeV to 40KeV.

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