Integrated passive components

Abstract

The subject of the present invention is to provide an integrated passive component which is not prone to cracks caused by thermal stress and can suppress the degradation of the characteristics of the passive circuit. A capacitor is arranged on an insulating substrate. An inductor including a conductor pattern having at least one end connected to the capacitor is also arranged on the substrate. The capacitor has a dielectric film mainly including the same constituent elements as the substrate, and at least two electrodes facing each other with the dielectric film sandwiched therebetween.

Description

Technical Field

[0001] The present invention relates to an integrated passive component formed by integrating a plurality of passive components. Background Art

[0002] With the rapid popularization of electronic devices with wireless communication functions, a large number of high-frequency bands are used in wireless communications. If a communication module mounted on an electronic device is multi-band and corresponds to multiple communication standards (multi-mode), the communication module will be enlarged. In order to suppress the enlargement of the communication module, it is preferred that the electronic components mounted on the communication module are miniaturized, thinned, and highly integrated. For the high-frequency front-end module of the communication module mounted on a portable terminal, etc., miniaturization, thinness, high Q value, etc. are required.

[0003] In order to realize high integration of communication modules, technologies such as three-dimensional mounting and embedding components in package substrates are applied. In addition, integrated passive components such as noise filters and band filters are required to be thinner and smaller.

[0004] Passive components in which a capacitance element is formed on a substrate made of an insulating material or a semiconductor material (Patent Document 1) and LC filters including capacitors and inductors formed on a conductive substrate (Patent Document 2) are known.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-186495

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-21997

[0007] Due to the difference between the linear expansion coefficient of the substrate and the linear expansion coefficient of the dielectric film of the capacitor, thermal stress is generated in the capacitor and its surroundings. If the thermal stress becomes large, cracks may sometimes be generated in the insulating film around the capacitor. The cracks become the main cause of the reduction in quality such as moisture resistance.

[0008] In addition, if a semiconductor material is used in the substrate, a low-resistance layer in which carriers are accumulated is sometimes generated at the interface between the substrate and the insulating film on the substrate. Due to this low-resistance layer, the insulation between multiple passive components and circuits formed on the substrate is reduced. If the temperature of the substrate rises, the resistance of the low-resistance layer decreases, so the characteristics of the passive components are further deteriorated in a high-temperature environment.

[0009] If a conductive material is used for the substrate, an alternating magnetic field generated by an inductor formed on the substrate generates eddy currents in the substrate. The eddy currents increase the loss and reduce the Q value of the inductor and the Q value of the filter circuit. Summary of the invention

[0010] An object of the present invention is to provide an integrated passive component which is less likely to generate cracks due to thermal stress and can suppress degradation of characteristics of a passive circuit.

[0011] According to one aspect of the present invention, there is provided an integrated passive component having:

[0012] Insulating substrate;

[0013] A capacitor disposed on the substrate; and

[0014] an inductor, arranged on the substrate, comprising a conductor pattern at least one end of which is connected to the capacitor,

[0015] The capacitor includes a dielectric film and at least two electrodes facing each other with the dielectric film interposed therebetween, wherein the dielectric film mainly includes the same constituent elements as those of the substrate.

[0016] The dielectric film of the capacitor mainly contains the same constituent elements as the substrate, so that the difference between the linear expansion coefficient of the substrate and the linear expansion coefficient of the dielectric film becomes smaller. As a result, the thermal stress generated in the dielectric film is reduced. Due to the reduction of thermal stress, the generation of cracks caused by thermal stress is suppressed. Thus, the high reliability of the passive circuit can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a diagram showing the positional relationship of the components of the integrated passive component according to the first embodiment in a plan view, Figure 1B is an equivalent circuit diagram of the integrated passive components based on the first embodiment.

[0018] Figure 2A is a diagram showing the positional relationship between the conductor pattern of the lower electrode layer and the conductor pattern of the upper electrode layer in a plan view, Figure 2B It is a diagram showing the positional relationship between the conductor pattern of the upper electrode layer and the conductor pattern of the first wiring layer in a plan view. Figure 2C The diagram shows the positional relationship between the conductor pattern of the first wiring layer and the conductor pattern of the second wiring layer in a plan view.

[0019] Figure 3A is a diagram showing the positional relationship between the conductor pattern of the second wiring layer and the conductor pattern of the third wiring layer in a plan view, Figure 3B It is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and a plurality of external connection terminals arranged on the uppermost conductor layer in a plan view.

[0020] Figure 4 yes Figure 1A A cross-sectional view taken along the dotted line 4-4.

[0021] Figure 5A , Figure 5B , Figure 5C ,as well as Figure 5D is a cross-sectional view of an integrated passive component at a mid-stage of manufacturing.

[0022] Fig. 6A , Figure 6B ,as well as Figure 6C is a cross-sectional view of an integrated passive component at a mid-stage of manufacturing.

[0023] Fig. 7A and Figure 7B is a cross-sectional view of an integrated passive component at a mid-stage of manufacturing.

[0024] Fig. 8A is a diagram showing the positional relationship of the components of the integrated passive component according to the second embodiment in a plan view, Figure 8B is an equivalent circuit diagram of the integrated passive components based on the second embodiment.

[0025] Fig.9A is a diagram showing the positional relationship between the conductor pattern of the lower electrode layer and the conductor pattern of the upper electrode layer in a plan view, Fig. 9B It is a diagram showing the positional relationship between the conductor pattern of the upper electrode layer and the conductor pattern of the first wiring layer in a plan view.

[0026] Fig. 10A is a diagram showing the positional relationship between the conductor pattern of the first wiring layer and the conductor pattern of the second wiring layer in a plan view, Fig. 10B It is a diagram showing the positional relationship between the conductor pattern of the second wiring layer and the conductor pattern of the third wiring layer in a plan view.

[0027] Fig.11 It is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and the external connection terminal in a plan view.

[0028] Fig.12 is a cross-sectional view of a capacitor portion of the integrated passive component according to the third embodiment.

[0029] Fig.13 is a cross-sectional view of an integrated passive component according to a fourth embodiment.

[0030] Fig.14A is a cross-sectional view of an integrated passive component according to a fifth embodiment, Fig. 14B and Fig. 14C They are cross-sectional views of the lower electrode and the conductor pattern, respectively.

[0031] Description of Reference Numerals

[0032] 11…lower electrode; 11A…first electrode; 11B…third electrode; 11L…lower conductor layer; 11U…upper conductor layer; 21…upper electrode; 21A…second electrode; 21B…fourth electrode; 22, 22A, 22B, 23…conductor pattern; 31…conductor pattern constituting a part of the inductor; 31A…surrounding portion; 31B…extending portion; 32…conductor pattern; 41…conductor pattern constituting a part of the inductor; 41L…lower conductor layer; 41U…upper conductor layer; 42, 43…conductor pattern; 51…constituting a part of the inductor Conductor pattern; 51L...inner pad; 52, 53...conductor pattern; 52L, 53L, 54L...inner pad; 61...substrate; 62, 62A, 62B, 62C...dielectric film; 63...first insulating film; 65...base layer; 71, 72, 73...second insulating film; 101, 102, 103, 104, 105, 106...lower electrode; 111A, 111B, 112A, 112B, 113A, 114A, 114B, 115A, 116A, 116B...upper electrode; 113B, 115B...conductor pattern ; 121, 122, 124...a conductor pattern constituting a part of an inductor; 123, 125A, 125B, 126, 127A, 127B, 128A, 128B, 129...a conductor pattern; 131, 132, 133, 134, 135...a conductor pattern constituting a part of an inductor; 136A, 136B, 136C, 136D, 136E, 136F, 136G...a conductor pattern; 141, 142, 143, 144, 145...a conductor pattern constituting a part of an inductor; 146A, 146B, 146C, 147D, 148E, 149F, 150G...a conductor pattern; 6C, 146D…conductor pattern; 201…photoresist film; 201A…opening; 202…conductor film; 203…metal laminate film; 204…photoresist film; 204A…opening; C, C1, C2, C3, C4, C5, C6…capacitor; DMY…dummy terminal; GND…ground terminal; H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13…via hole; In…input terminal; L, L1, L2, L3, L4, L5…inductor; Out…output terminal. DETAILED DESCRIPTION

[0033] [First embodiment]

[0034] Reference Figure 1A to Figure 7B The integrated passive component based on the first embodiment is described with reference to the accompanying drawings of the specification.

[0035] Figure 1A is a diagram showing the positional relationship of the components of the integrated passive component according to the first embodiment in a plan view, Figure 1B: is an equivalent circuit diagram of the integrated passive component according to the first embodiment. The integrated passive component according to the first embodiment has a capacitor C, an inductor L, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY provided on an insulating substrate.

[0036] Multiple conductor layers and multiple insulating films for insulating the upper and lower adjacent conductor layers are stacked on the substrate. In the first embodiment, six conductor layers are stacked, and these conductor layers are called the lower electrode layer, the upper electrode layer, the first wiring layer, the second wiring layer, and the third wiring layer in order from the substrate side. The uppermost conductor layer is provided with multiple external connection terminals such as the input terminal In, the output terminal Out, and the ground terminal GND. Figure 1A In the figure, each conductor layer is marked with different shades and directions. The shape and positional relationship of the conductor patterns arranged in each conductor layer will be described later. Figure 2A to Figure 3B The accompanying drawings are described in detail.

[0037] like Figure 1B As shown, an inductor L is connected between the input terminal In and the output terminal Out, and a capacitor C is connected between the input terminal In and the ground terminal GND. The integrated passive component according to the first embodiment functions as a low-pass filter.

[0038] Reference Figure 2A to Figure 3B The structure of the conductor patterns of two conductor layers adjacent to each other is described in the accompanying drawings. Figure 2A to Figure 3B In the drawings, the conductor pattern of the wiring layer on the relatively lower side is indicated by a dotted line.

[0039] Figure 2A 1 is a diagram showing the positional relationship between the conductor pattern of the lower electrode layer and the conductor pattern of the upper electrode layer in a plan view. The conductor pattern that becomes the lower electrode 11 of the capacitor C is arranged on the lower electrode layer. The conductor pattern that becomes the upper electrode 21 of the capacitor C and other conductor patterns 22 are arranged on the upper electrode layer. In a plan view, the upper electrode 21 and the conductor pattern 22 overlap with the lower electrode 11. The conductor pattern 22 is connected to the lower electrode 11 through a conduction hole H1 provided in the insulating film.

[0040] Figure 2B: This is a diagram showing the positional relationship between the conductor pattern of the upper electrode layer and the conductor pattern of the first wiring layer when viewed from above. The first wiring layer is provided with a conductor pattern 31 and another conductor pattern 32. The conductor pattern 31 is composed of a surrounding portion 31A and an extension portion 31B. The surrounding portion 31A is approximately one circle along the outer periphery of a rounded square that is arranged at a position that does not overlap with the capacitor C when viewed from above, and the extension portion 31B extends from one end of the surrounding portion 31A and passes through a position that overlaps with the conductor pattern 22 of the upper electrode layer. The surrounding portion 31A constitutes a part of the inductor L. The extension portion 31B is connected to the conductor pattern 22 of the upper electrode layer through the via H2. That is, the conductor pattern 31 is connected to the lower electrode 11 ( Figure 2A )connect.

[0041] In a plan view, one end of the conductor pattern 32 overlaps with the upper electrode 21 of the capacitor C. The conductor pattern 32 is connected to the upper electrode 21 through the via H3 .

[0042] Figure 2C 1 is a diagram showing the positional relationship between the conductor pattern of the first wiring layer and the conductor pattern of the second wiring layer in a plan view. The conductor pattern 41 constituting a part of the inductor L and other conductor patterns 42 and 43 are arranged in the second wiring layer. The conductor pattern 41 is composed of a portion roughly overlapping with the conductor pattern 31 of the first wiring layer and a portion arranged inside the conductor pattern 31 and parallel to the outer portion for approximately one circle. That is, the conductor pattern 41 has a spiral (spiral) shape with a number of turns of about 2. The end of the outer peripheral side of the conductor pattern 41 is connected to the end of one side of the conductor pattern 31 of the first wiring layer through the via H4.

[0043] The conductor pattern 42 is connected to the other end of the conductor pattern 31 of the first wiring layer through the via H5. The conductor pattern 43 is connected to the conductor pattern 32 of the first wiring layer through the via H6.

[0044] Figure 3A 1 is a diagram showing the positional relationship between the conductor pattern of the second wiring layer and the conductor pattern of the third wiring layer in a plan view. The conductor pattern 51 constituting a part of the inductor L and other conductor patterns 52 and 53 are arranged on the third wiring layer. The conductor pattern 51 has a spiral shape arranged to overlap with the conductor patterns on the inner and outer sides of the conductor pattern 41 of the second wiring layer. The end of the inner side of the conductor pattern 51 is connected to the end of the inner side of the conductor pattern 41 of the second wiring layer through the via H7. An inner layer pad 51L having a circular planar shape is connected to the end of the outer side of the conductor pattern 51.

[0045] The conductor patterns 52 and 53 are connected to the conductor patterns 42 and 43 of the second wiring layer through the via holes H8 and H9, respectively. Inner layer pads 52L and 53L having a circular planar shape are connected to the ends of the conductor patterns 52 and 53, respectively. In addition, an isolated inner layer pad 54L having a circular planar shape is arranged which is not connected to other conductor patterns of the lower layer than the third wiring layer.

[0046] Figure 3B 1 is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and the plurality of external connection terminals arranged on the uppermost conductor layer when viewed from above. The plurality of external connection terminals include an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY. The output terminal Out is connected to the inner layer pad 51L through a via H10. The input terminal In is connected to the inner layer pad 52L through a via H11. The ground terminal GND is connected to the inner layer pad 53L through a via H12. The dummy terminal DMY is connected to the inner layer pad 54L through a via H13.

[0047] That is, the conductor patterns 31, 41, and 51 constituting a part of the inductor constitute the inductor L with the thickness direction of the substrate as the coil axial direction. One end of the inductor L is connected to the conductor pattern 22 ( Figure 2A , Figure 2B ) and the lower electrode 11 of the capacitor C ( Figure 2A ) is connected. The other end of the inductor L is connected via the inner layer pad 51L ( Figure 3A ) and output terminal Out( Figure 3B ) is connected. The upper electrode 21 of the capacitor C ( Figure 2A ) through the conductor patterns 32, 43, 53, and the inner pad 53L ( Figure 2B , Figure 2C , Figure 3A ) and the ground terminal GND( Figure 3B ) connection. In top view, the inductor L( Figure 1A ) is configured without capacitor C( Figure 1A ) overlap.

[0048] Figure 4 yes Figure 1A A cross-sectional view along the dotted line 4-4.

[0049] The lower electrode 11 is arranged on a part of one surface (hereinafter referred to as the upper surface) of the insulating substrate 61. The dielectric film 62 covers the upper surface of the substrate 61 and the lower electrode 11. The upper electrode 21 and the conductor pattern 22 are arranged on the dielectric film 62. The conductor pattern 22 is connected to the lower electrode 11 through the conductive hole H1 provided in the dielectric film. The lower electrode 11 and the upper electrode 21 sandwich the dielectric film 62 from top to bottom to form a capacitor C.

[0050] The first insulating film 63 covers the upper electrode 21, the conductor pattern 22, and the dielectric film 62. That is, the first insulating film 63 covers the capacitor C. The surrounding portion 31A and the extending portion 31B of the conductor pattern 31, and the conductor pattern 32 are arranged on the first insulating film 63. Figure 4 In the cross section shown, one conductor pattern 31 constituting a part of the inductor L appears in three places. The conductor pattern 31 is connected to the conductor pattern 22 via a via H2 provided in the first insulating film 63 . The conductor pattern 32 is connected to the upper electrode 21 via a via H3 provided in the first insulating film 63 .

[0051] The first-layer second insulating film 71 covers the conductor patterns 31, 32 and the first insulating film 63. The conductor pattern 41 constituting a part of the inductor L and other conductor patterns 42 are arranged on the first-layer second insulating film 71. Figure 4 In the cross section shown, one conductor pattern 41 appears at four locations. Of the conductor patterns 41 that appear at four locations, the conductor patterns 41 at both ends are arranged so as to overlap with the conductor pattern 31 of the lower layer when viewed from above. The conductor pattern 42 is connected to the conductor pattern 31 of the lower layer through the via H5 provided in the second insulating film 71.

[0052] The second insulating film 72 of the second layer covers the conductor patterns 41 and 42 of the second wiring layer and the second insulating film 71 of the first layer. The conductor pattern 51 constituting a part of the inductor L, other conductor patterns 52, and the inner pad 52L are arranged on the second insulating film 72 of the second layer. Figure 4 In the cross section shown, one conductor pattern 51 appears at four locations. The conductor pattern 51 that appears at the four locations is arranged at a position overlapping with the conductor pattern 41 of the lower layer when viewed from above. The conductor pattern 52 is connected to the conductor pattern 42 of the lower layer through the via H8 provided in the second insulating film 72. In this way, the inductor L includes the conductor patterns 31, 41, and 51 arranged above and below at least one layer of the second insulating films 71, 72, and 73, respectively. In addition, the inductor L has a spiral structure with a direction perpendicular to the upper surface of the substrate 61 as the central axis, and has a helical structure.

[0053] The third layer second insulating film 73 covers the conductor patterns 51 and 52 and the second layer second insulating film 72. The input terminal In is arranged on the third layer second insulating film 73. The input terminal In is connected to the lower layer inner pad 52L through the via hole H11 provided in the second insulating film 73.

[0054] Next, an example of the material used for each component of the integrated passive component and the size of each component will be described.

[0055] The substrate 61, the dielectric film 62, and the first insulating film 63 are formed of an insulating material mainly containing the same constituent elements. For example, the substrate 61, the dielectric film 62, and the first insulating film 63 are formed of an insulating material mainly containing silicon and nitrogen as constituent elements. For example, silicon nitride (SiN) ceramics is used for the substrate 61, and silicon nitride in an amorphous state is used for the dielectric film 62 and the first insulating film 63.

[0056] Here, "mainly contains" means that other elements may be contained to the extent that they do not have a significant effect on the linear expansion coefficient and volume resistivity of the material. The linear expansion coefficient of silicon nitride is 2.5×10 －6 / ℃, volume resistivity ratio 10 14 Ω·cm is large. For example, when the content of a constituent element is 50 mol % or more, it can be considered that the constituent element is mainly contained. For example, when the content of oxygen and carbon in silicon nitride (SiON) containing oxygen and silicon carbide (SiCN) containing carbon in silicon nitride is less than 50 mol %, it can be considered that the material mainly contains silicon and nitrogen.

[0057] Resin, such as epoxy resin, polyimide resin, etc., is used in the second insulating films 71, 72, 73. The Young's modulus of the insulating material used in the second insulating films 71, 72, 73 is smaller than the Young's modulus of the insulating material used in the substrate 61, the dielectric film 62, and the first insulating film 63. For example, the Young's modulus of the insulating material used in the second insulating films 71, 72, 73 is less than 10 GPa. For example, the Young's modulus of the epoxy film is in the range of more than 2 GPa and less than 8 GPa. In addition, in order to make the linear expansion coefficient of the second insulating films 71, 72, 73 close to the linear expansion coefficient of the substrate 61, a composite material containing an inorganic insulating material in the resin can also be used as the second insulating films 71, 72, 73.

[0058] Au, Al, or Cu, which is a metal material with high conductivity, is used for the lower electrode 11, the upper electrode 21, and the conductor pattern 22 of the capacitor C. Au, Al, Cu, or a metal material mainly composed of Cu is used for the conductor patterns 31, 41, and 51 constituting the inductor L, and the conductor patterns 32, 42, 43, 52, and 53 arranged in the same wiring layer as these. In addition, it is preferable to use Cu or a metal material mainly composed of Cu, which is easy to thicken.

[0059] The input terminal In, the output terminal Out, the ground terminal GND, and the dummy terminal DMY include a main part made of Au, Al, Cu, or Cu as a main component, and an anti-oxidation film covering the surface of the main part. For example, NiAu, NiPaAu, etc. are used in the anti-oxidation film. In addition, a solder layer of NiSn, NiSnAg, etc. may be added to these external connection terminals.

[0060] The thickness of the substrate 61 is adjusted according to the required specifications of the height of the integrated passive components. For example, the thickness of the substrate 61 is 50 μm or more and 300 μm or less. The thickness of the dielectric film 62 is determined by the capacitance required by the capacitor C, the withstand voltage characteristics, the moisture resistance, etc. For example, the thickness of the dielectric film 62 is 30 nm or more and 500 nm or less. The thickness of the first insulating film 63 is mainly determined by the moisture resistance required by the capacitor C. For example, the thickness of the first insulating film 63 is 100 nm or more and 1000 nm or less.

[0061] To ensure sufficient coverage of the dielectric film 62, the thickness of the lower electrode 11 is preferably set to be less than the thickness of the dielectric film 62. To ensure sufficient coverage of the first insulating film 63, the thickness of the upper electrode 21 and the conductive pattern 22 is preferably set to be less than the thickness of the first insulating film 63.

[0062] In order to maintain the Q value of the inductor L high, it is preferable to reduce the resistance of the conductor patterns 31, 41, 51 constituting the inductor L. In order to reduce the resistance of the conductor patterns 31, 41, 51, it is preferable to make the conductor patterns 31, 41, 51 as thick as possible. For example, it is preferable to make the thickness of the conductor patterns 31, 41, 51 5 times or more the thickness of the lower electrode 11 and the upper electrode 21 of the capacitor C. For example, it is preferable to set the thickness of the conductor patterns 31, 41, 51 to about 5 μm, and set the thickness of the lower electrode 11 and the upper electrode 21 to 1 μm or less.

[0063] Next, refer to Figure 5A to Figure 7B The manufacturing method of the integrated passive component based on the first embodiment is described with reference to the accompanying drawings. Figure 5A to Figure 7B The accompanying drawing is a cross-sectional view of an integrated passive component at an intermediate stage of manufacture.

[0064] like Figure 5A As shown in FIG. 1 , a photoresist film 201 is formed on the upper surface of the substrate 61, and an opening 201A is formed in a predetermined region where the lower electrode 11 is to be formed. A conductor film 202 that becomes the lower electrode 11 is formed by vacuum evaporation on the upper surface of the substrate 61 exposed at the bottom of the opening 201A and on the photoresist film 201. The conductor film 202 is composed of two layers, for example, a Ti film with a thickness of 50 nm and an Au film with a thickness of 100 nm. The photoresist film 201 is removed together with the conductor film 202 formed thereon. As a result, as shown in FIG. Figure 5B As shown, the lower electrode 11 is left on the substrate 61.

[0065] like Figure 5C As shown in FIG. 1 , a dielectric film 62 is formed by a plasma CVD method so as to cover the upper surface of the substrate 61 and the lower electrode 11. Then, as shown in FIG. Figure 5DAs shown, a via hole H1 is formed in the dielectric film 62 by reactive ion etching (RIE). A portion of the lower electrode 11 is exposed in the via hole H1.

[0066] Next, if Fig. 6A As shown in FIG. 1 , the upper electrode 21 and the conductor pattern 22 are formed on the dielectric film 62 by the same process as the formation of the lower electrode 11. Then, the first insulating film 63 is formed by the plasma CVD method so as to cover the upper electrode 21, the conductor pattern 22, and the dielectric film 62. Furthermore, the via holes H2 and H3 are formed in the first insulating film 63 by the reactive ion etching method.

[0067] like Figure 6B As shown, a metal stacked film 203 is formed by sputtering to cover the upper surface of the first insulating film 63, and the side and bottom surfaces of the via holes H2 and H3. The metal stacked film 203 is composed of two layers of a Ti film and a Cu film thereon. A photoresist film 204 is formed on the metal stacked film 203, and an opening 204A is formed in a predetermined area for forming a conductor pattern. By electroplating using the metal stacked film 203 as a seed layer, Cu is precipitated in the opening 204A. Thus, the conductor patterns 31 and 32 are formed in the opening 204A.

[0068] Then, the photoresist film 204 is removed by an organic solvent, and the metal stack film 203 is further removed by wet etching. Figure 6C As shown, the conductor patterns 31 and 32 are formed. A metal layered film 203 used as a seed layer for electroplating is left under the conductor patterns 31 and 32. Fig. 7A The following drawings and Figure 4 In the figure, the description of the metal stacked film 203 is omitted.

[0069] Next, if Fig. 7A As shown in FIG. 1 , a first layer of the second insulating film 71 is formed to cover the conductor patterns 31, 32 and the first insulating film 63. The second insulating film 71 is formed by laminating a semi-cured epoxy resin film (B stage) mixed with a photosensitive material using a vacuum lamination method. There are steps on the base surface of the second insulating film 71 caused by the conductor patterns 31, 32, etc., but the upper surface of the second insulating film 71 is substantially flat.

[0070] like Figure 7B As shown, a portion of the second insulating film 71 is exposed to light and developed with an alkaline solution to form a via hole H5. A portion of the conductor pattern 31 is exposed in the via hole H5. Then, a heat treatment is performed to cure the epoxy resin film in a semi-cured state.

[0071] repeat Figure 6B to Figure 7B process, thus forming Figure 4 The laminated structure of the conductor patterns 41, 42 to the second insulating film 73 of the third layer is shown. In addition, external connection terminals such as the input terminal In are formed, and a NiAu anti-oxidation film is formed on the surface of the external connection terminals by a non-electroplating method. Then, the lower surface of the substrate 61 is ground by a back grinding method until the substrate 61 reaches the desired thickness. After grinding, the substrate 61 is divided into pieces by a cutting process to obtain an integrated passive component.

[0072] Next, the excellent effects of the first embodiment will be described.

[0073] In the first embodiment, the dielectric film 62 ( Figure 4 ) mainly comprises a substrate 61 ( Figure 4 ) is formed of insulating materials with the same constituent elements. Therefore, the difference in linear expansion coefficients between the two becomes smaller, and the thermal deformation and residual thermal stress that may occur in the manufacturing process are reduced. As a result, in the capacitor C ( Figure 4 ) is less likely to generate cracks due to thermal stress in the insulating material around the substrate. This can suppress the reduction in moisture resistance due to cracks and improve the quality of the integrated passive components.

[0074] Furthermore, in the first embodiment, the first insulating film 63 ( Figure 4 ) is also formed of an insulating material containing the same constituent elements as the substrate 61. Therefore, cracks caused by thermal stress are less likely to occur in the insulating material around the capacitor C.

[0075] Since an insulating material is used in the substrate 61, it is possible to suppress the reduction of insulation between the plurality of passive elements integrated in the integrated passive component. In addition, even if an alternating magnetic field is generated due to the high-frequency current flowing through the inductor L, an eddy current will not be generated in the substrate 61. Moreover, when viewed from above, the inductor L is arranged at a position that does not overlap with the capacitor C. Therefore, even if an alternating magnetic field is generated, it is not easy to generate eddy currents in the lower electrode 11 and the upper electrode 21 of the capacitor C. The Q value of the inductor L will not be reduced due to the eddy current, so the Q value of the inductor L can be improved.

[0076] In addition, in the first embodiment, the second insulating films 71, 72, 73 ( Figure 4 ) uses a material with a Young's modulus smaller than that of the conductor patterns 31, 41, 51, etc. Therefore, when the temperature of the integrated passive component rises and the second insulating films 71, 72, 73 and the conductor patterns 31, 41, 51 thermally expand, the second insulating films 71, 72, 73 absorb the thermal deformation. As a result, the thermal deformation generated in the conductor patterns 31, 41, 51 can be reduced.

[0077] Generally, if the conductor patterns 31, 41, 51 are thickened, thermal deformation is likely to occur in the conductor patterns 31, 41, 51 and the insulating films around them. In the first embodiment, the second insulating films 71, 72, 73 absorb thermal deformation, so that even if the conductor patterns 31, 41, 51 are thickened, various problems caused by thermal deformation are unlikely to occur. By thickening the conductor patterns 31, 41, 51 constituting the inductor L, the resistance component of the inductor L can be reduced, and a high Q value can be achieved.

[0078] The second insulating films 71, 72, 73 use resin, so that even if there are bumps on the base surfaces of the second insulating films 71, 72, 73, the upper surfaces of the second insulating films 71, 72, 73 can be flattened. That is, the flatness of the upper surface of each of the second insulating films 71, 72, 73 can be made smaller than the flatness of the lower surface. Here, "flatness" refers to the size of the deviation from the correct plane geometrically. For example, the surface of the object can be defined as the interval between two planes when clamped by two parallel planes. The upper surfaces of the second insulating films 71, 72, 73 become flat, so that the conductor patterns 41, 51, input terminals In, etc. formed on the second insulating films 71, 72, 73 can be miniaturized and the cross-sectional shape can be highly vertical and horizontal.

[0079] Since thermal deformation is less likely to occur in the conductor patterns 31, 41, 51 constituting the inductor L, and the upper surfaces of the second insulating films 71, 72, 73 can be made flat, the conductor patterns constituting the inductor L can be further multilayered. If the inductor L is multilayered, a desired inductance can be obtained by adopting only a spiral structure instead of a spiral structure. By adopting only a spiral structure, the size of the inductor L in a plan view can be reduced. Thus, miniaturization of the integrated passive component can be achieved.

[0080] Next, a modification of the first embodiment will be described.

[0081] In the first embodiment, the first insulating film 63 is formed of an insulating material mainly containing the same constituent elements as the substrate 61, but may be formed of other insulating materials. In order to ensure sufficient moisture resistance of the capacitor C, the first insulating film 63 is preferably formed of an inorganic insulating material. For example, the first insulating film 63 may also be formed of SiO or the like. In addition, in order to suppress the generation of cracks, it is preferred to select the material of the first insulating film 63 so that the difference in linear expansion coefficient between the first insulating film 63 and the substrate 61 is smaller than the difference in linear expansion coefficient between the substrate 61 and the second insulating films 71, 72, 73.

[0082] In the first embodiment, the substrate 61 and the dielectric film 62 are made of silicon nitride, but the substrate 61 and the dielectric film 62 may also be made of other inorganic insulating materials, such as aluminum oxide.

[0083] In the first embodiment, the first insulating film 63 ( Figure 4 ), the conductor patterns 31 and 32 of the first wiring layer are directly arranged on the first insulating film 63, but a resin insulating film may be arranged on the first insulating film 63, and the conductor patterns 31 and 32 of the first wiring layer may be arranged on the insulating film. Thus, the base surface of the first wiring layer can be flattened.

[0084] An inorganic insulating film may be provided, and a first-layer second insulating film 71 may be provided on the inorganic insulating film to cover the conductor patterns 31 and 32 of the first wiring layer and the first insulating film 63 ( Figure 4 ). As the inorganic insulating film, the same material as the first insulating film 63 may be used. By configuring the inorganic insulating film on the first wiring layer, moisture is less likely to enter the capacitor C, and thus the environmental resistance of the capacitor C can be further improved.

[0085] In the first embodiment, one end of the inductor L is connected to one electrode of the capacitor C, but both ends of the inductor L may be connected to the two electrodes of the capacitor C. In this case, an LC parallel resonant circuit can be obtained.

[0086] [Second embodiment]

[0087] Next, refer to Figure 8A to Figure 11 The integrated passive components according to the second embodiment are described in the accompanying drawings. Figure 1A The description of the common structures of the integrated passive components according to the first embodiment shown in the drawings of FIG. 7 is omitted.

[0088] Fig. 8A is a diagram showing the positional relationship of the components of the integrated passive component according to the second embodiment in a plan view, Figure 8B : is an equivalent circuit diagram of the integrated passive component based on the second embodiment. The integrated passive component based on the first embodiment is a low-pass filter including one capacitor C and one inductor L. In contrast, the integrated passive component based on the second embodiment is a band-pass filter including six capacitors and five inductors.

[0089] Between the input terminal In and the output terminal Out, a capacitor C1, an inductor L1, and a capacitor C2 are connected in series in order from the input terminal In side. A series circuit of a capacitor C3 and an inductor L2, and a series circuit of a capacitor C4 and an inductor L3 are connected in parallel between the input terminal In and the ground terminal GND. A series circuit of a capacitor C5 and an inductor L4, and a series circuit of a capacitor C6 and an inductor L5 are connected in parallel between the output terminal Out and the ground terminal GND.

[0090] These passive elements are formed by conductor patterns included in the lower electrode layer, the upper electrode layer, the first wiring layer, the second wiring layer, and the third wiring layer, similarly to the first embodiment. As external connection terminals, an input terminal In, an output terminal Out, and two ground terminals GND are provided.

[0091] Reference Figures 9A to 11 The structure of the conductor patterns of two conductor layers adjacent to each other is described in the accompanying drawings. Figures 9A to 11 In the drawings, the conductor pattern of the wiring layer on the relatively lower side is indicated by a dotted line.

[0092] Fig.9A It is a diagram showing the positional relationship between the conductor pattern of the lower electrode layer and the conductor pattern of the upper electrode layer in a plan view. Fig. 9B It is a diagram showing the positional relationship between the conductor pattern of the upper electrode layer and the conductor pattern of the first wiring layer in a plan view. Fig. 10A The diagram shows the positional relationship between the conductor pattern of the first wiring layer and the conductor pattern of the second wiring layer in a plan view. Fig. 10B It is a diagram showing the positional relationship between the conductor pattern of the second wiring layer and the conductor pattern of the third wiring layer in a plan view. Fig.11 It is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and the external connection terminal in a plan view.

[0093] By passing through the lower electrode 101 ( Fig.9A ) and the upper electrodes 111A, 111B of the upper electrode layer ( Fig.9A ) to form capacitor C1. Specifically, a capacitor composed of upper electrode 111A and lower electrode 101 and a capacitor composed of lower electrode 101 and upper electrode 111B are connected in series to form capacitor C1. Similarly, through lower electrode 102 ( Fig.9A ) and upper electrodes 112A, 112B ( Fig.9A ) forms a capacitor C2. By the lower electrode 104 ( Fig.9A ) and upper electrodes 114A, 114B ( Fig.9A ) forms a capacitor C4. By the lower electrode 106 ( Fig.9A ) and upper electrodes 116A, 116B ( Fig.9A ) forms capacitor C6.

[0094] The capacitor C3 is formed by the lower electrode 103 of the lower electrode layer and the upper electrode 113A of the upper electrode layer. The conductor pattern 113B of the upper electrode layer is connected to the lower electrode 103 through a via hole. Similarly, the capacitor C5 is formed by the lower electrode 105 and the upper electrode 115A. The conductor pattern 115B is connected to the lower electrode 105 through a via hole. Hereinafter, the description of the via hole connecting the upper and lower conductor patterns is omitted.

[0095] One upper electrode 111A of the capacitor C1 ( Fig.9A ) through the conductor pattern 128A ( Fig. 9B )、Conductor pattern 136B( Fig. 10A )、Conductor pattern 146A( Fig. 10B ) and input terminal In( Fig.11 ) is connected. The other upper electrode 111B ( Fig.9A ) and the conductor pattern 128B ( Fig. 9B )、Conductor pattern 136D( Fig. 10A )、The conductor pattern 141 for the inductor L1 ( Fig. 10B )、Conductor pattern 131( Fig. 10A )、Conductor pattern 121( Fig. 9B ) is connected. The conductor pattern 121 ( Fig. 9B ) and the upper electrode 112A ( Fig.9A ) is connected. The other upper electrode 112B of the capacitor C2 ( Fig.9A ) through the conductor pattern 126 ( Fig. 9B )、Conductor pattern 136F( Fig. 10A )、Conductor pattern 146C( Fig. 10B ) and output terminal Out( Fig.11 )connect.

[0096] The upper electrode 113A of the capacitor C3 ( Fig.9A ) through the conductor pattern 123 ( Fig. 9B )、Conductor pattern 136A( Fig. 10A ), and the conductor pattern 146A ( Fig. 10B ) and input terminal In( Fig.11 ) is connected. The lower electrode 103 ( Fig.9A ) through the conductor pattern 113B ( Fig.9A ) and through the conductor pattern 122 for the inductor L2 ( Fig. 9B )、Conductor pattern 132( Fig. 10A )、Conductor pattern 142( Fig. 10B ) and the conductor pattern 146D ( Fig. 10B ) is connected. Conductor pattern 146D ( Fig. 10B) and the ground terminal GND( Fig.11 )connect.

[0097] One upper electrode 114A ( Fig.9A ) through the conductor pattern 125A ( Fig. 9B )、Conductor pattern 136C( Fig. 10A )、Conductor pattern 146A( Fig. 10B ) and input terminal In( Fig.11 ) is connected. The other upper electrode 114B ( Fig.9A ) through the conductor pattern 125B ( Fig. 9B )、The conductor pattern 133 for the inductor L3 ( Fig. 10A )、Conductor pattern 143( Fig. 10B )、Conductor pattern 146B( Fig. 10B ) and the ground terminal GND( Fig.11 )connect.

[0098] The upper electrode 115A of the capacitor C5 ( Fig.9A ) through the conductor pattern 129 ( Fig. 9B )、Conductor pattern 136G( Fig. 10A )、Conductor pattern 146C( Fig. 10B ) and output terminal Out( Fig.11 ) is connected. The lower electrode 105 ( Fig.9A ) through the conductor pattern 115B ( Fig.9A )、The conductor pattern 124 for the inductor L4 ( Fig. 9B )、Conductor pattern 134( Fig. 10A )、Conductor pattern 144( Fig. 10B )、Conductor pattern 146B( Fig. 10B ) and the ground terminal GND( Fig.11 )connect.

[0099] One of the upper electrodes 116B of the capacitor C6 ( Fig.9A ) through the conductor pattern 127B ( Fig. 9B )、Conductor pattern 136E( Fig. 10A )、Conductor pattern 146C( Fig. 10B ) and output terminal Out( Fig.11 ) is connected. The other upper electrode 116A of the capacitor C6 ( Fig.9A ) through the conductor pattern 127A ( Fig. 9B )、The conductor pattern 135 for the inductor L5 ( Fig. 10A )、Conductor pattern 145( Fig. 10B )、Conductor pattern 146D( Fig. 10B ) and the ground terminal GND( Fig.11 )connect.

[0100] The stacked structure of the integrated passive components of the second embodiment is similar to that of the first embodiment. Figure 4 The laminated structure of the substrate 61 to the third-layer second insulating film 73 is the same. External connection terminals such as the input terminal In are arranged on the third-layer second insulating film 73 .

[0101] Next, the excellent effects of the second embodiment are described. The integrated passive component based on the second embodiment has the same advantages as the integrated passive component based on the first embodiment ( Figure 4 ) has the same stacked structure as the first embodiment, so cracks caused by thermal stress are not easily generated. As a result, the reduction in moisture resistance caused by cracks can be suppressed, and the quality of the integrated passive component can be improved.

[0102] In addition, as in the second embodiment, by providing a plurality of capacitors and a plurality of inductors on one substrate 61, the degree of freedom in circuit design of the passive circuit is improved.

[0103] [Third embodiment]

[0104] Next, refer to Fig.12 The integrated passive component according to the third embodiment is described below. Figure 1A The description of the common structures of the integrated passive components according to the first embodiment shown in the drawings of FIG. 7 is omitted.

[0105] Fig.12 is a cross-sectional view of a capacitor portion of an integrated passive component according to the third embodiment. Fig.12 In the figure, description of the structure above the second insulating film 71 of the first layer is omitted.

[0106] In the first embodiment, the capacitor C is composed of a lower electrode 11 and an upper electrode 21 ( Figure 4 ) are composed of two layers of electrodes. In contrast, in the third embodiment, the capacitor C is composed of four layers of electrodes. The first electrode 11A, the second electrode 21A, the third electrode 11B, and the fourth electrode 21B are stacked in order from the substrate 61 side. A first layer of dielectric film 62A is arranged between the first electrode 11A and the second electrode 21A, a second layer of dielectric film 62B is arranged between the second electrode 21A and the third electrode 11B, and a third layer of dielectric film 62C is arranged between the third electrode 11B and the fourth electrode 21B. As in the first embodiment, the first insulating film 63 covers the capacitor C.

[0107] The dielectric films 62A, 62B, and 62C are formed of an insulating material mainly containing the same constituent elements as those of the substrate 61 .

[0108] The first electrode 11A and the third electrode 11B are connected via a conductor pattern 22A arranged in the same layer as the second electrode 21A. The second electrode 21A and the fourth electrode 21B are connected via a conductor pattern 23 arranged in the same layer as the third electrode 11B. The third electrode 11B is connected to a conductor pattern 31 constituting a part of the inductor via a conductor pattern 22B arranged in the same layer as the fourth electrode 21B. The fourth electrode 21B is connected to a conductor pattern 32 arranged on the first insulating film 63.

[0109] Next, the excellent effects of the third embodiment will be described.

[0110] In the third embodiment, the dielectric films 62A, 62B, and 62C are formed of an insulating material mainly containing the same constituent elements as the substrate 61, so that it is possible to suppress the thermal stress caused by the difference in linear expansion coefficients in these dielectric films 62A, 62B, and 62C. If the electrodes of the capacitor C are multilayered, cracks caused by thermal stress are likely to occur, but in the third embodiment, the thermal stress is reduced, so even if the electrodes are multilayered, the excellent effect of suppressing the occurrence of cracks can be maintained.

[0111] By multi-layering the electrodes of the capacitor C, the area occupied by the capacitor C in a plan view can be reduced under the condition of the same capacitance. This enables miniaturization of the integrated passive components.

[0112] Next, a modification of the third embodiment will be described.

[0113] In the third embodiment, the capacitor C is formed by four layers of electrodes, but it may be formed by three layers, or five or more layers of electrodes.

[0114] [Fourth embodiment]

[0115] Next, refer to Fig.13 The integrated passive component according to the fourth embodiment is described below. Figure 1A The description of the common structures of the integrated passive components according to the first embodiment shown in the drawings of FIG. 7 is omitted.

[0116] Fig.13 1 is a cross-sectional view of an integrated passive component according to the fourth embodiment. In the first embodiment, the lower electrode 11 is directly arranged on the substrate 61. In contrast, in the fourth embodiment, a base layer 65 is arranged on the upper surface of the substrate 61, and the lower electrode 11 is arranged on the base layer 65. In addition, a dielectric film 62 is also arranged on the base layer 65.

[0117] The base layer 65 is formed of an insulating material mainly containing the same constituent elements as the substrate 61, for example, the same insulating material as the dielectric film 62. The base layer 65 is thinner than the substrate 61. The base layer 65 can be formed on the substrate 61 by, for example, a plasma CVD method.

[0118] Next, the excellent effects of the fourth embodiment will be described.

[0119] The surface roughness of the base layer 65 formed by a thin film forming technique such as plasma CVD is smaller than the surface roughness of the upper surface of the ceramic substrate 61. As an index of the magnitude relationship of the surface roughness, for example, the arithmetic mean roughness, the root mean square roughness, etc. can be used.

[0120] Next, the excellent effects of the fourth embodiment will be described.

[0121] In the fourth embodiment, the surface roughness of the base surface (upper surface of the base layer 65) forming the lower electrode 11 is smaller than the surface roughness of the base surface (upper surface of the substrate 61) forming the lower electrode 11 of the first embodiment. Therefore, in the case of forming the conductor pattern of the wiring layer provided with the lower electrode 11 by the photolithography method, the conductor pattern can be miniaturized. Thus, the miniaturization of the integrated passive component can be achieved.

[0122] In addition, the base layer 65 is formed of an insulating material mainly containing the same constituent elements as the substrate 61, so the difference between the linear expansion coefficient of the base layer 65 and the linear expansion coefficient of the substrate 61 is small. Therefore, the excellent effect of the first embodiment such as being able to suppress the occurrence of cracks caused by thermal stress is not weakened by the configuration of the base layer 65.

[0123] [Fifth embodiment]

[0124] Next, refer to Fig.14A , Fig. 14B ,as well as Fig. 14C The integrated passive component according to the fifth embodiment is described below. Figure 1A The description of the common structures of the integrated passive components according to the first embodiment shown in the drawings of FIG. 7 is omitted.

[0125] Fig.14A is a cross-sectional view of an integrated passive component according to a fifth embodiment. Fig. 14B as well as Fig. 14C 1 and 12 are cross-sectional views of the lower electrode 11 and the conductor pattern 41, respectively. In the fifth embodiment, a lower conductor layer 11L ( Fig. 14B ), an upper conductor layer 11U is arranged on the upper surface ( Fig. 14B). Similarly, the lower conductor layer and the upper conductor layer are respectively arranged on the upper surface and the lower surface of the upper electrode 21 and the conductor pattern 22. In addition, the lower conductor layer is also arranged on the side surface of the via hole.

[0126] A lower conductor layer 41L and an upper conductor layer 41U are respectively arranged on the upper surface and the lower surface of the conductor pattern 41 of the first wiring layer. Fig. 14C ). Similarly, the lower conductor layer and the upper conductor layer are also respectively arranged on the lower surface and the upper surface of the other conductor patterns 42 of the second wiring layer, the first wiring layer and the plurality of conductor patterns of the third wiring layer. In addition, the lower conductor layer is arranged on the lower surface of the external connection terminal such as the input terminal In.

[0127] exist Fig.14A In the figure, these lower conductor layers and upper conductor layers are indicated by relatively thick solid lines. The lower conductor layers 11L, 41L and the upper conductor layers 11U, 41U are formed of Ti, Ni, an alloy containing Ti, or an alloy containing Ni. As an alloy containing Ti, for example, TiW is listed. In the metal laminated film 203 ( Figure 6B ) when Ti is used, a seed layer composed of Ti may be provided as a lower conductor layer.

[0128] Next, the excellent effects of the fifth embodiment will be described.

[0129] By configuring the lower conductor layer 11L ( Fig. 14B ), the adhesion between the substrate 61 and the lower electrode 11 can be improved. By configuring the upper conductor layer 11U ( Fig. 14B ), the adhesion between the lower electrode 11 and the dielectric film 62 can be improved. By configuring the lower conductor layer 41L ( Fig. 14C ), the adhesion between the conductor pattern 41 and the second insulating film 71 of the first layer can be improved. By configuring the upper conductor layer 41U ( Fig. 14C ), the adhesion between the conductor pattern 41 and the second insulating film 72 of the second layer can be improved. Similarly, for other conductor patterns, the adhesion with the insulating films, dielectric films, etc. above and below them can also be improved.

[0130] By improving the adhesion between the conductor pattern and the insulating film, it is possible to provide an integrated passive component of higher quality.

[0131] Next, a modification of the fifth embodiment will be described.

[0132] In order to improve the adhesion between the conductor pattern made of Cu and the insulating film on the conductor pattern, the copper surface may be roughened (CZ treatment).

[0133] The above-mentioned embodiments are illustrative, and it is of course possible to partially replace or combine the structures shown in different embodiments. The same effects produced by the same structures in multiple embodiments are not mentioned in sequence in each embodiment. In addition, the present invention is not limited to the above-mentioned embodiments. For example, it is obvious to those skilled in the art that various changes, improvements, combinations, etc. can be made.

Claims

1. An integrated passive component, characterized in that: have: Insulating substrate; A capacitor is disposed on the substrate; and an inductor, disposed on the substrate, comprising a conductor pattern at least one end of which is connected to the capacitor, The capacitor includes a dielectric film and at least two electrodes facing each other with the dielectric film interposed therebetween, wherein the dielectric film mainly includes the same constituent elements as the substrate. The substrate and the dielectric film mainly contain silicon and nitrogen as constituent elements.

2. The integrated passive component according to claim 1, characterized in that The integrated passive component further includes a first insulating film covering the capacitor and mainly including the same constituent elements as the dielectric film, The inductor is arranged above the first insulating film.

3. The integrated passive component according to claim 1 or 2, characterized in that: The inductor has a spiral structure or a helical structure with a direction perpendicular to a surface of the substrate on which the capacitor is arranged as a central axis. The inductor is arranged at a position not overlapping with the capacitor in a plan view.

4. The integrated passive component according to claim 1 or 2, characterized in that: The capacitor includes at least three layers of stacked electrodes, and the dielectric film is disposed between the upper and lower electrodes.

5. The integrated passive component according to claim 1 or 2, characterized in that: The substrate is formed of ceramic, The integrated passive component further comprises an amorphous insulating base layer, the base layer being disposed on the substrate and mainly comprising the same constituent elements as the substrate. The capacitor is disposed on the base layer.

6. The integrated passive component according to claim 1 or 2, characterized in that: The plurality of electrodes of the capacitor are formed of Au, Al, or Cu.

7. The integrated passive component according to claim 6, characterized in that The capacitor further includes a conductor layer, which is arranged between each of the plurality of electrodes of the capacitor and the dielectric film and on the lower surface of the lowermost electrode of the capacitor and is composed of Ti, Ni, an alloy containing Ti, or an alloy containing Ni.

8. The integrated passive component according to claim 1 or 2, characterized in that: The integrated passive component further includes a plurality of second insulating films stacked on the substrate and the capacitor, The inductor includes conductor patterns disposed above and below at least one layer of the plurality of second insulating films.

9. The integrated passive component according to claim 8, characterized in that The Young's modulus of each of the plurality of second insulating films is 10 GPa or less.

10. The integrated passive component according to claim 8, characterized in that The plurality of second insulating films are formed of resin.

11. The integrated passive component according to claim 8, characterized in that The planarity of an upper surface of each of the plurality of second insulating films is smaller than the planarity of a lower surface.

12. The integrated passive component according to claim 8, characterized in that The conductor pattern constituting the inductor is formed of Cu or a metal material containing Cu as a main component.

13. The integrated passive component according to claim 12, characterized in that The inductor includes a conductor layer disposed at an interface between a conductor pattern constituting the inductor and each of the plurality of second insulating films, and made of Ti, Ni, an alloy containing Ti, or an alloy containing Ni.

14. The integrated passive component according to claim 8, characterized in that The thickness of the conductor pattern constituting the inductor is 5 times or more greater than the thickness of each of the plurality of electrodes of the capacitor.

Images