A power device structure and manufacturing method thereof

Abstract

The present invention provides a power device structure and a manufacturing method thereof, the method comprising the following steps: providing a substrate with a gate groove, forming a gate dielectric layer on the sidewall and bottom surface of the gate groove; forming a gate material sidewall in the gate groove; forming a sacrificial layer in the gate groove, the top surface of the sacrificial layer being lower than the upper surface of the substrate; forming an insulating layer above the sacrificial layer; forming at least one through hole in the insulating layer; removing the sacrificial layer; forming a sealing layer in the through hole; forming a gate material filling layer in the gate groove, the gate material filling layer being located above the insulating layer and connected to the gate material sidewall. The manufacturing method of the power device structure of the present invention hollows out the lower part of the gate material so that the lower part of the trench gate structure has a cavity. Since the cavity has a very low dielectric constant, the capacitance between the gate material and the drain of the power device structure can be significantly reduced, thereby reducing the power consumption of the power device, which is beneficial to improving the power utilization rate and saving energy.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to a power device structure and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices are the core components of power electronics technology. Power devices can be divided into two categories: power IC (integrated circuit) devices and power discrete devices. Power discrete devices include power MOSFET (metal-oxide semiconductor field effect transistor), high-power transistors and IGBT (insulated gate bipolar transistor) devices. Early power devices were all produced based on planar technology, but with the development of semiconductor technology, small size, high power and high performance have become the main development trends. Taking planar process MOSFET devices as an example, due to the limitation of the parasitic resistance of the JFET (junction field effect transistor) in the body, the area reduction of a single primitive cell is limited, which makes it difficult to increase the density of primitive cells and it is difficult to further reduce the on-resistance (RDSON) of the planar process MOSFET. Since the trench process changes the channel from horizontal to vertical, it eliminates the influence of the parasitic JFET resistance of the planar structure and greatly reduces the cell size. On this basis, the cell density can be increased and the total width of the channel per unit area of ​​the chip can be increased. The channel width-to-length ratio of the device on a unit silicon wafer can be increased, thereby increasing the current, reducing the on-resistance, and optimizing related parameters, achieving the goal of smaller die with greater power and high performance. Therefore, the trench process is increasingly used in new power devices.

[0003] Trench structure power devices use a gate oxide layer grown on the sidewall of the trench and filled with polysilicon to form a gate. This trench gate structure greatly improves the utilization efficiency of the plane area of ​​the power device, allowing a larger device unit channel width and current density per unit area, thereby enabling the device to obtain a greater current conduction capability. However, current power devices using trench gate structures still have gate-drain capacitance C gd The higher the problem, the higher the power consumption of vertical power devices. In the context of increasingly prominent energy and environmental issues, it is not conducive to improving power utilization, saving energy and alleviating the energy crisis. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a power device structure and a manufacturing method thereof, so as to solve the problem of the gate-drain capacitance C of the trench power device in the prior art. gd The problem of higher parasitic resistance.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a power device structure, comprising the following steps:

[0006] Providing a substrate with a gate trench, and forming a gate dielectric layer on the sidewall and bottom surface of the gate trench;

[0007] Forming a gate material sidewall in the gate trench, wherein the gate material sidewall covers a surface of a portion of the gate dielectric layer located on a sidewall of the gate trench;

[0008] forming a sacrificial layer in the gate trench, wherein a top surface of the sacrificial layer is lower than an upper surface of the substrate;

[0009] forming an isolation layer in the gate trench, wherein the isolation layer is located above the sacrificial layer, and a top surface of the isolation layer is lower than an upper surface of the substrate;

[0010] forming at least one through hole in the insulating layer, wherein the through hole passes through the insulating layer from top to bottom;

[0011] removing the sacrificial layer;

[0012] forming a sealing layer in the through hole to seal the through hole;

[0013] A gate material filling layer is formed in the gate trench, wherein the gate material filling layer is located above the isolation layer and connected to the gate material sidewall.

[0014] Optionally, the material of the sacrificial layer includes at least one of photoresist and amorphous carbon.

[0015] Optionally, the sacrificial layer is removed by providing oxygen so that the oxygen reacts with the sacrificial layer through the through hole.

[0016] Optionally, after most of the sacrificial layer is removed by providing oxygen, the remaining sacrificial layer is removed by wet cleaning.

[0017] Optionally, after removing the sacrificial layer and before forming the sealing layer, a step of removing water vapor is also included.

[0018] Optionally, after forming the sealing layer and before forming the gate material filling layer, a step of wet cleaning the surface of the gate material sidewall is also included.

[0019] Optionally, the thickness of the sacrificial layer accounts for 20-60% of the depth of the gate trench.

[0020] Optionally, the thickness of the isolation layer accounts for 5-15% of the depth of the gate trench, and the aspect ratio of the through hole is greater than 3:1.

[0021] Optionally, the bottom surface of the sealing layer is higher than the bottom surface of the insulating layer.

[0022] Optionally, the material of the gate material sidewall and the gate material filling layer includes polysilicon, the material of the isolation layer includes tetraethyl orthosilicate, and the material of the sealing layer includes silicon oxide.

[0023] The present invention also provides a power device structure, comprising a substrate and a trench gate structure located in the substrate, wherein the trench gate structure comprises:

[0024] A gate trench starts from the upper surface of the substrate and extends toward the lower surface of the substrate but does not penetrate the substrate;

[0025] A gate dielectric layer, located on the sidewalls and bottom surface of the gate trench;

[0026] A gate material sidewall, located in the gate trench and covering the surface of a portion of the gate dielectric layer located on the sidewall of the gate trench;

[0027] an isolation layer, located in the gate trench, wherein the sidewall of the isolation layer is connected to the gate material sidewall, wherein a portion of the gate dielectric layer located at the bottom of the gate trench, the gate material sidewall and the isolation layer together form a cavity;

[0028] The gate material filling layer is located in the gate trench and above the isolation layer, and the gate material filling layer is connected to the gate material sidewall.

[0029] Optionally, the height of the cavity accounts for 20-60% of the depth of the gate trench.

[0030] Optionally, the material of the gate material sidewall and the gate material filling layer includes polysilicon, the material of the isolation layer includes tetraethyl orthosilicate, and the material of the sealing layer includes silicon oxide.

[0031] As described above, the manufacturing method of the power device structure of the present invention hollows out the lower part of the gate material so that the lower part of the trench gate structure has a cavity. Since the cavity has a very low dielectric constant, the capacitance between the gate material and the drain of the power device structure can be significantly reduced, thereby reducing the power consumption of the power device, which is beneficial to improving the utilization rate of electric energy and saving energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram showing the method for manufacturing the power device structure of the present invention for forming a gate dielectric layer on the sidewall and bottom surface of the gate trench.

[0033] Figure 2 It is a schematic diagram showing the method for manufacturing a power device structure of the present invention for forming a conformal layer of gate material on the surface of the gate dielectric layer.

[0034] Figure 3It is a schematic diagram showing the method for manufacturing the power device structure of the present invention, wherein the portion of the gate material conformal layer located at the bottom of the gate trench is removed to obtain the gate material sidewall.

[0035] Figure 4 It is a schematic diagram showing the method for manufacturing a power device structure of the present invention, wherein a sacrificial layer is formed in the gate trench.

[0036] Figure 5 It is a schematic diagram showing the method for manufacturing the power device structure of the present invention to form an isolation layer in the gate trench.

[0037] Figure 6 It is a schematic diagram showing the method for manufacturing a power device structure of the present invention, wherein at least one through hole is formed in the isolation layer.

[0038] Figure 7 It is a schematic diagram showing the removal of the sacrificial layer in the method for manufacturing the power device structure of the present invention.

[0039] Figure 8 Display as Figure 7 Top view of the structure shown.

[0040] Fig. 9 It is a schematic diagram showing the method for manufacturing a power device structure of the present invention, wherein a sealing layer is formed in the through hole to seal the through hole.

[0041] Fig.10 It is a schematic diagram showing the method for manufacturing the power device structure of the present invention to form a gate material filling layer in the gate trench.

[0042] Fig.11 It is a schematic diagram showing the method for manufacturing the power device structure of the present invention, in which a body region is formed on the upper part of the drift layer.

[0043] Fig.12 It is a schematic diagram showing the method for manufacturing the power device structure of the present invention, in which a source is formed on the upper portion of the body region.

[0044] Component number description

[0045] 1 Drain layer

[0046] 2 Drift layer

[0047] 3. Gate dielectric layer

[0048] 4 Gate trench

[0049] 5. Gate material conformal layer

[0050] 6. Gate material sidewall

[0051] 7 Sacrificial Layer

[0052] 8 Insulation layer

[0053] 9 Through Holes

[0054] 10 Sealing layer

[0055] 11 Cavity

[0056] 12. Gate material filling layer

[0057] 13 Body Area

[0058] 14 Source DETAILED DESCRIPTION

[0059] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0061] Embodiment 1

[0062] This embodiment provides a method for manufacturing a power device structure, comprising the following steps:

[0063] like Figure 1 As shown, a substrate with a gate trench 4 is provided, and a gate dielectric layer 3 is formed on the sidewall and bottom surface of the gate trench 4 .

[0064] As an example, the substrate includes a drain layer 1 and a drift layer 2 from bottom to top, and the gate trench 4 is located in the drift layer 2. The drain layer 1 can be heavily doped with the first conductivity type, and the drift layer can be lightly doped with the first conductivity type. In this embodiment, the first conductivity type is N-type, and correspondingly, the second conductivity type to be described later is P-type. Of course, in other embodiments, the first conductivity type can also be P-type, and correspondingly, the second conductivity type is N-type.

[0065] In addition, in other embodiments, the doping layer in the substrate may also be adjusted according to specific power device requirements, and the protection scope of the present invention should not be excessively limited here.

[0066] As an example, a furnace tube device or other devices are used to deposit a silicon oxide layer as the gate dielectric layer 3 by thermal oxidation or chemical vapor deposition.

[0067] like Figure 2 and Figure 3 As shown, a gate material sidewall 6 is formed in the gate trench 4 , and the gate material sidewall 6 covers the surface of the gate dielectric layer 3 located on the sidewall of the gate trench 4 .

[0068] As an example, a furnace tube device or other equipment is first used to form a gate material conformal layer 5 on the surface of the gate dielectric layer 3 by chemical vapor deposition, and then the portion of the gate material conformal layer 5 located at the bottom of the gate trench 4 is removed by dry etching, and the remaining gate material conformal layer serves as the gate material side wall 6.

[0069] As an example, the material of the gate material spacer 6 includes polysilicon.

[0070] like Figure 4 As shown, a sacrificial layer 7 is formed in the gate trench 4 , and the top surface of the sacrificial layer 7 is lower than the upper surface of the substrate.

[0071] As an example, the material of the sacrificial layer 7 includes but is not limited to photoresist or amorphous carbon. In this embodiment, photoresist is preferably used, which can be filled into the gate trench 4 by spin coating. When amorphous carbon is used as the sacrificial layer, it can be obtained by chemical vapor deposition.

[0072] As an example, the thickness of the sacrificial layer 7 accounts for 20-60% of the depth of the gate trench, and can be adjusted according to the performance requirements of the device.

[0073] like Figure 5 As shown, an isolation layer 8 is formed in the gate trench 4 , the isolation layer 8 is located above the sacrificial layer 7 , and the top surface of the isolation layer 8 is lower than the upper surface of the substrate.

[0074] As an example, the material of the isolation layer 8 includes tetraethyl orthosilicate (TEOS). In this embodiment, the isolation layer 8 is formed by flowable chemical vapor deposition (FCVD). The thickness of the isolation layer 8 accounts for 5-15% of the depth of the gate trench 4.

[0075] like Figure 6 As shown, at least one through hole 9 is formed in the insulating layer 8, and the through hole 9 passes through the insulating layer 8 from top to bottom.

[0076] As an example, the through holes 9 are formed by photolithography and etching, and the number of the through holes 9 is 1 to 5. In this embodiment, two through holes are taken as an example.

[0077] It should be noted that the through hole 9 needs to meet a certain aspect ratio so that it can be quickly filled later. In this embodiment, the aspect ratio of the through hole 9 is preferably greater than 3:1.

[0078] like Figure 7 and Figure 8 As shown, the sacrificial layer 7 is removed, wherein, Figure 8 Display as Figure 7 Top view of the structure shown.

[0079] As an example, the sacrificial layer 7 is removed by providing oxygen gas so that the oxygen gas reacts with the sacrificial layer 7 via the through hole 9 .

[0080] It should be pointed out that since some sacrificial layer will inevitably remain, in this embodiment, after most of the sacrificial layer 7 is removed by providing oxygen, wet cleaning is used to further remove the remaining sacrificial layer 7. The wet cleaning solution can be an acidic solution, which can be configured according to the specific sacrificial layer material.

[0081] As an example, before the next step is performed, water vapor is further removed by hydrogen treatment or helium treatment.

[0082] like Fig. 9 As shown, a sealing layer 10 is formed in the through hole 9 to seal the through hole 9 .

[0083] As an example, the material of the sealing layer 10 includes silicon oxide, which can be deposited by chemical vapor deposition. In this embodiment, SiH4 with relatively low filling capacity is used as a reaction gas to form the sealing layer 10, and the sealing layer 10 is formed at the upper part of the through hole 9, and the bottom surface of the sealing layer 10 is higher than the bottom surface of the insulating layer 8. In other words, the through hole 9 is quickly sealed.

[0084] At this time, the portion of the gate dielectric layer 3 located at the bottom of the gate trench 4, the gate material sidewall 6, the isolation layer 8 and the sealing layer 10 together form a cavity 11. Since the through hole 9 is quickly sealed, very little reaction gas and its products enter the cavity 11. The cavity 11 has a very low dielectric constant, similar to the dielectric constant of air.

[0085] like Fig.10 As shown, a gate material filling layer 12 is formed in the gate trench 4 . The gate material filling layer 12 is located above the isolation layer 8 and connected to the gate material sidewall 6 .

[0086] As an example, before forming the gate material filling layer, the surface of the gate material sidewall is cleaned by a wet method to remove silicon oxide particles or impurities on the surface of the gate material sidewall.

[0087] As an example, the gate material filling layer 12 is prepared by chemical vapor deposition using furnace tube equipment or other equipment, and the material of the gate material filling layer includes polysilicon.

[0088] At this point, a trench gate structure is manufactured, and the lower part of the trench gate structure has the cavity 11, which can significantly reduce the gate-drain capacitance.

[0089] like Fig.11 As shown, a body region 13 may be further formed on the upper portion of the drift layer 2, and the body region 13 may be doped with the second conductivity type. Specifically, the body region 13 may be obtained by implanting the second conductivity type ions and performing diffusion.

[0090] like Fig.12 As shown, a source 14 may be further formed on the upper portion of the body region 13 by ion implantation, and the source 14 is heavily doped with the first conductivity type.

[0091] Subsequently, further steps such as forming an oxide layer, etching contact holes, forming a contact area at the bottom of the contact holes, forming a gate metal layer and a source metal layer may be performed, which are well known to those skilled in the art and will not be described in detail here.

[0092] At this point, a vertical power device structure is manufactured. The manufacturing method of the power device structure of this embodiment hollows out the lower part of the gate material so that the lower part of the trench gate structure has a cavity. Since the cavity has a very low dielectric constant, the capacitance between the gate material and the drain of the power device structure can be significantly reduced, thereby reducing the power consumption of the power device, which is beneficial to improving the utilization rate of electric energy and saving energy.

[0093] Embodiment 2

[0094] This embodiment provides a power device structure. Fig.12, showing a cross-sectional view of the power device structure, including a substrate and a trench gate structure located in the substrate, the trench gate structure including a gate trench, a gate dielectric layer 3, a gate material sidewall 6, an isolation layer 8 and a gate material filling layer 12, wherein the gate trench starts from the upper surface of the substrate and extends toward the lower surface of the substrate, but does not penetrate the substrate; the gate dielectric layer 3 is located on the sidewall and bottom of the gate trench; the gate material sidewall 6 is located in the gate trench and covers the surface of the portion of the gate dielectric layer 3 located on the sidewall of the gate trench; the isolation layer 8 is located in the gate trench, the sidewall of the isolation layer 8 is connected to the gate material sidewall 6, the portion of the gate dielectric layer 3 located at the bottom of the gate trench, the gate material sidewall 6 and the isolation layer 8 together form a cavity 11; the gate material filling layer 12 is located in the gate trench and above the isolation layer 8, and the gate material filling layer 12 is connected to the gate material sidewall 6.

[0095] As an example, the substrate includes a drain layer 1 and a drift layer 2 in sequence, the gate trench 4 is located in the drift layer 2 , the drift layer 2 has a body region 13 on the top, and the body region 13 has a source 14 on the top.

[0096] As an example, the drain layer 1 may be heavily doped with the first conductivity type, the drift layer may be lightly doped with the first conductivity type, the body region 13 may be doped with the second conductivity type, and the source 14 may be heavily doped with the first conductivity type. In this embodiment, the first conductivity type is N-type, and correspondingly, the second conductivity type is P-type. Of course, in other embodiments, the second conductivity type may be P-type, and the second conductivity type may be N-type. The doping layer in the substrate may also be adjusted according to the specific power device requirements, and the protection scope of the present invention should not be excessively limited here.

[0097] As an example, the height of the cavity 11 accounts for 20-60% of the depth of the gate trench.

[0098] As an example, the material of the gate material sidewall 6 and the gate material filling layer 12 includes polysilicon, and the material of the isolation layer 8 includes tetraethyl orthosilicate.

[0099] As an example, a sealing layer 10 may be further provided in the insulating layer, and the material of the sealing layer 10 includes silicon oxide.

[0100] In the power device structure of this embodiment, the lower part of the trench gate structure has a cavity, which can significantly reduce the gate-drain capacitance, so that the power device has lower power consumption.

[0101] In summary, the manufacturing method of the power device structure of the present invention hollows out the lower part of the gate material, so that the lower part of the trench gate structure has a cavity. Since the cavity has a very low dielectric constant, the capacitance between the gate material and the drain of the power device structure can be significantly reduced, thereby reducing the power consumption of the power device, which is beneficial to improving the utilization rate of electric energy and saving energy. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a power device structure, characterized in that: The following steps are involved: Providing a substrate with a gate trench, and forming a gate dielectric layer on the sidewall and bottom surface of the gate trench; Forming a gate material sidewall in the gate trench, wherein the gate material sidewall covers a surface of a portion of the gate dielectric layer located on a sidewall of the gate trench; forming a sacrificial layer in the gate trench, wherein a top surface of the sacrificial layer is lower than an upper surface of the substrate; forming an isolation layer in the gate trench, wherein the isolation layer is located above the sacrificial layer, and a top surface of the isolation layer is lower than an upper surface of the substrate; forming at least one through hole in the insulating layer, wherein the through hole passes through the insulating layer from top to bottom; removing the sacrificial layer; Forming a sealing layer in the through hole to seal the through hole, wherein the portion of the gate dielectric layer located at the bottom of the gate trench, the gate material sidewall, the isolation layer and the sealing layer together form a cavity; A gate material filling layer is formed in the gate trench, the gate material filling layer is located above the isolation layer and connected to the gate material sidewall, and the material of the gate material sidewall and the gate material filling layer includes polysilicon.

2. The method for manufacturing a power device structure according to claim 1, characterized in that: The material of the sacrificial layer includes at least one of photoresist and amorphous carbon.

3. The method for manufacturing a power device structure according to claim 2, characterized in that: The sacrificial layer is removed by providing oxygen gas so that the oxygen gas reacts with the sacrificial layer through the through hole.

4. The method for manufacturing a power device structure according to claim 3, characterized in that: After most of the sacrificial layer is removed by supplying oxygen, the remaining sacrificial layer is removed by wet cleaning.

5. The method for manufacturing a power device structure according to claim 1, characterized in that: After removing the sacrificial layer and before forming the sealing layer, the method further includes a step of removing water vapor.

6. The method for manufacturing a power device structure according to claim 1, characterized in that: After forming the sealing layer and before forming the gate material filling layer, the method further includes a step of wet cleaning the surface of the gate material sidewall.

7. The method for manufacturing a power device structure according to claim 1, characterized in that: The thickness of the sacrificial layer accounts for 20-60% of the depth of the gate trench.

8. The method for manufacturing a power device structure according to claim 1, characterized in that: The thickness of the isolation layer accounts for 5-15% of the depth of the gate trench, and the aspect ratio of the through hole is greater than 3:

1.

9. The method for manufacturing a power device structure according to claim 1, characterized in that: The bottom surface of the sealing layer is higher than the bottom surface of the insulating layer.

10. The method for manufacturing a power device structure according to claim 1, characterized in that: The material of the insulating layer includes tetraethyl orthosilicate, and the material of the sealing layer includes silicon oxide.

11. A power device structure, comprising a substrate and a trench gate structure located in the substrate, characterized in that: The trench gate structure comprises: A gate trench starts from the upper surface of the substrate and extends toward the lower surface of the substrate but does not penetrate the substrate; A gate dielectric layer, located on the sidewalls and bottom surface of the gate trench; A gate material sidewall, located in the gate trench and covering the surface of a portion of the gate dielectric layer located on the sidewall of the gate trench; an isolation layer, located in the gate trench and having at least one through hole, an upper portion of the through hole being provided with a sealing layer, a side wall of the isolation layer being connected to the gate material side wall, wherein a portion of the gate dielectric layer located at the bottom of the gate trench, the gate material side wall, the isolation layer and the sealing layer together enclose a cavity; A gate material filling layer is located in the gate trench and above the isolation layer. The gate material filling layer is connected to the gate material sidewall. The gate material sidewall and the gate material filling layer are made of polysilicon.

12. The power device structure according to claim 11, characterized in that: The height of the cavity accounts for 20-60% of the depth of the gate trench.

13. The power device structure according to claim 11, characterized in that: The material of the insulating layer includes tetraethyl orthosilicate, and the material of the sealing layer includes silicon oxide.

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