III-nitride enhanced HEMT device and method for manufacturing the same

Abstract

The present invention discloses a III-nitride enhanced HEMT device and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; epitaxially growing a III-nitride heterojunction on the substrate, the III-nitride heterojunction comprising a channel layer and a barrier layer, a two-dimensional electron gas being formed in the channel layer; etching the barrier layer and part of the channel layer to form a source region and a drain region; forming a source and a drain in the source region and the drain region respectively; epitaxially growing a first passivation layer on the barrier layer and the source and the drain; etching the first passivation layer to form a source window and a drain window on the source and the drain respectively, and forming a gate window penetrating the first passivation layer between the source window and the drain window; performing an oxidation process on the III-nitride heterojunction below the gate window using an inductively coupled plasma system to form an insulating dielectric layer; and forming a gate in the gate window. The present invention can accurately control the growth rate and thickness of the insulating dielectric layer, and can achieve a low damage effect.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN)-based high electron mobility transistors (HMETs) can meet the needs of high-efficiency and high-voltage power electronic applications due to the wide bandgap (3.4eV), high electron mobility, and high breakdown electric field of GaN materials. Traditional AlGaN / GaN high electron mobility transistors have a depletion mode (D-mode) channel modulation mechanism because the AlGaN / GaN interface can spontaneously polarize to form a high concentration of carriers. However, from the perspective of safe operation and low power consumption of applications, enhancement mode (E-mode) power transistors are more popular among circuit designers. The use of enhancement mode power transistors can avoid the use of negative voltage power supplies to simplify the design of gate drive circuits.

[0003] At present, the mainstream technologies for making GaN enhancement devices include gate groove, fluorine ion implantation and p-type GaN gate. Among them: the gate groove technology requires the use of etching process, and the damage caused by the etching process will lead to increased gate leakage and uneven threshold voltage; the fluorine ion implantation technology will have the problem of poor stability of threshold voltage under high field and high temperature stress; the p-type GaN gate technology requires an additional layer of p-type GaN epitaxy, which is costly. The growth uniformity and magnesium (Mg) activation of p-type GaN are the difficulties of this technology, and it is necessary to etch and remove the p-type GaN outside the gate area. This process will also cause etching damage, resulting in poor transistor interface characteristics. At the same time, the p-type GaN gate has a low withstand voltage, usually less than +7V, which increases the difficulty of circuit design.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a group III nitride enhanced HEMT device and a method for manufacturing the same. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a group III nitride enhanced HEMT device and a method for manufacturing the same.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A method for manufacturing a group III nitride enhanced HEMT device, the manufacturing method comprising:

[0008] providing a substrate;

[0009] Epitaxially growing a III-nitride heterojunction on a substrate, wherein the III-nitride heterojunction includes a channel layer and a barrier layer, and a two-dimensional electron gas is formed in the channel layer;

[0010] Etching the barrier layer and part of the channel layer to form a source region and a drain region;

[0011] forming a source electrode and a drain electrode in the source region and the drain region, respectively;

[0012] epitaxially growing a first passivation layer over the barrier layer and the source and drain electrodes;

[0013] Etching the first passivation layer to form a source window and a drain window above the source and the drain respectively, and forming a gate window penetrating the first passivation layer between the source window and the drain window;

[0014] An inductively coupled plasma system is used to perform an oxidation process on the III-nitride heterojunction below the gate window to form an insulating dielectric layer;

[0015] A gate is formed in the gate window.

[0016] In one embodiment, a portion of the barrier layer below the gate window is oxidized to form an insulating dielectric layer, a lower surface of the insulating dielectric layer is located above the interface between the channel layer and the barrier layer, and a thickness of the barrier layer below the insulating dielectric layer is less than or equal to 10 nm; or,

[0017] The entire barrier layer below the gate window is oxidized to form an insulating dielectric layer, and the lower surface of the insulating dielectric layer is located at the interface between the channel layer and the barrier layer; or,

[0018] The entire barrier layer and a portion of the channel layer below the gate window are oxidized to form an insulating dielectric layer, and the lower surface of the insulating dielectric layer is located below the interface between the channel layer and the barrier layer.

[0019] In one embodiment, in the oxidation process, the oxidizing gas includes oxygen and / or nitrous oxide, the gas flow rate is 10-80 sccm, the chamber pressure is 8-20 mTorr, the RF power range is 5-100W, and the inductively coupled plasma power is 100-300W.

[0020] In one embodiment, the manufacturing method further comprises:

[0021] An alkaline solution and an acidic solution are used to remove a portion of the insulating dielectric layer. The alkaline solution includes one or more of sodium hydroxide, potassium hydroxide, ammonia water, and tetramethylammonium hydroxide solution. The acidic solution includes a hydrochloric acid solution.

[0022] In one embodiment, in the manufacturing method, before or after the step of “epitaxially growing a first passivation layer on the barrier layer and the source and drain electrodes”, the method further includes:

[0023] An ion implantation process or an etching process is used to isolate a passive region in the III-nitride heterojunction beside the source and / or drain to form an isolation region;

[0024] The ions in the ion implantation process are O ions or F ions, and the etching gas in the etching process is BCl 3 or Cl 2 .

[0025] In one embodiment, in the manufacturing method, “etching the barrier layer and a portion of the channel layer to form a source region and a drain region” specifically includes:

[0026] Performing ohmic etching on the barrier layer and part of the channel layer to form a source region and a drain region, wherein the depth of the ohmic etching is 0 to 30 nm below the interface between the channel layer and the barrier layer; or,

[0027] “Etching the barrier layer and part of the channel layer to form a source region and a drain region” specifically means:

[0028] Pre-etching a portion of the barrier layer, with the depth of the pre-etching being 0 to 10 nm;

[0029] The remaining barrier layer and part of the channel layer are ohmically etched to form a source region and a drain region. The depth of the ohmically etched is 0 to 30 nm below the interface between the channel layer and the barrier layer.

[0030] In one embodiment, in the manufacturing method, “etching the first passivation layer” specifically includes:

[0031] Etching the first passivation layer by using a dry etching process and / or a wet etching process;

[0032] Among them, the dry etching process uses plasma for etching, and the wet etching process uses acidic solution or alkaline solution for etching.

[0033] In one embodiment, the substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and / or,

[0034] A buffer layer is formed on the substrate, and the buffer layer is a combination of one or more of a GaN buffer layer, an AlN buffer layer, and an AlGaN buffer layer; and / or,

[0035] An isolation layer is formed in the channel layer and the barrier layer, and the isolation layer is a nitride isolation layer; and / or,

[0036] A cap layer is formed on the barrier layer, and the cap layer is a nitride cap layer; and / or,

[0037] The III-group nitride heterojunction is an AlGaN / GaN heterojunction; and / or,

[0038] The channel layer is a GaN channel layer with a thickness of 50 nm to 2 μm; and / or,

[0039] The barrier layer is Al x GaN1-x The barrier layer has a thickness of 10 nm to 30 nm, wherein x=0.1 to 0.3; and / or,

[0040] The first passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer.

[0041] In one embodiment, the manufacturing method further comprises:

[0042] forming a gate field plate electrically connected to the gate on the first passivation layer;

[0043] epitaxially growing a second dielectric layer on the first passivation layer and the gate field plate;

[0044] Etching the second passivation layer to expose the source and drain electrodes;

[0045] forming a source field plate electrically connected to the source electrode and / or a drain field plate electrically connected to the drain electrode on the second passivation layer;

[0046] epitaxially growing a third dielectric layer on the second passivation layer and the source field plate and / or the drain field plate;

[0047] Etching the third dielectric layer to expose all or part of the source field plate and / or the drain field plate;

[0048] Wherein, the gate, source, drain, gate field plate, source field plate and / or drain field plate are made of metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride;

[0049] The second passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer;

[0050] The third passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and a polyimide passivation layer.

[0051] The technical solution provided by an embodiment of the present invention is as follows:

[0052] A group III nitride enhanced HEMT device, wherein the group III nitride enhanced HEMT device is manufactured by the above-mentioned manufacturing method, and the group III nitride enhanced HEMT device comprises:

[0053] substrate;

[0054] A group III nitride heterojunction located on a substrate, wherein the group III nitride heterojunction includes a channel layer and a barrier layer, and a two-dimensional electron gas is formed in the channel layer;

[0055] A source region and a drain region are formed in the barrier layer and a portion of the channel layer;

[0056] A source electrode and a drain electrode, located in the source region and the drain region;

[0057] A first passivation layer, located above the barrier layer and the source and drain electrodes;

[0058] A source window, a drain window and a gate window, wherein the source window and the drain window are formed in the first passivation layer above the source and the drain, and the gate window is formed in the first passivation layer between the source window and the drain window;

[0059] An insulating dielectric layer located in a III-nitride heterojunction below the gate window;

[0060] A gate is located in the gate window.

[0061] The present invention has the following beneficial effects:

[0062] The present invention uses an inductively coupled plasma system to perform an oxidation process on the III-nitride heterojunction under the gate to form an insulating dielectric layer, which can improve the gate withstand voltage and reduce gate leakage, reduce the additional growth steps of the gate insulating dielectric, and reduce the difficulty of manufacturing the III-nitride enhanced device;

[0063] The oxidation process can precisely control the growth rate and thickness of the insulating dielectric layer and achieve a low damage effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 It is a schematic structural diagram of a III-nitride enhanced HEMT device in a specific embodiment of the present invention;

[0066] Figure 2 to Figure 12 FIG. 4 is a process flow chart of a method for manufacturing a group III nitride enhanced HEMT device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0068] Ginseng Figure 1 As shown, a III-nitride enhanced HEMT device in a specific embodiment of the present invention includes:

[0069] Substrate 10;

[0070] A buffer layer 20, located on the substrate 10;

[0071] A group III nitride heterojunction located on the buffer layer 20 , wherein the group III nitride heterojunction includes a channel layer 30 and a barrier layer 40 , and a two-dimensional electron gas 2DEG is formed in the channel layer 30 ;

[0072] The source region and the drain region are formed in the barrier layer 40 and a portion of the channel layer 30;

[0073] A source electrode 61 and a drain electrode 62, located in the source region and the drain region;

[0074] A first passivation layer 51 is located above the barrier layer 40 and the source electrode 61 and the drain electrode 62;

[0075] A source window, a drain window and a gate window, wherein the source window and the drain window are formed in the first passivation layer 51 above the source 61 and the drain 62, and the gate window is formed in the first passivation layer 51 between the source window and the drain window;

[0076] An insulating dielectric layer 70 is located in the III-nitride heterojunction below the gate window;

[0077] A gate 63, located in the gate window;

[0078] A gate field plate 631 , located above the first passivation layer 51 and electrically connected to the gate 63 ;

[0079] A second passivation layer 52 , located above the gate field plate 631 and the first passivation layer 51 ;

[0080] A source field plate 611 , located above the second passivation layer 52 and electrically connected to the source electrode 61 ;

[0081] The third passivation layer 53 is located above the source field plate 611 and the second passivation layer 52 .

[0082] The III-nitride enhanced HEMT device and the manufacturing method thereof in this embodiment are described in detail below with reference to the accompanying drawings.

[0083] Ginseng Figure 2 As shown, firstly, a buffer layer 20 and a group III nitride heterojunction are epitaxially grown on a substrate 10 . The group III nitride heterojunction includes a channel layer 30 and a barrier layer 40 . A two-dimensional electron gas 2DEG is formed in the channel layer 40 .

[0084] The substrate 10 is any one of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, etc.; the buffer layer 20 is a combination of one or more of a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, etc.; the III-group nitride heterojunction is an AlGaN / GaN heterojunction, the channel layer 30 is a GaN channel layer with a thickness of 50nm to 2μm, and the barrier layer 40 is Al x GaN 1-x The barrier layer has a thickness of 10 nm to 30 nm, wherein x=0.1 to 0.3.

[0085] Preferably, an isolation layer (not shown) is formed in the channel layer 30 and the barrier layer 40, and the isolation layer may be a nitride isolation layer, such as an aluminum nitride isolation layer (AlN spacer); preferably, a cap layer (not shown) is formed on the barrier layer 40, and the cap layer is a nitride cap layer, such as a gallium nitride cap layer.

[0086] Ginseng Figure 3 As shown, the barrier layer 40 and a portion of the channel layer 30 are etched to form a source region 601 and a drain region 602 .

[0087] This step can be:

[0088] Pre-etching a portion of the barrier layer 40, with the depth of the pre-etching being 0 to 10 nm;

[0089] The remaining barrier layer 40 and part of the channel layer 30 are ohmically etched to form a source region 601 and a drain region 602 . The depth of the ohmic etching is 0 to 30 nm below the interface between the channel layer and the barrier layer (AlGaN / GaN).

[0090] The ohmic etching and pre-etching in this embodiment help to reduce the annealing temperature of the ohmic metal and reduce the annealing time, so that the ohmic metal and the semiconductor layer can form an ohmic contact better. Of course, in other embodiments, the ohmic etching or pre-etching step may not be performed, and a higher annealing temperature or a longer annealing time will be required accordingly.

[0091] Ginseng Figure 4 As shown, a source 61 and a drain 62 are formed in the source region 601 and the drain region 602 , respectively.

[0092] The source and drain metal materials may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal may be formed by evaporation or sputtering, and after formation, the photoresist and excess metal may be removed by stripping, or the metal may be removed from the area other than the source and drain by metal etching.

[0093] Ginseng Figure 5 As shown, a first passivation layer 51 is epitaxially grown on the barrier layer 40 and the source 61 and the drain 62 .

[0094] The material of the first passivation layer can be an insulating medium such as silicon nitride, silicon oxide, and aluminum oxide, or a composite medium composed of different insulating media. After the first passivation layer is grown, it can be planarized by chemical mechanical polishing (CMP).

[0095] Ginseng Figure 6 As shown, an ion implantation process or an etching process is used to isolate the inactive region in the III-nitride heterojunction beside the source and drain to form an isolation region 80.

[0096] The passive area is isolated by an ion implantation process such as injecting strongly negatively charged O ions or F ions, or by an etching process, where the etching gas may be BCl3, Cl2, or the like.

[0097] If the isolation method adopts an etching process, this step can also be performed before the source and drain metals are formed. At this time, the first passivation layer has not yet been formed, which can reduce the etching depth and shorten the etching time.

[0098] Ginseng Figure 7 As shown, the first passivation layer 51 is etched to form a source window and a drain window above the source and the drain respectively, and a gate window penetrating the first passivation layer is formed between the source window and the drain window.

[0099] The window can be formed by dry plasma etching, or wet etching using an acidic or alkaline solution, or by a combination of dry etching and wet etching.

[0100] Preferably, the medium close to the surface of the AlGaN barrier layer can be removed by wet etching or low-damage etching to reduce the damage to the AlGaN surface.

[0101] Ginseng Figure 8a As shown, an inductively coupled plasma system is used to perform an oxidation process on the III-nitride heterojunction below the gate window to form an insulating dielectric layer 70.

[0102] The inductively coupled plasma (ICP) system is a high-density, low-pressure system with two independent RF power sources (13.56MHz). It can obtain high-density plasma at low pressure. The plasma density and plasma bombardment energy are independently controllable. Compared with the reactive ion etching system, it has a higher reaction rate and lower etching damage, and can maintain good anisotropy in the high aspect ratio window.

[0103] In the oxidation process of this embodiment, the oxidizing gas includes (O2) and nitrous oxide (N2O), the gas flow rate is 10-80 sccm, the chamber pressure is 8-20 mTorr (1 mTorr = 0.133 Pa), the RF power range is 5-100 W, and the inductively coupled plasma power is 100-300 W. Preferably, a carrier gas may also be mixed into the gas, and the carrier gas may be an inert gas such as nitrogen (N2) or argon (Ar).

[0104] Aluminum gallium nitride will produce aluminum oxide and gallium oxide after being treated with oxygen or nitrous oxide plasma, and gallium nitride will produce gallium oxide after being treated with oxygen or nitrous oxide plasma, wherein aluminum oxide and gallium oxide can both be used as insulating dielectric layers of the gate.

[0105] It is worth noting that the parameters in the system reaction process, such as gas flow, chamber pressure, RF power and inductively coupled plasma power, can affect the oxidation rate and damage degree, and the time of the control process can affect the thickness of the insulating dielectric layer. Generally, when the thickness of AlGaN is less than 10nm, two-dimensional electron gas cannot be formed underneath it, and the transistor will be transformed from depletion mode to enhancement mode. The smaller the thickness of AlGaN or the thicker the insulating dielectric layer, the threshold voltage and gate leakage will increase or decrease accordingly. When GaN is also oxidized, the changes in threshold voltage and gate leakage will be very obvious. However, in this case, the damage to the two-dimensional electron gas channel will also increase.

[0106] As in this embodiment, part of the barrier layer below the gate window is oxidized to form an insulating dielectric layer 70, the lower surface of the insulating dielectric layer 70 is located above the interface between the channel layer and the barrier layer, and the thickness of the barrier layer below the insulating dielectric layer is less than or equal to 10 nm.

[0107] Ginseng Figure 8b As shown, in another embodiment of the present invention, the entire barrier layer below the gate window is oxidized to form an insulating dielectric layer 70, and the lower surface of the insulating dielectric layer 70 is located at the interface between the channel layer and the barrier layer.

[0108] Ginseng Figure 8c As shown, in another embodiment of the present invention, the entire barrier layer and a portion of the channel layer below the gate window are oxidized to form an insulating dielectric layer 70, and the lower surface of the insulating dielectric layer 70 is located below the interface between the channel layer and the barrier layer.

[0109] The thickness of the insulating dielectric layer in the above three embodiments is different, and the corresponding enhanced HEMT devices exhibit significantly different electrical characteristics.

[0110] Compared with the processing method performed in a conventional reactive ion etching (RIE) system, the advantage of the present invention is that the oxidation rate can be precisely varied within the range of 0.5 to 2 nm / min using an inductively coupled plasma system, and the rate is stable.

[0111] Ginseng Figure 8d As shown, in another embodiment of the present invention, the insulating dielectric layer is treated with an alkaline solution and an acidic solution, which can also achieve the effect of controlling the thickness of the insulating dielectric layer.

[0112] The alkaline solution may be sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonia (NH4OH), tetramethylammonium hydroxide (TMAH), etc., and the acidic solution may be hydrochloric acid (HCl), etc. Through multiple oxidation-removal cycles, the thickness of the remaining insulating dielectric layer can be precisely controlled, and a low damage effect can be achieved.

[0113] Ginseng Fig. 9 As shown, a gate 63 is formed in the gate window, and a gate field plate 631 electrically connected to the gate 63 is formed on the first passivation layer 51 .

[0114] The gate metal and gate field plate materials may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal may be formed by evaporation or sputtering. After formation, the photoresist and excess metal may be removed by stripping, or by metal etching. At this time, the gate and the insulating dielectric layer and semiconductor layer below it form a metal-insulator-semiconductor (MIS) structure.

[0115] Ginseng Fig.10 As shown, a second dielectric layer 52 is epitaxially grown on the first passivation layer 51 and the gate field plate 631 , and the second passivation layer 52 is etched to expose the source 61 and the drain 62 .

[0116] The material of the second passivation layer can be an insulating medium such as silicon nitride, silicon oxide, or a composite medium composed of different insulating media. After the second passivation layer is grown, it can be planarized by chemical mechanical polishing (CMP).

[0117] Next, windows are formed in the source and drain regions. The windows may be formed by dry plasma etching, wet etching using an acid solution, or a combination of dry etching and wet etching.

[0118] Ginseng Fig.11 As shown, a source field plate 611 electrically connected to the source electrode 61 is formed on the second passivation layer 52 .

[0119] The source field plate material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The source field plate metal may be formed by evaporation or sputtering, and after formation, the photoresist and excess metal may be removed by stripping, or the metal in the area other than the source field plate and the drain may be removed by metal etching.

[0120] Ginseng Fig.12 As shown, a third dielectric layer 53 is epitaxially grown on the second passivation layer 52 and the source field plate, and the third dielectric layer is etched to expose the source field plate and the drain.

[0121] The material of the third passivation layer can be an insulating medium such as silicon nitride, silicon oxide, polyimide (PI), or a composite medium composed of different insulating media. After the third passivation layer is grown, it can be planarized by chemical mechanical polishing (CMP).

[0122] Next, windows are formed in the source and drain regions. The windows can be formed by dry plasma etching, or by wet etching using an acid solution selected according to the material of the dielectric layer, or by a combination of dry etching and wet etching.

[0123] It should be understood that the above embodiments are described by taking the setting of gate field plates and source field plates as an example, and the corresponding second passivation layer and third passivation layer need to be epitaxially grown on the first passivation layer. In other embodiments, gate field plates and source field plates may not be set, or drain field plates may be added, all of which fall within the scope of protection of the present invention.

[0124] In the present invention, an inductively coupled plasma system is used to process the AlGaN / GaN heterojunction structure, which can accurately control the growth rate and thickness of the insulating dielectric layer and achieve a low damage effect. This method for making an enhanced gallium nitride device based on an inductively coupled plasma system can utilize conventional depletion-type gallium nitride transistor epitaxy, which reduces production costs while having good compatibility with the depletion-type gallium nitride transistor process. The oxidized AlGaN / GaN material will produce insulating aluminum oxide (Al2O3) and gallium oxide (Ga2O3), which can be used as insulating media to improve gate withstand voltage and reduce gate leakage, which also reduces the additional growth steps of the gate insulating medium, has practical significance, and helps to reduce the difficulty of making enhanced gallium nitride transistors.

[0125] It can be seen from the above technical solutions that the present invention has the following advantages:

[0126] The present invention uses an inductively coupled plasma system to perform an oxidation process on the III-nitride heterojunction under the gate to form an insulating dielectric layer, which can improve the gate withstand voltage and reduce gate leakage, reduce the additional growth steps of the gate insulating dielectric, and reduce the difficulty of manufacturing the III-nitride enhanced device;

[0127] The oxidation process can precisely control the growth rate and thickness of the insulating dielectric layer and achieve a low damage effect.

[0128] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0129] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a group III nitride enhanced HEMT device, characterized in that: The manufacturing method comprises: providing a substrate; A III-group nitride heterojunction is epitaxially grown on a substrate, wherein the III-group nitride heterojunction includes a channel layer and a barrier layer, wherein a two-dimensional electron gas is formed in the channel layer, wherein the III-group nitride heterojunction is an AlGaN / GaN heterojunction, wherein the channel layer is a GaN channel layer with a thickness of 50 nm to 2 μm, and the barrier layer is an Al x GaN 1-x Barrier layer, thickness is 10nm~30nm, where x=0.1~0.3; Etching the barrier layer and part of the channel layer to form a source region and a drain region; forming a source electrode and a drain electrode in the source region and the drain region, respectively; epitaxially growing a first passivation layer over the barrier layer and the source and drain electrodes; Only the first passivation layer is etched to form a source window and a drain window above the source and the drain respectively, and a gate window penetrating the first passivation layer is formed between the source window and the drain window, and then an inductively coupled plasma system is directly used to perform an oxidation process on the III-nitride heterojunction below the gate window to form an insulating dielectric layer; forming a gate in the gate window; Part of the barrier layer below the gate window is oxidized to form an insulating dielectric layer, the lower surface of the insulating dielectric layer is located above the interface between the channel layer and the barrier layer, and the thickness of the barrier layer below the insulating dielectric layer is less than or equal to 10nm; or, the entire barrier layer below the gate window is oxidized to form an insulating dielectric layer, and the lower surface of the insulating dielectric layer is located at the interface between the channel layer and the barrier layer; or, the entire barrier layer and part of the channel layer below the gate window are oxidized to form an insulating dielectric layer, and the lower surface of the insulating dielectric layer is located below the interface between the channel layer and the barrier layer; In the oxidation process, the oxidizing gas includes oxygen and / or nitrous oxide, the gas flow rate is 10-80 sccm, the chamber pressure is 8-20 mTorr, the RF power range is 5-100 W, the inductively coupled plasma power is 100-300 W, and the oxidation rate is 0.5-2 nm / min.

2. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: The manufacturing method further comprises: An alkaline solution and an acidic solution are used to remove a portion of the insulating dielectric layer. The alkaline solution includes one or more of sodium hydroxide, potassium hydroxide, ammonia water, and tetramethylammonium hydroxide solution. The acidic solution includes a hydrochloric acid solution.

3. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: In the manufacturing method, before or after the step of "epitaxially growing a first passivation layer on the barrier layer and the source and drain electrodes", the following steps are further included: An ion implantation process or an etching process is used to isolate a passive region in the III-nitride heterojunction beside the source and / or drain to form an isolation region; The ions in the ion implantation process are O ions or F ions, and the etching gas in the etching process is BCl 3 or Cl 2 .

4. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: In the manufacturing method, “etching the barrier layer and part of the channel layer to form a source region and a drain region” specifically includes: Performing ohmic etching on the barrier layer and part of the channel layer to form a source region and a drain region, wherein the depth of the ohmic etching is 0 to 30 nm below the interface between the channel layer and the barrier layer; or, “Etching the barrier layer and part of the channel layer to form a source region and a drain region” specifically includes: Pre-etching part of the barrier layer, with the depth of pre-etching being 0-10 nm; The remaining barrier layer and part of the channel layer are ohmically etched to form a source region and a drain region. The depth of the ohm etching is 0 to 30 nm below the interface between the channel layer and the barrier layer.

5. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: In the manufacturing method, “etching the first passivation layer” specifically includes: Etching the first passivation layer by using a dry etching process and / or a wet etching process; Among them, the dry etching process uses plasma for etching, and the wet etching process uses acidic solution or alkaline solution for etching.

6. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: The substrate is any one of a silicon substrate, a sapphire substrate and a silicon carbide substrate; and / or, A buffer layer is formed on the substrate, and the buffer layer is a combination of one or more of a GaN buffer layer, an AlN buffer layer, and an AlGaN buffer layer; and / or, An isolation layer is formed in the channel layer and the barrier layer, and the isolation layer is a nitride isolation layer; and / or, A cap layer is formed on the barrier layer, and the cap layer is a nitride cap layer; and / or, The first passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer.

7. The method for manufacturing a III-nitride enhanced HEMT device according to claim 1, characterized in that: The manufacturing method further comprises: forming a gate field plate electrically connected to the gate on the first passivation layer; epitaxially growing a second dielectric layer on the first passivation layer and the gate field plate; Etching the second passivation layer to expose the source and drain electrodes; forming a source field plate electrically connected to the source electrode and / or a drain field plate electrically connected to the drain electrode on the second passivation layer; epitaxially growing a third passivation layer on the second passivation layer and the source field plate and / or the drain field plate; Etching the third passivation layer to expose all or part of the source field plate and / or the drain field plate; Wherein, the gate, source, drain, gate field plate, source field plate and / or drain field plate are made of metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride; The second passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer; The third passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and a polyimide passivation layer.

8. A III-nitride enhanced HEMT device, characterized in that: The III-group nitride enhanced HEMT device is manufactured by the manufacturing method according to any one of claims 1 to 7, and the III-group nitride enhanced HEMT device comprises: substrate; A group III nitride heterojunction located on a substrate, wherein the group III nitride heterojunction includes a channel layer and a barrier layer, and a two-dimensional electron gas is formed in the channel layer; A source region and a drain region are formed in the barrier layer and a portion of the channel layer; A source electrode and a drain electrode, located in the source region and the drain region; A first passivation layer, located above the barrier layer and the source and drain electrodes; A source window, a drain window and a gate window, wherein the source window and the drain window are formed in the first passivation layer above the source and the drain, and the gate window is formed in the first passivation layer between the source window and the drain window; An insulating dielectric layer located in a III-nitride heterojunction below the gate window; A gate is located in the gate window.

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