Fan-out package landfill method

Abstract

The present invention relates to the field of chip packaging technology, and specifically discloses a fan-out type packaging embedding method, comprising the following steps: step S12: embed the chip to be packaged into the groove of the fan-out substrate, and deposit a parylene dielectric layer on the upper surface of the chip, the gap between the side of the chip and the side wall of the groove; step S13: form a metal layer on the parylene dielectric layer; step S14: use the metal layer as a mask and use a dual damascene process; repeat steps S13-S14n times in sequence to form n layers of wiring in the parylene dielectric layer, wherein n≥1, and each layer of wiring is connected to pads at different positions on the chip or to different positions of the fan-out substrate. The parylene dielectric layer of the present invention has a good gap filling effect, basically no bubbles and cavities are generated inside, and the surface flatness is high, the process stability is high, the process compatibility is good, and the wiring layer stress can also be reduced.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, and in particular discloses a fan-out type packaging embedding method. Background Art

[0002] The International Technology Roadmap for Semiconductors (ITRS) clearly puts forward two directions for the development of integrated circuit technology in the future: one is More Moore (continuing Moore's Law), and the other is More than Moore (extending Moore's Law). The technical route that develops along the direction of extending Moore's Law focuses more on integrating multiple functional chips into one system. At present, advanced packaging is considered to be an important development direction for semiconductor technology in the next stage. As the development of Moore's Law slows down, the use of advanced packaging technology to meet the miniaturization and multi-functionality of the system has become a new engine for the development of the integrated circuit industry.

[0003] Among them, fan-out packaging is a typical three-dimensional packaging method. After placing the chip on a substrate with grooves dug, it is connected through a redistribution layer (RDL), which can improve device density and achieve high-performance packaging interconnection.

[0004] In the process of realizing fan-out packaging, filling is a key link. Polyimide (PI) is usually used to fill the gap between the chip and the fan-out slot, but polyimide has inherent disadvantages, including: it requires a high temperature of about 300 degrees Celsius during curing, and has poor process compatibility; the gap cannot be completely filled due to shrinkage after curing; if vacuum is not drawn during spin coating, there will be bubbles inside, affecting the stability of the later process, but vacuum drawing requires a complex process, etc. Summary of the invention

[0005] The main purpose of the present invention is to provide a fan-out package embedding method, aiming to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above object, the present invention proposes a fan-out package embedding method, comprising the following steps:

[0007] Step S12: embedding the chip to be packaged into the groove of the fan-out substrate, and depositing a parylene dielectric layer on the upper surface of the chip and in the gap between the side surface of the chip and the side wall of the groove;

[0008] Step S13: forming a metal layer on the parylene dielectric layer;

[0009] Step S14: using the metal layer as a mask and utilizing a dual damascene process;

[0010] Repeat steps S13-S14 n times in sequence to form n layers of wiring in the parylene dielectric layer, wherein n≥1, and each layer of wiring is connected to pads at different positions on the chip or to different positions on the fan-out substrate.

[0011] In addition, the above-mentioned fan-out packaging embedding method of the present invention may also have the following additional technical features.

[0012] According to one embodiment of the present invention, step S14 includes the following steps:

[0013] Etching openings on the surface of the metal layer, wherein positions of the openings correspond to pad positions of the chip or positions to be connected on the fan-out substrate;

[0014] Etching the parylene dielectric layer using the metal layer as a mask, wherein the etching depth is less than the thickness of the parylene dielectric layer;

[0015] Etching a wiring pattern on the surface of the metal layer, wherein the wiring pattern is connected to the opening;

[0016] Using the metal layer as a mask, the parylene dielectric layer is etched again until the chip surface corresponding to the opening position is exposed, so as to form a wiring groove in the parylene dielectric layer;

[0017] removing the metal layer;

[0018] A metal seed layer is formed on the inner surface of the wiring groove, and metal is filled in the wiring groove, and a planarization process is performed to form a wiring layer.

[0019] According to an embodiment of the present invention, the total depth of etching the parylene dielectric layer twice is not less than the thickness of the parylene dielectric layer.

[0020] According to an embodiment of the present invention, the raw materials for preparing the parylene dielectric layer are p-xylene cyclodimer and its chloride, and the method for preparing the parylene dielectric layer is vacuum vapor deposition.

[0021] According to one embodiment of the present invention, the parylene dielectric layer is selected from a mixture of one or more of parylene-N, parylene-C, parylene-D, and parylene-AF4.

[0022] According to one embodiment of the present invention, the step of embedding the chip to be packaged into the groove of the silicon substrate includes:

[0023] The chip is fixed in the groove using an organic adhesive material, with the solder tab of the chip facing outward.

[0024] According to an embodiment of the present invention, the number of the grooves is not less than one, and at least one chip is buried in each groove.

[0025] According to an embodiment of the present invention, the metal layer is made of a metal with a high parylene selectivity, and the thickness of the metal layer is no more than 1 μm.

[0026] According to an embodiment of the present invention, the material of the metal layer is selected from Ti, Al or Ta, and the metal layer is removed by an etching or corrosion process.

[0027] According to one embodiment of the present invention, the material of the metal seed layer and the metal filled in the wiring groove is selected from any one of Cu, Al, Ti, Au, Ag, Pt, Ni, Cr and Zn.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The deposition environment of the parylene dielectric layer of the present invention is a vacuum, so the gap filling effect is good, and basically no bubbles and cavities are generated inside. In addition, the surface flatness is high, the process stability is high, the process compatibility is good, and the wiring layer stress can be further reduced. In contrast, it is difficult to avoid the appearance of bubbles during the spin coating and curing process of polyimide (PI), which will cause cavities in the gaps and affect the process stability. Even if a vacuum is drawn, it is difficult to achieve complete filling. In addition, during the curing process of PI, the solvent will evaporate, and eventually grooves will be formed on the surface, which is not conducive to the later process;

[0030] 2. The deposition process of the parylene dielectric layer of the present invention is a low-temperature process, and the process environment can be at room temperature, so the process compatibility is better;

[0031] 3. The parylene dielectric layer of the present invention is softer than PI and can relieve internal stress;

[0032] 4. The parylene dielectric layer of the present invention has many types and high selectivity. Different types of parylene dielectric layers can be selected according to needs. For example, parylene-N and parylene-AF4 have high heat resistance and are suitable for subsequent processes requiring heating.

[0033] 5. The parylene dielectric layer of the present invention has good electrical insulation and mechanical properties, and can also be used as the dielectric of the wiring layer to achieve good insulation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0035] Figure 1 This is a flow chart of a fan-out package filling method in one embodiment of the present application;

[0036] Figure 2 A schematic diagram of a structure for cutting grooves on a fan-out substrate in one embodiment of the present application;

[0037] Figure 3 For Figure 2 A schematic diagram of the structure after a chip is embedded in the groove and a parylene dielectric layer is deposited;

[0038] Figure 4 For Figure 3 Schematic diagram of the structure after a metal layer is deposited on the parylene dielectric layer;

[0039] Figure 5 For Figure 4 Schematic diagram of the structure after the metal layer surface is etched to form openings;

[0040] Figure 6 For Figure 5 Schematic diagram of the structure after continuing to etch the opening;

[0041] Figure 7 For Figure 6 A schematic diagram of a structure after a wiring pattern is formed on the basis of the wiring pattern;

[0042] Figure 8 For Figure 7 A schematic diagram of a structure after a wiring groove is formed on the basis of the wiring groove;

[0043] Fig. 9 For Figure 8 Schematic diagram of the structure after removing the metal layer;

[0044] Fig.10 For Fig. 9 Schematic diagram of the structure after metal is filled on the basis;

[0045] Fig.11 For Fig.10 Schematic diagram of the structure after flattening on the basis of;

[0046] Fig.12 For Fig.11 A schematic diagram of the structure after the second layer wiring is formed on this basis.

[0047] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0049] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0050] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0051] Refer to the following Figure 1-12 The fan-out package filling method of some embodiments of the present invention is described. Figure 1 As shown, the specific steps include:

[0052] Step S11: Figure 2 As shown, a groove 101 is formed on the fan-out substrate 10;

[0053] Specifically, a fan-out substrate 10 is provided, and a groove 101 slightly larger than the size of the chip 11 to be packaged is etched on the front of the fan-out substrate 10. Specifically, the material of the fan-out substrate 10 can be PCB or silicon, the number of the grooves 101 can be multiple, the depth of the grooves 101 is not less than 10 μm, and one or more chips 11 to be packaged can be buried in each groove 101.

[0054] Step S12: Figure 3 As shown, a chip 11 to be packaged is buried in a groove 101, and a parylene dielectric layer 12 is deposited on the upper surface of the chip, the side of the chip and the gap between the sidewall of the groove;

[0055] Specifically, the chip 11 is fixed in the groove 101 using an organic adhesive material, with the soldering pad of the chip 11 facing outward, wherein the organic adhesive material may be a polymer glue or a polymer adhesive film. In addition, the gap between the side of the chip 11 and the side wall of the groove 101 is no greater than 10 μm, and the height difference between the chip 11 and the plane on the silicon substrate after being buried is no more than 5 μm;

[0056] Next comes the wiring;

[0057] Step S13: Figure 4 As shown, a metal layer 13 is deposited on the parylene dielectric layer 12;

[0058] Specifically, the metal layer 13 is made of one or more metal materials, and its thickness is no more than 1 μm. The metal layer 13 is made of a metal with a high parylene selectivity, such as Ti, Al, and Ta.

[0059] Step S14: Figure 5 As shown, a photolithography process is used to etch an opening 130 on the surface of the metal layer 13; specifically, the position of the opening 130 corresponds to the pad position of the chip 11 or the position to be connected on the fan-out substrate 10;

[0060] Step S15: Figure 6 As shown, the parylene dielectric layer 12 is etched using the metal layer 13 as a mask to continue etching downward to open the hole 130, and the etching depth is less than the thickness of the parylene dielectric layer 12;

[0061] Step S16: Figure 7 As shown, the photolithography process is again used to etch the surface of the metal layer 13 to form a wiring pattern 131, and the wiring pattern 131 is connected to the opening 130;

[0062] Step S17: Figure 8 As shown, the metal layer 13 is used as a mask to etch the parylene dielectric layer 12 again until the surface of the chip 11 corresponding to the position of the opening 130 is exposed, so as to form a wiring groove 120 in the parylene dielectric layer 12. Specifically, after the etching is completed, the parylene dielectric layer 12 corresponding to the opening 130 is completely etched away, that is, the etching depths of the two times before and after are equal to the thickness of the parylene dielectric layer 12. It should be noted that a layer of parylene dielectric layer 12 is still retained on the surface of the chip 11 not corresponding to the opening 130;

[0063] Step S18: Fig. 9 As shown, the metal layer 13 is removed by corrosion or etching process;

[0064] Step S19: Fig.10 As shown, a metal seed layer is formed on the inner surface of the wiring groove 120 by PVD sputtering or evaporation, and the metal 14 is filled in the wiring groove by electroplating. Specifically, the material of the metal seed layer and the metal 14 filled in the wiring groove can be selected from Cu, Al, Ti, Au, Ag, Pt, Ni, Cr and Zn, etc.;

[0065] Step S20: Fig.11 As shown, a flattening process is performed to form a layer of metal wiring. Specifically, a polishing process is used to polish the surface of the parylene dielectric layer 12;

[0066] Step S21: Fig.12As shown, steps S13-S20 are repeated to form a second layer wiring 15 connected to the pad of the chip 11 on the fan-out substrate 10;

[0067] Those skilled in the art may repeat steps S13 - S20 several times as needed to form an N-th layer of wiring connected to the pads of the chip 11 on the fan-out substrate 10 , which will not be elaborated herein.

[0068] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0069] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A fan-out package embedding method, characterized in that: The following steps are involved: Step S12: embedding the chip to be packaged into the groove of the fan-out substrate, and vacuum vapor depositing a parylene dielectric layer on the upper surface of the chip, the gap between the side of the chip and the side wall of the groove; the raw material for preparing the parylene dielectric layer is p-xylene cyclodimer and its chloride, and the parylene dielectric layer is selected from a mixture of one or more of parylene-N, parylene-C, parylene-D, and parylene-AF4; Step S13: forming a metal layer on the parylene dielectric layer; Step S14: etching openings on the surface of the metal layer, wherein the positions of the openings correspond to the pad positions of the chip or the positions to be connected on the fan-out substrate; Etching the parylene dielectric layer using the metal layer as a mask, wherein the etching depth is less than the thickness of the parylene dielectric layer; Etching a wiring pattern on the surface of the metal layer, wherein the wiring pattern is connected to the opening; Using the metal layer as a mask, the parylene dielectric layer is etched again until the chip surface corresponding to the opening position is exposed, so as to form a wiring groove in the parylene dielectric layer; removing the metal layer; Forming a metal seed layer on the inner surface of the wiring groove, filling the wiring groove with metal, and flattening the groove to form a wiring layer; Steps S13-S14 are repeated n times in sequence using a dual damascene process to form n layers of wiring in the parylene dielectric layer, wherein n≥1, and each layer of wiring is connected to pads at different positions on the chip or to different positions on the fan-out substrate.

2. The fan-out package embedding method according to claim 1, characterized in that: The total depth of etching the parylene dielectric layer twice is not less than the thickness of the parylene dielectric layer.

3. The fan-out package embedding method according to claim 1, characterized in that: The step of embedding the chip to be packaged into the groove of the fan-out substrate comprises: The chip is fixed in the groove using an organic adhesive material, with the solder tab of the chip facing outward.

4. The fan-out package embedding method according to claim 1, characterized in that: The number of the grooves is not less than one, and at least one chip is buried in each groove.

5. The fan-out package embedding method according to claim 1, characterized in that: The metal layer is made of a metal with a high parylene selectivity, and the thickness of the metal layer is no more than 1 μm.

6. The fan-out package embedding method according to claim 5, characterized in that: The material of the metal layer is selected from Ti, Al or Ta, and the metal layer is removed by etching or corroding process.

7. The fan-out package embedding method according to any one of claims 1 to 6, characterized in that: The material of the metal seed layer and the metal filled in the wiring groove is selected from any one of Cu, Al, Ti, Au, Ag, Pt, Ni, Cr and Zn.

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