Invisible semiconductor device and its preparation method and application

Abstract

The present invention discloses an invisible semiconductor device and its preparation method and application. The preparation method comprises: forming a sacrificial layer, an epitaxial layer and a nanocolumn array in sequence on an epitaxial substrate, wherein the epitaxial layer and the nanocolumn array both contain III-V semiconductor materials; providing an insulating material layer that at least covers the nanocolumn array, and processing at least one window on the insulating material layer so that at least part of the nanocolumn array is exposed from the window; providing a first electrode at the window of the insulating material layer so that the first electrode is electrically connected to the nanocolumn array exposed from the window, the first electrode is a transparent electrode, and providing a second electrode on the area of ​​the insulating material layer other than the window, thereby forming an invisible semiconductor device. The invisible semiconductor device provided by the present invention has a long service life, and the invisible semiconductor device has a vertical nanocolumn array, which is conducive to releasing epitaxial stress and improving crystal quality.

Description

Technical Field

[0001] The present invention relates to an invisible semiconductor device, in particular to an invisible semiconductor device and a preparation method and application thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Invisibility, commonly known as "invisible", and "transparency" can also achieve the effect of invisibility. In recent years, stealth technology has received more and more attention from the world. It can be applied to stealth aircraft, invisible cloaks, etc. It is a high-tech technology that humans dream of. In order to achieve invisibility, many researchers have introduced negative refractive index materials, hoping to achieve the "transparency" of materials through complex electromagnetic wave regulation. Although the technology has broad application prospects, it is extremely difficult and it will still take a long time to be truly applied. Therefore, stealth technology will remain a global difficulty for a long time in the future.

[0003] Semiconductor devices have a wide range of applications, such as blue light-emitting devices (LEDs) and ultraviolet detectors, which can be used in many fields such as lighting, image display, missile detection, fire detection, radiation detection and confidential communications. GaN (commonly known as gallium nitride)-based materials have the advantages of wide band gap, high thermal conductivity, stable physical and chemical properties, strong radiation resistance, and continuously adjustable band gap. The wavelength of (Al, Ga) N materials can cover the ultraviolet band of 200-365nm, and (In, Ga) N materials can cover the visible light band (380nm-400nm), which is an ideal choice for the preparation of semiconductor devices. GaN-based invisible semiconductor devices have great application prospects. For example, invisible display devices using invisible light-emitting devices can be used in automobile windshield navigation, train glass display, smart skin and other fields, while invisible detectors can greatly improve the concealment of detectors. Therefore, invisible semiconductor devices have high application value in both military and civilian fields.

[0004] Although GaN-based invisible semiconductor devices have broad application prospects, they are extremely challenging. The reason is that it is difficult for current semiconductor devices to obtain invisible characteristics. Although some two-dimensional materials (such as graphene) have transparent (invisible) characteristics, they do not have the functions of semiconductor devices and cannot be used independently as semiconductor devices. On the other hand, there is no definition standard for invisible semiconductor devices at this stage. Another synonym for invisible is transparent, but we believe that the two are not completely equivalent. Invisible can be roughly described as high transparency. Since the definition in this regard is still in a blank stage, we believe that in the visible light range (380nm-400nm), the minimum transmittance of semiconductor devices is greater than 90% and can be considered invisible, and between 50%-90% is semi-invisible.

[0005] One-dimensional (nano-column) semiconductor materials can alleviate the stress problem caused by substrate mismatch and improve crystal quality. Compared with films of the same thickness, nano-column structures have higher transmittance, that is, higher transparency. At the same time, when nano-column materials are bent, they can avoid damage caused by squeezing between materials, thereby improving flexibility. At present, there are reports (CN107785355A, Adv. Mater. 2011, 23, 4614) proposing to first prepare graphene on the SiO2 / Si surface, then grow a GaN-based nanocolumn array (i.e., a one-dimensional GaN-based material), and finally peel off the graphene and the nanocolumns and transfer them to a flexible substrate; this scheme can theoretically prepare flexible devices with transparency, but it also has certain limitations: A. Currently, the direct epitaxial growth of one-dimensional GaN-based materials on graphene is not mature, and the quality of its epitaxial crystals is difficult to guarantee. During the epitaxial growth process, the graphene will also be damaged to a certain extent; B. Graphene itself is an extremely thin film, and the thickness of a single layer of graphene is about 0.1 nm. Graphene itself is very easy to be damaged. In other words, the step of simultaneously peeling off the graphene and the nanocolumns and transferring them to the flexible substrate is difficult in actual operation and is very easy to damage the graphene or the nanocolumns.

[0006] On the other hand, there are also articles reporting the use of tape (Carbon 2018, 130, 390) or a siloxane (PDMS) material (Nano Lett. 2015, 15, 6958) to directly peel off the nanopillar array by mechanical force; although this mechanical peeling method has the advantages of low cost and low difficulty, the direct peeling method by mechanical force will damage the crystal quality and uniformity of the bottom of the nanopillar arrangement, and the tape or PDMS material used to connect the nanopillars will reduce the transparency of the film after peeling. Therefore, the ability to prepare invisible semiconductor devices while having the advantages of low cost and low difficulty is still a technical problem that needs to be solved in the industry. Summary of the invention

[0007] The main purpose of the present invention is to provide an invisible semiconductor device and a preparation method and application thereof to overcome the deficiencies in the prior art.

[0008] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0009] An embodiment of the present invention provides a method for preparing an invisible semiconductor device, which comprises:

[0010] forming a sacrificial layer, an epitaxial layer and a nanocolumn array in sequence on the epitaxial substrate, wherein the epitaxial layer and the nanocolumn array both contain III-V group semiconductor materials;

[0011] Disposing an insulating material layer that at least covers the nanorod array, and processing at least one window on the insulating material layer so that at least a portion of the nanorod array is exposed from the window;

[0012] A first electrode is arranged at the window of the insulating material layer, so that the first electrode is electrically connected to the nanorod array exposed from the window, and the first electrode is a transparent electrode; and

[0013] A second electrode is arranged on the region of the insulating material layer except the window, thereby forming an invisible semiconductor device.

[0014] Furthermore, the preparation method also includes: destroying the sacrificial layer to peel off the epitaxial structure or invisible semiconductor device on the sacrificial layer as a whole, transferring the peeled epitaxial structure or invisible semiconductor device, so that the epitaxial layer is directly set on the transparent conductive substrate; wherein, the step of destroying the sacrificial layer to achieve the transfer of the epitaxial structure or invisible semiconductor device can be performed after forming the nanocolumn array and before or after forming the invisible semiconductor device.

[0015] Furthermore, the preparation method specifically includes: forming the epitaxial structure or invisible semiconductor device on the first surface of the epitaxial substrate, and forming an electrode conductive to the sacrificial layer on the second surface of the epitaxial substrate opposite to the first surface, and then removing the sacrificial layer by electrochemical etching.

[0016] Furthermore, the preparation method specifically includes: forming an electrode (such as an In ball) on the second surface of the epitaxial substrate that is conductive with the sacrificial layer, and covering the electrode with an epoxy resin so that the electrode is not conductive with the electrochemical solution; then performing electrochemical etching in an electrochemical solution (such as a KOH solution) to etch away the sacrificial layer, wherein the voltage used in the electrochemical etching is U, 0.2V≤U≤600V

[0017] Furthermore, the nanocolumn array includes a plurality of nanocolumns, and any of the nanocolumns includes a first nanocolumn, a second nanocolumn and a third nanocolumn formed in sequence along a direction away from the epitaxial layer.

[0018] Furthermore, at least one of the first nanorod, the second nanorod and the third nanorod is a single-layer or multi-layer structure.

[0019] Furthermore, the first nano-pillar, the second nano-pillar and the third nano-pillar are n-type doped or p-type doped.

[0020] Furthermore, the n-type doping or p-type doping concentration of the first nanorod, the second nanorod and the third nanorod is 1×10 18 -1×10 24 cm -3 .

[0021] Furthermore, the first nanorod comprises Al 1-m Gam N nanorods, 0<m≤1, but not limited thereto.

[0022] Furthermore, the second nanorod includes In 1-n-x Al n Ga x N or gallium oxide or indium gallium zinc oxide nanorods, 0≤x≤1, 0≤n≤1, 0≤n+x≤1, but not limited thereto.

[0023] Furthermore, the third nanorod comprises Al 1-z Ga z N nanorods, 0<z≤1, but not limited thereto.

[0024] Furthermore, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of the Al component or the content of the In component in the N nanocolumn is uniformly distributed or increases or decreases gradually.

[0025] Furthermore, the height of the first nanocolumn is 100nm-2000nm, the height of the second nanocolumn is 20nm-800nm, and the height of the third nanocolumn is 0nm-800nm.

[0026] Furthermore, the diameter of the single nanocolumn does not exceed 300 nm.

[0027] Furthermore, the epitaxial layer is an epitaxial layer having pores or defects.

[0028] Furthermore, the epitaxial layer is a GaN epitaxial layer having pores or defects.

[0029] Furthermore, the density of pores or defects in the epitaxial layer is greater than 1×10 13 m -2

[0030] Furthermore, the total thickness of the epitaxial layer is H1, 1nm≤H1<600nm.

[0031] Furthermore, the sacrificial layer includes a single layer or multiple layers of Al 1-b Ga b N layers, where 0≤b<1, and the b values ​​corresponding to two adjacent layers are different.

[0032] Furthermore, the thickness of the sacrificial layer is H0, 1nm≤H0<100nm.

[0033] Furthermore, the epitaxial substrate includes any one or a combination of two or more of a silicon wafer, a sapphire substrate, a GaN self-supporting substrate, a silicon carbide substrate, a diamond substrate, a metal substrate, and a substrate covered with a two-dimensional thin film material, but is not limited thereto.

[0034] Furthermore, the transparent conductive substrate includes any one of a conductive film, a two-dimensional thin film material, and glass, epoxy resin, and a transparent tape with indium tin oxide or silver nanowires formed on the surface, but is not limited thereto.

[0035] Furthermore, a colloid having conductive, transparent and adhesive properties is formed on the transparent conductive substrate.

[0036] Furthermore, the insulating material layer is made of silicon oxide.

[0037] Furthermore, the thickness of the insulating material layer is 400 nm.

[0038] Furthermore, the shape of the window is polygonal or circular.

[0039] Further, the diameter or width of the window is 3-5000 μm;

[0040] Furthermore, the material of the first electrode includes any one of a two-dimensional thin film material and silver nanowires, but is not limited thereto.

[0041] Furthermore, the second electrode is a metal electrode.

[0042] Furthermore, the material of the second electrode includes nickel and / or gold, but is not limited thereto.

[0043] Furthermore, the second electrode is disposed around the window;

[0044] Furthermore, the two-dimensional thin film material includes any one of graphene, boron nitride, molybdenum disulfide, and tungsten disulfide with a thickness within 5 nm, but not less than this.

[0045] The embodiment of the present invention further provides an invisible semiconductor device, which includes: an epitaxial layer, a nanorod array disposed on the epitaxial layer, an insulating material layer disposed on the surface of the nanorod array, and a first electrode and a second electrode;

[0046] A window is also provided on the insulating material layer, and at least a partial area of ​​the surface of the nanocolumn array is exposed from the window. The first electrode is a transparent electrode, and the first electrode at least covers the window and is electrically connected to the surface of the nanocolumn array located in the window area. The second electrode is provided in an area outside the window.

[0047] Furthermore, the epitaxial layer is an epitaxial layer having pores or defects.

[0048] Furthermore, the epitaxial layer is a GaN epitaxial layer having pores or defects.

[0049] Furthermore, the total thickness of the epitaxial layer is H1, 1nm≤H1<600nm.

[0050] Furthermore, the nanocolumn array includes a plurality of nanocolumns vertically arranged on the epitaxial layer, and any of the nanocolumns includes a first nanocolumn, a second nanocolumn and a third nanocolumn stacked in sequence from bottom to top.

[0051] Furthermore, at least one of the first nanorod, the second nanorod and the third nanorod is a single-layer or multi-layer structure.

[0052] Furthermore, the first nano-pillar, the second nano-pillar and the third nano-pillar are n-type doped or p-type doped.

[0053] Furthermore, the first nanorod comprises Al 1-m Ga m N nanopillars, 0<m≤1.

[0054] Furthermore, the second nanorod includes In 1-n-x Al n Ga x N or gallium oxide or indium gallium zinc oxide nanorod, 0≤x≤1, 0≤n≤1, 0≤n+x≤1.

[0055] Furthermore, the third nanorod comprises Al 1-z Ga z N nanopillars, 0<z≤1.

[0056] Furthermore, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of the Al component or the content of the In component in the N nanocolumn is uniformly distributed or gradually increases or decreases.

[0057] Furthermore, the height of the first nanocolumn is 100nm-2000nm, the height of the second nanocolumn is 20nm-800nm, and the height of the third nanocolumn is 0nm-800nm.

[0058] Furthermore, the diameter of the single nanocolumn does not exceed 300 nm.

[0059] Furthermore, the material of the insulating material layer includes silicon oxide, but is not limited thereto.

[0060] Furthermore, the thickness of the insulating material layer is 400 nm.

[0061] Furthermore, the shape of the window is polygonal or circular, for example, triangle, rectangle, circle, etc., but not limited thereto.

[0062] Furthermore, the diameter or width of the window is 3-5000 μm.

[0063] Furthermore, the material of the first electrode includes any one of a two-dimensional thin film material and silver nanowires, but is not limited thereto.

[0064] Furthermore, the two-dimensional thin film material includes any one of graphene, boron nitride, molybdenum disulfide, and tungsten disulfide with a thickness within 5 nm, but is not limited thereto.

[0065] Furthermore, the material of the second electrode includes nickel and / or gold, but not limited thereto.

[0066] Furthermore, the second electrode is arranged around the window.

[0067] Furthermore, the epitaxial layer is arranged on a transparent conductive substrate.

[0068] Furthermore, the transparent conductive substrate includes any one of a conductive film, a two-dimensional thin film material, and glass, epoxy resin, and a transparent tape with indium tin oxide or silver nanowires formed on the surface, but is not limited thereto.

[0069] Furthermore, a colloid having conductive, transparent and adhesive properties is formed on the transparent conductive substrate.

[0070] The embodiments of the present invention also provide an invisible semiconductor device obtained by the preparation method or use of the invisible semiconductor device in the field of manufacturing invisible display equipment or invisible detectors.

[0071] Furthermore, the invisible display device includes but is not limited to car windshield navigation, train glass display or smart skin.

[0072] Compared with the prior art, the advantages of the present invention include:

[0073] 1) The embodiment of the present invention provides an invisible semiconductor device with a long service life, and the invisible semiconductor device has a vertical nanocolumn array, which is more conducive to releasing epitaxial stress and improving crystal quality compared to traditional thin film structures; and compared to organic materials, GaN-based materials have a long service life and strong corrosion resistance;

[0074] 2) The embodiment of the present invention provides an invisible semiconductor device with strong practicality: the invisible semiconductor device structure provided by the embodiment of the present invention is directly grown in the epitaxial process without the need for additional catalysts, which reduces the process difficulty; the electrochemical etching and photolithography required in the preparation process are both conventional etching processes, with low precision requirements, which is conducive to improving practicality;

[0075] 3) The embodiment of the present invention provides a cost-controlled invisible semiconductor device: the device epitaxy provided by the embodiment of the present invention is directly grown during the epitaxy process without the need for additional catalysts, which is beneficial to reducing the epitaxy cost; the electrochemical etching and photolithography required for the preparation scheme are both conventional etching processes with low cost; the original substrate after peeling off also facilitates the reuse of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 It is a schematic diagram of a preparation process of a stealth GaN-based semiconductor device provided in a typical implementation case of the present invention;

[0077] Figure 2 It is a schematic diagram of the preparation process of another invisible GaN-based semiconductor device provided in a typical implementation case of the present invention;

[0078] Figure 3 It is a schematic structural diagram of a stealth GaN-based semiconductor device provided in a typical implementation case of the present invention;

[0079] Figure 4 is a schematic diagram of an epitaxial structure of a GaN-based semiconductor device provided in Example 1 of the present invention;

[0080] Figure 5 is a schematic diagram of the epitaxial structure of the device after peeling off provided in Example 1 of the present invention;

[0081] Figure 6 is a schematic diagram of the structure of the epitaxial wafer surface after the first photolithography provided in Example 1 of the present invention;

[0082] Figure 7 This is a schematic diagram of the structure after the second electrode preparation on the surface of the epitaxial wafer provided in Example 1 of the present invention;

[0083] Figure 8 is a schematic diagram of the structure of the epitaxial wafer surface after the second photolithography provided in Example 1 of the present invention;

[0084] Fig. 9 It is a schematic diagram of the structure after the electrode is prepared for the third time on the surface of the epitaxial wafer provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0085] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0086] The embodiment of the present invention further provides an invisible semiconductor device, which includes: an epitaxial layer, a nanorod array disposed on the epitaxial layer, an insulating material layer disposed on the surface of the nanorod array, and a first electrode and a second electrode disposed on the insulating material layer;

[0087] A window is also provided on the insulating material layer, and at least a portion of the nanocolumn array is exposed from the window. The first electrode is a transparent electrode, and the first electrode at least covers the window and is in contact with or connected to the nanocolumn array located in the window area. The second electrode is provided on the first electrode, and the second electrode is located in an area outside the window.

[0088] Specifically, the epitaxial layer is a GaN epitaxial layer with pores or defects, and the total thickness of the epitaxial layer is H1, 1nm≤H1<600nm.

[0089] Specifically, the nanocolumn array includes a plurality of nanocolumns vertically arranged on the epitaxial layer, and any of the nanocolumns includes Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaZnO nanorods and Al 1-z Ga z N nanorods; wherein 0<m≤1, 0≤x≤1, 0≤n≤1, 0≤n+x≤1, 0<z≤1; preferably, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z Any one of the N nanocolumns is a single layer or multilayer structure; preferably, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of the Al component or the content of the In component in the N nanocolumn is uniformly distributed or gradually increases or decreases.

[0090] Specifically, Al1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The N nanorods are n-type doped or p-type doped, and the concentration of n-type doping or p-type doping is 1×10 18 -1×10 24 cm -3 ; The Al 1-m Ga m The height of the N nanocolumns is 100nm-2000nm. 1-n-x Al n Ga x The height of the N or gallium oxide or indium gallium zinc oxide nanorods is 20nm-800nm. 1-z Ga z The height of the N nano-pillars is 0 nm-800 nm; the diameter of the single nano-pillar does not exceed 300 nm.

[0091] Specifically, the material of the insulating material layer includes silicon oxide, and the thickness of the insulating material layer is 400nm; preferably, the shape of the window is polygonal or circular, for example, a triangle, a rectangle, a circle, etc., preferably, the diameter or width of the window is 3-5000μm, preferably, the material of the first electrode includes any one of a two-dimensional thin film material and silver nanowires, preferably, the two-dimensional thin film material includes any one of graphene, boron nitride, molybdenum disulfide, and tungsten disulfide with a thickness of less than 5nm, preferably, the material of the second electrode includes nickel and / or gold, etc.

[0092] Compared with traditional planar films, the invisible semiconductor device provided by the embodiment of the present invention has a nanocolumn array, which can not only improve the crystal quality but also improve the transparency of the device; in addition, the peeling process is also conducive to the reuse of the epitaxial substrate and reduce costs; and the invisible semiconductor device provided by the embodiment of the present invention is highly practical and can provide technical support for the development and wide application of invisible semiconductor devices.

[0093] See also Figure 1 , an embodiment of the present invention provides a method for preparing an invisible semiconductor device, which comprises:

[0094] S1, growing a sacrificial layer on the first surface of the epitaxial substrate, the total thickness of the sacrificial layer is H0, 1nm≤H0<100nm;

[0095] S2, growing a GaN epitaxial layer with pores or defects on the sacrificial layer, with a total thickness of H1, 1nm≤H1<600nm;

[0096] S3, growing a nanocolumn array having a semiconductor device structure on the GaN epitaxial layer; preparing an etching electrode on a second surface of the epitaxial substrate opposite to the first surface, and connecting the etching electrode to the sacrificial layer, and then removing the sacrificial layer by electrochemical etching to peel off the epitaxial structure above the sacrificial layer as a whole, and transferring it to the surface of the transparent conductive substrate;

[0097] S4. Making an insulating material layer on the nanocolumn array that at least covers the nanocolumn array, and processing a pattern array including a plurality of pattern windows on the insulating material layer through a first photolithography process, wherein the area within the pattern window needs to absorb or emit photons, the nanocolumn array within the pattern window is exposed to the air and is not covered by the insulating material layer, while the area outside the pattern window is covered by an insulating material layer, and the insulating material layer has no gaps;

[0098] S5, preparing or transferring a layer of electrode with high transparency as a first electrode on the insulating material layer, and electrically connecting the first electrode to the nanorod array exposed from the pattern window;

[0099] S6. Processing a plurality of grooves on the first electrode through a second photolithography process to separate the plurality of pattern windows, wherein the depth of the grooves extends all the way to the transparent conductive substrate, the separated pattern window regions are not conductive, and each pattern window is surrounded by a certain area of ​​insulating material;

[0100] S7. Prepare a metal electrode as a second electrode in the area corresponding to the surrounding area of ​​each pattern window on the first electrode, thereby forming the invisible semiconductor device, wherein the divided pattern window areas are still not conductive and the pattern window areas have high transparency.

[0101] See also Figure 2 In some specific implementations, a method for preparing an invisible semiconductor device may further include:

[0102] S1, growing a sacrificial layer on the first surface of the epitaxial substrate, the total thickness of the sacrificial layer is H0, 1nm≤H0<100nm;

[0103] S2, growing a GaN epitaxial layer with pores or defects on the sacrificial layer, with a total thickness of H1, 1nm≤H1<600nm;

[0104] S3, growing a nanorod array having a semiconductor device structure on the GaN epitaxial layer;

[0105] S4. Making an insulating material layer on the nanocolumn array that at least covers the nanocolumn array, and processing a pattern array including a plurality of pattern windows on the insulating material layer through a first photolithography process, wherein the area within the pattern window needs to absorb or emit photons, the nanocolumn array within the pattern window is exposed to the air and is not covered by the insulating material layer, while the area outside the pattern window is covered by an insulating material layer, and the insulating material layer has no gaps;

[0106] S5, preparing or transferring a layer of electrode with high transparency as a first electrode on the insulating material layer, and electrically connecting the first electrode to the nanorod array exposed from the pattern window;

[0107] S6. Processing a plurality of grooves on the first electrode through a second photolithography process to separate the plurality of pattern windows, wherein the depth of the grooves extends all the way to the transparent conductive substrate, the separated pattern window regions are not conductive, and each pattern window is surrounded by a certain area of ​​insulating material;

[0108] S7, preparing a metal electrode as a second electrode in an area corresponding to the surrounding area of ​​each pattern window on the first electrode, thereby forming the semiconductor device, wherein the divided pattern window areas are still not conductive and the pattern window areas have high transparency;

[0109] An etching electrode is prepared on the second surface of the epitaxial substrate opposite to the first surface, and the etching electrode is connected to the sacrificial layer. The sacrificial layer is then removed by electrochemical etching to peel off the semiconductor device above the sacrificial layer as a whole and transfer it to the surface of the transparent conductive substrate to form a final invisible semiconductor device.

[0110] Of course, it should be noted that the step of destroying the sacrificial layer and transferring the epitaxial structure above the sacrificial layer can be performed after forming the nanocolumn array, before forming the invisible semiconductor device, or at any time. Those skilled in the art can also transfer the epitaxial structure according to the specific circumstances.

[0111] Of course, those skilled in the art may also destroy the sacrificial layer by directly peeling it off with mechanical force, and then transfer the epitaxial structure or the device structure of the invisible semiconductor device on the sacrificial layer.

[0112] Specifically, the process of removing the sacrificial layer by electrochemical etching specifically includes: preparing an electrode (for example, an In ball) that is conductive to the sacrificial layer on the second surface of the epitaxial substrate opposite to the first surface, and covering the electrode with epoxy resin to prevent the electrode from being conductive to the electrochemical solution; then performing electrochemical etching in an electrochemical solution (for example, a KOH solution) to etch away the sacrificial layer, and the voltage used in the electrochemical etching is U, 0.2V≤U≤600V.

[0113] Specifically, the transparent conductive substrate includes a conductive film, a two-dimensional thin film material, and glass, epoxy resin, and transparent tape with a layer of indium tin oxide (ITO) or silver nanowires on the surface; before transferring the nanocolumn array, a layer of colloid with conductive, transparent and sticky properties can also be coated on the transparent conductive substrate to better fix the transferred nanocolumn array.

[0114] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention may be implemented in many different forms, and the present invention should not be construed as being limited to the specific embodiments set forth herein. On the contrary, these embodiments are provided to explain the principles of the present invention and their practical applications, so that other persons skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for specific intended applications. In the accompanying drawings, for the sake of clarity, the shapes and sizes of the elements may be exaggerated, and the same reference numerals will always be used to represent the same or similar elements.

[0115] It will be understood that although the terms "first", "second", etc. may be used herein to describe various structures and processes, these structures should not be limited by these terms, which are only used to distinguish one structure or process from another.

[0116] See also Figure 3 A typical embodiment of the present invention provides an invisible semiconductor device, which includes: a GaN epitaxial layer 11, a nanorod array disposed on the GaN epitaxial layer 11, a silicon oxide layer 20 disposed on the surface of the nanorod array, a graphene electrode 30 disposed on the silicon oxide layer 20, and a Ni / Au electrode 50 disposed on the graphene electrode 30;

[0117] In which, a window is also provided on the silicon oxide layer 20, and at least a partial area of ​​the surface of the nanocolumn array is exposed from the window. The graphene electrode 30 is a highly transparent electrode, and the graphene electrode 30 at least covers the window and is electrically connected to the nanocolumn array located in the window area. The Ni / Au electrode 50 is arranged on the graphene electrode 30 and surrounds the peripheral area outside the window.

[0118] Specifically, the GaN epitaxial layer 11 is a GaN epitaxial layer with pores or defects, and the total thickness of the GaN epitaxial layer 11 is H1, 1nm≤H1<600nm.

[0119] Specifically, the nanocolumn array includes a plurality of nanocolumns vertically arranged on the GaN epitaxial layer 11, and any of the nanocolumns includes Al 1-m Ga m N nanorods 12, In 1-n-xAl n Ga x N or gallium oxide or indium gallium zinc oxide nanorods 13 and Al 1-z Ga z N nanorods 14; wherein 0<m≤1, 0≤x≤1, 0≤n≤1, 0≤n+x≤1, 0<z≤1, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of Al component or In component in the N nanocolumn is uniformly distributed or increases or decreases gradually; 1-m Ga m The height of the N nanorod 12 is 100nm-2000nm. 1-n-x Al n Ga x The height of the N or gallium oxide or indium gallium zinc oxide nanorod 13 is 20nm-800nm. 1-z Ga z The height of the N nano-pillar 14 is 0 nm-800 nm; the diameter of a single nano-pillar does not exceed 300 nm.

[0120] The present invention proposes a method for preparing an invisible semiconductor device. The above-mentioned preparation method of the present invention will be described below through specific embodiments, but the following embodiments are only specific examples of the present invention and do not limit all of them.

[0121] Example 1

[0122] 1) First, place the silicon substrate in a molecular beam epitaxy (MBE) growth chamber for epitaxial growth. Figure 4 , specifically including the following steps:

[0123] In the first step, an AlN sacrificial layer 10 with a thickness of about 5 nm is grown on the front side of the n-type doped silicon (Si) substrate;

[0124] In the second step, a Si-doped GaN epitaxial layer 11 with a thickness of 20 nm and a doping concentration of 1×10 22 cm -3 ;

[0125] In the third step, a layer of Si-doped GaN nanorods 12 with a height of about 500 nm and a doping concentration of 1×10 22 cm -3 ;

[0126] The fourth step is to grow a 50 nm thick In layer on the GaN nanorod 12. 0.3 Ga 0.7 N nanopillars 13.

[0127] Step 5: In 0.3 Ga 0.7 A 10 nm thick Al layer is grown on the N nanorod 13. 0.2 Ga 0.8 N nanorods 14, and then on Al 0.2 Ga 0.8 A layer of Mg-doped GaN nanorod 15 with a thickness of 100 nm is grown on the N nanorod 14, and the doping concentration is 1×10 21 cm -3 ;

[0128] That is to say, the Al of this embodiment 1-b Ga b In N material, b is 0, and in Al 1-m Ga m In the N nanocolumn, m is 1. 1-n-x In the AlnGaxN nanocolumn, x is 0.7 and n is 0. The In component in the actual sample will fluctuate and be unevenly distributed. 1-z GazN nanorods have a two-layer structure, close to In 1-x Ga x The z value of the layer with N nanopillars is 0.8 and the thickness is 10nm, while the z value of the other layer is 1 and the thickness is 100nm;

[0129] 2) An electrode for etching is prepared on the back of the Si substrate. The electrode material for etching is In ball, and the electrode is covered with epoxy resin to prevent the electrode from being conductive with the electrochemical solution. Then, electrochemical etching is performed in a KOH solution at a voltage of about 5 V to etch away the AlN sacrificial layer 10. After peeling off the Si substrate, an epitaxial structure including an epitaxial layer and a nanocolumn array on the AlN sacrificial layer 10 is obtained, and the epitaxial structure is transferred to a glass sheet covered with an indium tin oxide (ITO) layer 16 on one side, wherein the GaN epitaxial layer 11 is arranged on the ITO layer 16. The device structure formed is as follows: Figure 5 As shown;

[0130] 3) A 400nm SiO2 layer 20 is formed on the surface of the nanorod array, and a pattern array including a plurality of square patterns 21 is prepared by photolithography. The side length of a single square pattern is 300μm. The square pattern is not covered with material, while the area outside the square pattern is covered with a 400nm SiO2 layer 20. The upper surface of the SiO2 layer is connected together without gaps. The obtained device structure is as follows: Figure 6As shown;

[0131] 4) A layer of graphene 30 is transferred onto the surface of the SiO2 layer 20 as a first electrode, and the graphene layer 30 is electrically contacted or connected to the nanorod array from the square pattern 21 region, and the obtained device structure is as follows: Figure 7 As shown;

[0132] 5) Using photolithography to prepare elongated grooves 40 in the graphene layer 30, the grooves are extended to the ITO layer or the glass layer to separate the multiple square patterns on the SiO2 layer 20, and the device structure obtained is as follows: Figure 8 As shown;

[0133] 6) Ni / Au 50 is prepared as a second electrode in the area corresponding to the four sides of each square pattern on the graphene layer 30. The Ni / Au electrode 50 can be rectangular with a length of 500 μm and a width of 200 μm, such as Fig. 9 The device can be used as a light-emitting device. At the same time, the device can also be peeled off from the ITO layer 16. The peeling process can be placed in an ethanol solution, and then the ITO layer 16 is separated from the epitaxial layer 11. The device structure obtained is as follows Figure 3 As shown;

[0134] 7) If Figure 3 As shown, a thin gold wire (ie, external lead) 60 may be connected to the Ni / Au electrode 50 to facilitate connection to a power source or circuit.

[0135] Among them, the GaN epitaxial layer 11 not only serves as the connection layer of the nanocolumn array, but also serves as the current connection and expansion layer. In this way, the transmittance can be significantly improved after the peeling substrate and the ITO layer are removed. The transmittance of an invisible semiconductor device provided in an embodiment of the present invention in an area without a SiO2 layer 20 (i.e., the aforementioned window area) is greater than 90% in the visible light range (380nm-400nm), and the area can be considered to be invisible.

[0136] Example 2

[0137] This embodiment is basically the same as Embodiment 1, except that In 1-n-x Al n Ga x There are 6 In in N nanopillars 0.25 Ga 0.75 N(15nm) / GaN(5nm) superlattice structure, namely In 0.25 Ga 0.75N (15nm) and GaN (5nm) are arranged alternately, with a total of 6 periods, in which the values ​​of x in two adjacent layers are 0.75 and 1 respectively, and the values ​​of n are all 0. In addition, there is a layer of hydrogel about 1μm thick on the surface of the transferred transparent conductive substrate, which is used to fix the nanocolumns. The device can be used as a light-emitting device.

[0138] Example 3

[0139] This embodiment is basically the same as embodiment 1, except that 50 nm thick gallium oxide (Ga2O3) nanorods are used instead of In 1-n-x Al n Ga x N nanorods, and Al 1-z Ga z The thickness of the N nanocolumn is 0, and the epitaxial equipment is a metal organic chemical vapor deposition (MOCVD) equipment. The device can be used as an ultraviolet detector.

[0140] Example 4

[0141] This embodiment is basically the same as the embodiment 1, except that the pattern formed on the silicon oxide layer 20 in this embodiment is circular with a diameter of 500 μm; and the material used for the first electrode is silver nanowire.

[0142] Example 5

[0143] This embodiment is basically the same as Embodiment 1, except that In 1-n-x Al n Ga x There are 5 Al 0.2 Ga 0.8 N(20nm) / GaN(6nm) superlattice structure, namely Al 0.2 Ga 0.8 N (20nm) and GaN (6nm) are alternately arranged, with a total of 5 periods, where the values ​​of x in two adjacent layers are 0.8 and 1, and the values ​​of n are 0.2 and 0, respectively; Al 1-z Ga z There are 5 layers in the N nanocolumn, all of which are p-type doped. 1-x Ga x The calculation starts from the first layer of the N nanocolumn. The first layer is 5nm thick AlN, and the z value is 0. The second layer is 6nm thick Al 0.1 Ga 0.9 N, z is 0.9, the third layer is 4nm thick AlN, z is 0, and the fourth layer is 50nm thick Al 0.15 Ga 0.85 N, z takes the value of 0.85, the 5th layer is 30nm thick GaN, and z takes the value of 1.

[0144] Example 6

[0145] This embodiment is basically the same as Embodiment 1. The difference is that the sacrificial layer Al in this embodiment 1-b Ga b N has 2 layers, the first layer is an 8nm thick AlN layer, b value is 0, and the second layer is a 5nm thick Al 0.15 Ga 0.85 N layer, b value is 0.85, and 60nm thick indium gallium zinc oxide nanorods are used instead of In 1-n-x Al n Ga x N nanopillars.

[0146] Example 7

[0147] This embodiment is basically the same as embodiment 1, except that the Al 1-m Ga m The N nanocolumn has two layers. The first layer is a 200nm thick GaN layer with an m value of 1. The second layer is a 250nm thick gradient layer with an m value gradually varying from 1 to 0.75. The transparent conductive substrate used after the nanocolumn is peeled off is a transparent tape covered with multiple layers of BN (commonly known as boron nitride) two-dimensional material.

[0148] Example 8

[0149] 1) First, a silicon substrate is placed in a molecular beam epitaxial growth chamber for epitaxial growth. The device epitaxial structure is the same as in Example 1. Figure 4 ;

[0150] 2) A 500nm SiO2 layer 20 is formed on the surface of the nanorod array, and a pattern array including a plurality of square patterns 21 is prepared by photolithography, wherein the side length of a single square pattern is 300μm, the square pattern is not covered with material, and the area outside the square pattern is covered with a 400nm SiO2 layer 20, and the upper surface of the SiO2 layer is connected together without gaps, such as Figure 6 As shown;

[0151] 3) A layer of graphene 30 is transferred onto the surface of the SiO2 layer 20 as a first electrode, and the graphene layer 30 is electrically contacted or connected to the nanorod array from the square pattern 21 area, such as Figure 7 As shown;

[0152] 4) Using photolithography technology to prepare elongated grooves 40 in the graphene layer 30, the grooves are extended to the ITO layer or the glass layer to separate the multiple square patterns on the SiO2 layer 20, such as Figure 8 As shown;

[0153] 5) A Ni / Au electrode 50 is prepared as a second electrode in the area corresponding to the four sides of each square pattern on the graphene layer 30. The Ni / Au electrode 50 can be rectangular with a length of 500 μm and a width of 200 μm, such as Fig. 9 , thereby forming the invisible semiconductor device;

[0154] 6) An etching electrode is prepared on the back side of the Si substrate. The etching electrode material is In balls, and the etching electrode is covered with epoxy resin to prevent the etching electrode from being conductive to the electrochemical solution. Then, electrochemical etching is performed in a NaOH, KOH or HNO3 solution at a voltage of about 20 V to etch away the AlN sacrificial layer 10, so as to separate the Si substrate from the device structure of the invisible semiconductor device on the AlN sacrificial layer 10, and the device structure is transferred to a transparent resin material (such as PET), wherein the GaN epitaxial layer 11 in the device structure serves not only as a connection layer for the nanocolumn array, but also as a current connection and expansion layer.

[0155] After the semiconductor device is manufactured, the stripping and transfer steps are performed to form the final invisible semiconductor device, thereby reducing the difficulty of the device process. In an invisible semiconductor device provided in an embodiment of the present invention, if the minimum value of the transmittance in the visible light range (380nm-400nm) in the area without the SiO2 layer 20 (i.e., the aforementioned window area) is greater than 90%, then the area can be considered invisible; if it is between 50%-90%, then the area can be considered semi-invisible.

[0156] Compared with the prior art, the embodiment of the present invention provides an invisible semiconductor device with a long service life, and the invisible semiconductor device has a vertical nanocolumn array, which is more conducive to releasing epitaxial stress and improving crystal quality compared with traditional thin film structures; and compared with organic materials, GaN-based materials have a long service life and strong corrosion resistance.

[0157] The embodiments of the present invention provide an invisible semiconductor device with strong practicality: the invisible semiconductor device structure provided by the embodiments of the present invention is directly grown in the epitaxial process without the need for additional catalysts, thereby reducing the process difficulty; the electrochemical etching and photolithography required in the preparation process are both conventional etching processes with low precision requirements, which is conducive to improving practicality.

[0158] The embodiment of the present invention provides a cost-controlled invisible semiconductor device: the device epitaxy provided by the embodiment of the present invention is directly grown during the epitaxy process without the need for additional catalysts, which is beneficial to reducing the epitaxy cost; the electrochemical etching and photolithography required for the preparation scheme are both conventional etching processes with low cost; the original substrate after peeling off also facilitates the reuse of the substrate.

[0159] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an invisible semiconductor device, characterized in that include: A sacrificial layer, an epitaxial layer and a nanocolumn array are sequentially formed on an epitaxial substrate, wherein the epitaxial layer and the nanocolumn array both contain III-V semiconductor materials, the epitaxial layer is a GaN epitaxial layer with pores or defects, and the density of the pores or defects in the epitaxial layer is greater than 1×10 13 m -2 The nanocolumn array includes a plurality of nanocolumns, any of which includes a first nanocolumn, a second nanocolumn and a third nanocolumn sequentially formed in a direction away from the epitaxial layer, and the first nanocolumn includes Al 1-m Ga m N nanorods, 0<m≤1, the second nanorods include In 1-n-x Al n Ga x N or gallium oxide or indium gallium zinc oxide nanorods, 0≤x≤1, 0≤n≤1, 0≤n+x≤1, the third nanorods include Al 1-z Ga z N nanorods, 0<z≤1, the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of Al component or In component in the N nanocolumns is uniformly distributed or gradually increases or decreases; Destroying the sacrificial layer to peel off the epitaxial structure or invisible semiconductor device on the sacrificial layer as a whole, transferring the peeled epitaxial structure or invisible semiconductor device, and placing the epitaxial layer directly on the transparent conductive substrate; Disposing an insulating material layer that at least covers the nanorod array, and processing at least one window on the insulating material layer so that at least a portion of the nanorod array is exposed from the window; A first electrode is arranged at the window of the insulating material layer, so that the first electrode is electrically connected to the nanocolumn array exposed from the window, the first electrode is a transparent electrode, and a second electrode is arranged on the area of ​​the insulating material layer except the window, thereby forming an invisible semiconductor device.

2. The preparation method according to claim 1, characterized in that: include: The epitaxial structure or invisible semiconductor device is formed on the first surface of the epitaxial substrate, and an electrode connected to the sacrificial layer is formed on the second surface of the epitaxial substrate opposite to the first surface, and then the sacrificial layer is removed by electrochemical etching.

3. The preparation method according to claim 1, characterized in that: At least one of the first nanorod, the second nanorod and the third nanorod is a single-layer or multi-layer structure.

4. The preparation method according to claim 1, characterized in that: The first nanocolumn, the second nanocolumn and the third nanocolumn are n-type doped or p-type doped, and the n-type or p-type doping concentration is 1×10 18 -1×10 24 cm -3 .

5. The preparation method according to claim 1, characterized in that: The height of the first nanocolumn is 100 nm-2000 nm, the height of the second nanocolumn is 20 nm-800 nm, and the height of the third nanocolumn is 0 nm-800 nm.

6. The preparation method according to claim 1, characterized in that: The total thickness of the epitaxial layer is H1, 1nm≤H1<600nm.

7. The preparation method according to claim 1, characterized in that: The sacrificial layer includes a single layer or multiple layers of Al 1-b Ga b N layers, where 0≤b<1, and the b values ​​corresponding to two adjacent layers are different.

8. The preparation method according to claim 1, characterized in that: The thickness of the sacrificial layer is H0, 1nm≤H0<100nm.

9. The preparation method according to claim 1, characterized in that: The epitaxial substrate includes any one or a combination of two or more of a silicon wafer, a sapphire substrate, a GaN self-supporting substrate, a silicon carbide substrate, a diamond substrate, a metal substrate, and a substrate covered with a two-dimensional thin film material.

10. The preparation method according to claim 1, characterized in that: The transparent conductive substrate comprises a conductive film, a two-dimensional thin film material, and any one of glass, epoxy resin, and transparent tape with indium tin oxide or silver nanowires formed on the surface.

11. The preparation method according to claim 1, characterized in that: A colloid with conductive, transparent and adhesive properties is also formed on the transparent conductive substrate.

12. The preparation method according to claim 1, characterized in that: The insulating material layer is made of silicon oxide.

13. The preparation method according to claim 1, characterized in that: The thickness of the insulating material layer is 400 nm.

14. The preparation method according to claim 1, characterized in that: The shape of the window is polygonal or circular.

15. The preparation method according to claim 1, characterized in that: The diameter or width of the window is 3-5000 μm.

16. The preparation method according to claim 1, characterized in that: The material of the first electrode includes any one of a two-dimensional thin film material and a silver nanowire.

17. The preparation method according to claim 1, characterized in that: The second electrode is a metal electrode.

18. The preparation method according to claim 1, characterized in that: The material of the second electrode includes nickel and / or gold.

19. The preparation method according to claim 1, characterized in that: The second electrode is arranged around the window.

20. The preparation method according to claim 16, characterized in that: The two-dimensional thin film material includes any one of graphene, boron nitride, molybdenum disulfide and tungsten disulfide with a thickness within 5 nm.

21. An invisible semiconductor device, characterized in that include: An epitaxial layer, a nanorod array disposed on the epitaxial layer, an insulating material layer disposed on a surface of the nanorod array, and a first electrode and a second electrode; The epitaxial layer is a GaN epitaxial layer with pores or defects, and the density of the pores or defects in the epitaxial layer is greater than 1×10 13 m -2 The nanocolumn array includes a plurality of nanocolumns vertically arranged on the epitaxial layer, and any of the nanocolumns includes a first nanocolumn, a second nanocolumn and a third nanocolumn stacked in sequence from bottom to top, and the first nanocolumn includes Al 1-m Ga m N nanorods, 0<m≤1; the second nanorods include In 1-n-x Al n Ga x N or gallium oxide or indium gallium zinc oxide nanorods, 0≤x≤1, 0≤n≤1, 0≤n+x≤1; the third nanorods include Al 1-z Ga z N nanorods, 0<z≤1; the Al 1-m Ga m N nanorods, In 1-n-x Al n Ga x N or GaO or InGaO Zn nanorods, Al 1-z Ga z The content of Al component or In component in the N nanocolumns is uniformly distributed or gradually increases or decreases; A window is also provided on the insulating material layer, and at least a partial area of ​​the surface of the nanocolumn array is exposed from the window. The first electrode is a transparent electrode, and the first electrode at least covers the window and is electrically connected to the nanocolumn array. The second electrode is provided in an area outside the window.

22. The invisible semiconductor device according to claim 21, characterized in that: The total thickness of the epitaxial layer is H1, 1nm≤H1<600nm.

23. The invisible semiconductor device according to claim 21, characterized in that: At least one of the first nanorod, the second nanorod and the third nanorod is a single-layer or multi-layer structure.

24. The invisible semiconductor device according to claim 21, characterized in that: The first nano-rod, the second nano-rod and the third nano-rod are n-type doped or p-type doped.

25. The invisible semiconductor device according to claim 21, characterized in that: The n-type or p-type doping concentration is 1×10 18 -1×10 24 cm -3 .

26. The invisible semiconductor device according to claim 21, wherein: The height of the first nanocolumn is 100 nm-2000 nm, the height of the second nanocolumn is 20 nm-800 nm, and the height of the third nanocolumn is 0 nm-800 nm.

27. The invisible semiconductor device according to claim 21, characterized in that: The insulating material layer is made of silicon oxide.

28. The invisible semiconductor device according to claim 21, characterized in that: The thickness of the insulating material layer is 400 nm.

29. The invisible semiconductor device according to claim 21, characterized in that: The shape of the window is polygonal or circular.

30. The invisible semiconductor device according to claim 21, characterized in that: The diameter or width of the window is 3-5000 μm.

31. The invisible semiconductor device according to claim 21, characterized in that: The material of the first electrode includes any one of a two-dimensional thin film material and a silver nanowire.

32. The invisible semiconductor device according to claim 31, characterized in that: The two-dimensional thin film material includes any one of graphene, boron nitride, molybdenum disulfide and tungsten disulfide with a thickness within 5 nm.

33. The invisible semiconductor device according to claim 21, characterized in that: The material of the second electrode includes nickel and / or gold.

34. The invisible semiconductor device according to claim 21, characterized in that: The second electrode is arranged around the window.

35. The invisible semiconductor device according to claim 21, characterized in that: The epitaxial layer is disposed on a transparent conductive substrate.

36. The invisible semiconductor device according to claim 35, characterized in that: The transparent conductive substrate comprises a conductive film, a two-dimensional thin film material, and any one of glass, epoxy resin, and transparent tape with indium tin oxide or silver nanowires formed on the surface.

37. The invisible semiconductor device according to claim 35, characterized in that: A colloid with conductive, transparent and adhesive properties is also formed on the transparent conductive substrate.

38. Use of the invisible semiconductor device obtained by the preparation method described in any one of claims 1 to 20 or the invisible semiconductor device described in any one of claims 21 to 37 in the field of making invisible display devices or invisible detectors, wherein the invisible display devices include car windshield navigation, train glass display or smart skin.

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