A method for manufacturing shielded gate trench MOSFET

Abstract

The present invention discloses a method for manufacturing a shielded gate trench MOSFET. The dielectric layer of the manufactured shielded gate MOSFET below the first polysilicon includes a first oxide layer, a first silicon nitride and a second silicon nitride, and the dielectric layer on the side of the first polysilicon includes a first oxide layer and a second silicon nitride. That is to say, the thickness of the dielectric layer below the shielding gate is greater than the thickness of the dielectric layer on the side, so the electric field strength at the bottom of the trench can be weakened, avoiding the problem of a stronger electric field at the bottom of the trench existing in the prior art. Therefore, the present invention improves the breakdown voltage of the MOSFET.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a shielded gate trench MOSFET. Background Art

[0002] MOSFET chip is a discrete device that belongs to the category of semiconductor power devices. It belongs to the same semiconductor chip field as integrated circuits. Integrated circuits integrate thousands of transistors into the same chip through process methods, while MOSFET is a single transistor composed of thousands of cells of the same structure in parallel.

[0003] The key dynamic parameters of MOSFET include parasitic capacitance, switching time, gate parasitic resistance, etc., among which parasitic capacitance includes gate-source parasitic capacitance Cgs, gate-drain parasitic capacitance Cgd, and drain-source parasitic capacitance Cds. From the application point of view, the parasitic capacitance of MOSFET is summarized as input capacitance Ciss = Cgs + Cgd, output capacitance Coss = Cds + Cdg, and reverse transfer capacitance Crss = Cdg, among which reverse transfer capacitance Crss is also called Miller capacitance. Input capacitance and Miller capacitance play a leading role in the switching loss of MOSFET. The larger the chip area, the smaller the on-resistance of the chip, but the larger the area of ​​parasitic capacitance, the larger the input capacitance and Miller capacitance; under the premise of ensuring the established on-resistance, it is the responsibility of chip engineers to minimize the input capacitance and Miller capacitance of MOSFET.

[0004] In the shielded gate trench MOSFET structure, there are two layers of polysilicon. The second layer of polysilicon is the polysilicon gate of the MOSFET, and the first layer of polysilicon is the shielding gate, which is buried under the polysilicon gate. The top, sides and bottom of the shielding gate are surrounded by dielectric layers. The dielectric layer above the shielding gate and below the polysilicon gate is called the "polysilicon interlayer dielectric". The shielding gate is not brought out as an independent port, but is connected to the source area (source) by metal wiring inside the chip.

[0005] The shielded gate trench MOSFET uses the charge balance principle and combines it with deep trench technology to make the epitaxial layer between adjacent trenches depleted laterally and share the higher voltage vertically. Therefore, the potential at the bottom of the trench is higher and a very strong electric field is gathered at the bottom of the trench. In the traditional method, the dielectric layer at the bottom of the trench and the sidewall of the trench is formed simultaneously by high-temperature oxidation. However, the crystal orientation of the silicon atoms at the bottom of the trench is different from that of the sidewall of the trench. Therefore, the thickness of the dielectric layer grown at the bottom of the trench is smaller than that of the sidewall of the trench, and the bottom of the trench is arc-shaped. These conditions make the electric field under the shield gate (i.e., the bottom of the trench) stronger, resulting in a lower breakdown voltage of the MOSFET. Summary of the invention

[0006] The invention provides a method for manufacturing a shielded gate trench MOSFET, aiming to solve the problem that the dielectric layer at the bottom of the trench of the existing MOSFET chip is too thin and the electric field at the bottom of the trench is too strong, resulting in a low breakdown voltage of the MOSFET.

[0007] According to an embodiment of the present application, a method for manufacturing a shielded gate trench MOSFET is provided, comprising the following steps:

[0008] Step S1: growing an epitaxial layer on the surface of the substrate, forming a first trench and a second trench in the epitaxial layer, and forming a first oxide layer on the surfaces of the first trench and the second trench;

[0009] Step S2: generating a first silicon nitride on the surface of the first oxide layer, etching the first silicon nitride, and retaining a portion of the first silicon nitride at the bottom of the first trench and the second trench;

[0010] Step S3: depositing a second silicon nitride on the first oxide layer and the first silicon nitride surface, depositing a first polysilicon on the second silicon nitride surface, and etching the first polysilicon so that the height of the first polysilicon is lower than the first trench and the second trench;

[0011] Step S4: etching the first polysilicon in the first trench so that the height of the first polysilicon in the first trench is lower than the height of the first polysilicon in the second trench;

[0012] Step S5, depositing a second oxide layer in the first trench and the second trench, grinding the second oxide layer so that the height of the second oxide layer is flush with the second silicon nitride, and etching a portion of the second oxide layer in the first trench;

[0013] Step S6: etching the second silicon nitride so that the height of the second silicon nitride in the first trench is flush with the second oxide layer, and etching the first oxide layer so that the first oxide layer in the first trench is flush with the second silicon nitride;

[0014] Step S7: growing a third oxide layer on the sidewalls of the first trench and the second trench, the third oxide layer being connected to one end of the first oxide layer, depositing second polysilicon, etching a portion of the second polysilicon in the first trench, and etching away all of the second polysilicon in the second trench;

[0015] Step S8: forming a body region and a source region in sequence, depositing a dielectric layer, drilling holes at the positions of the first trench and the second trench to obtain a first contact hole and a second contact hole, and drilling holes between adjacent first trenches to obtain a third contact hole.

[0016] Preferably, the depth of the first groove and the second groove is 1.5-15 microns.

[0017] Preferably, the thickness of the first oxide layer is 30-500 nanometers, and the thickness of the second silicon nitride layer is 30-500 nanometers.

[0018] Preferably, in the above step S2, after etching the first silicon nitride, the longitudinal thickness of the first silicon nitride in the first trench and the second trench is 0.2-1 micrometer.

[0019] Preferably, in the above step S3, after etching the first polysilicon, the top surface of the first polysilicon in the first trench and the second trench is 0-0.5 micrometers lower than the top surface of the second silicon nitride.

[0020] Preferably, in the above step S4, the first polysilicon in the first trench is 1-2 microns lower than the upper surface of the epitaxial layer.

[0021] Preferably, in step S5, the longitudinal thickness of the second oxide layer retained in the first trench is 0.2-0.8 micrometers.

[0022] Preferably, the above step S6 specifically includes:

[0023] Step S61: using an over-etching process to etch the second silicon nitride on the top of the second oxide layer so that the second silicon nitride is flush with the second oxide layer;

[0024] Step S62: Based on the isotropy of the etching process, the second silicon nitride forms a first recessed area on both sides of the second oxide layer;

[0025] Step S63: using an over-etching process to etch the first oxide layer on the top of the second silicon nitride, so that the first oxide layer is flush with the second silicon nitride, and the second oxide layer is etched away partially at the same time;

[0026] Step S64: Based on the isotropy of the etching process, the first oxide layer forms second recessed areas on both sides of the second silicon nitride.

[0027] Preferably, the type of the MOSFET is the same as the doping type of the second polysilicon.

[0028] Preferably, in step S8, the first contact hole passes through the dielectric layer to the second polysilicon, the second contact hole passes through the dielectric layer, the second oxide layer to the first polysilicon in sequence, and the third contact hole passes through the dielectric layer, the third oxide layer, the source region to the body region in sequence.

[0029] Compared with the prior art, the method for manufacturing the shielded gate trench MOSFET provided by the present invention has the following beneficial effects:

[0030] 1. The shielded gate trench MOSFET manufactured by the method of this case has a dielectric layer under the shielding gate including a first oxide layer, a first silicon nitride and a second silicon nitride, and a dielectric layer on the side of the shielding gate including a first oxide layer and a second silicon nitride. That is to say, the thickness of the dielectric layer under the shielding gate is thicker than the thickness of the dielectric layer on the side, so the electric field strength at the bottom of the trench can be weakened, avoiding the problem of a stronger electric field at the bottom of the trench in the prior art. Therefore, this case improves the breakdown voltage of the MOSFET.

[0031] 2. A dielectric layer (second oxide layer) deposited by high-density plasma chemical vapor deposition is used as the polysilicon interlayer dielectric, and silicon nitride (second silicon nitride) is used as a stop layer for chemical mechanical polishing and a barrier layer for oxide layer corrosion. The formed polysilicon interlayer dielectric (second oxide layer) has a better isolation effect on the shielding gate (first polysilicon) and the polysilicon gate (second polysilicon), which can reduce the leakage between the shielding gate and the polysilicon gate and improve the performance of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0033] Figure 1 It is a flow chart of a method for manufacturing a shielded gate trench MOSFET provided by a first embodiment of the present invention.

[0034] Figure 2 It is a flow chart of step S6 in the method for manufacturing the shielded gate trench MOSFET provided by the first embodiment of the present invention.

[0035] Figure 3 It is a schematic diagram of the structure of growing an epitaxial layer on the substrate surface.

[0036] Figure 4 It is a schematic diagram of the structure of forming a first trench and a second trench and growing a first oxide layer.

[0037] Figure 5 It is a schematic diagram of the structure of growing the first silicon nitride on the surface of the first oxide layer.

[0038] Figure 6 It is a schematic diagram of the structure of removing the first silicon nitride and retaining the first silicon nitride at the bottom of the trench.

[0039] Figure 7 It is a schematic diagram of the structure of growing a second silicon nitride on the surface of a first silicon nitride and a first oxide layer.

[0040] Figure 8 It is a schematic diagram of the structure for depositing the first polysilicon.

[0041] Fig. 9 It is a schematic diagram of the structure of etching part of the first polysilicon.

[0042] Fig.10 It is a schematic diagram of the structure of etching the first polysilicon in the first trench.

[0043] Fig.11 It is a schematic diagram of the structure for growing the second oxide layer.

[0044] Fig.12 This is a schematic diagram of the structure after grinding the second oxide layer.

[0045] Fig.13 It is a schematic diagram of the structure of etching part of the second oxide layer in the first trench.

[0046] Fig.14 It is a schematic diagram of the structure of etching the second silicon nitride.

[0047] Fig.15 It is a schematic diagram of the structure of the first oxide layer being corroded.

[0048] Fig.16 It is a schematic diagram of the structure for growing the third oxide layer.

[0049] Fig.17 It is a schematic diagram of the structure for depositing the second polysilicon.

[0050] Fig.18 It is a schematic diagram of the structure of etching the second polysilicon.

[0051] Fig.19 It is a schematic diagram of the structure that forms the source region and the body region.

[0052] Fig. 20 It is a schematic diagram of the structure for forming a contact hole.

[0053] Fig.21 It is a schematic diagram of the structure for forming metal wiring.

[0054] Description of the label:

[0055] 1. Substrate; 2. Epitaxial layer; 3.1. First trench; 3.2. Second trench; 4. First oxide layer; 5. First silicon nitride; 6. Second silicon nitride; 7. First polysilicon; 8. Second oxide layer; 9. Third oxide layer; 10. Second polysilicon; 11. Body region; 12. Source region; 13. Dielectric layer; 15.1. First contact hole; 15.2. Second contact hole; 15.3. Third contact hole; 16.1. First metal connection; 16.2. Second metal connection; 16.3. Third metal connection. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0058] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0059] Please combine Figure 1 The first embodiment of the present invention discloses a method for manufacturing a shielded gate trench MOSFET, and the manufacturing method specifically comprises the following steps:

[0060] Step S1: growing an epitaxial layer 2 on the surface of the substrate 1, forming a first trench 3.1 and a second trench 3.2 in the epitaxial layer 2, and forming a first oxide layer 4 on the surfaces of the first trench 3.1 and the second trench 3.2. Figure 3-4 shown.

[0061] Step S2: Generate first silicon nitride 5 on the surface of the first oxide layer 4, etch the first silicon nitride 5, and retain part of the first silicon nitride 5 at the bottom of the first trench 3.1 and the second trench 3.2. Figure 5-6 shown.

[0062] Step S3: depositing the second silicon nitride 6 on the surface of the first oxide layer 4 and the first silicon nitride 5, depositing the first polysilicon 7 on the surface of the second silicon nitride 6, and etching the first polysilicon 7 so that the height of the first polysilicon 7 is lower than the first trench 3.1 and the second trench 3.2. Figure 7-9 shown.

[0063] Step S4: Etching the first polysilicon 7 in the first trench 3.1 so that the height of the first polysilicon 7 in the first trench 3.1 is lower than the height of the first polysilicon 7 in the second trench 3.2. Fig.10 shown.

[0064] Step S5, depositing a second oxide layer 8 in the first trench 3.1 and the second trench 3.2, grinding the second oxide layer 8 so that the height of the second oxide layer 8 is flush with the second silicon nitride 6, and etching a portion of the second oxide layer 8 in the first trench 3.1. Figure 11-13 shown.

[0065] Step S6: Etching the second silicon nitride 6 so that the height of the second silicon nitride 6 in the first trench 3.1 is flush with the second oxide layer 8, and etching the first oxide layer 4 so that the first oxide layer 4 in the first trench 3.1 is flush with the second silicon nitride 6. Figure 14-15 shown.

[0066] Step S7: growing a third oxide layer 9 on the sidewalls of the first trench 3.1 and the second trench 3.2, the third oxide layer 9 being connected to one end of the first oxide layer 4, depositing the second polysilicon 10, etching part of the second polysilicon 10 in the first trench 3.1, and etching away all of the second polysilicon 10 in the second trench 3.2. Figure 16-18 shown.

[0067] Step S8: forming the body region 11 and the source region 12 in sequence, depositing the dielectric layer 13, drilling holes at the positions of the first trench 3.1 and the second trench 3.2 to obtain the first contact hole 15.1 and the second contact hole 15.2, and drilling holes between adjacent first trenches to obtain the third contact hole 15.3. Figure 19-20 shown.

[0068] It can be understood that in step S1, the first groove 3.1 is a groove in the cell area, and the second groove 3.2 is a groove in the shielding gate connection area, wherein the number of first grooves 3.1 is several (greater than or equal to 2), the several first grooves 3.1 are arranged adjacent to each other, and the depth of the first groove 3.1 and the second groove 3.2 is 1.5-15 microns.

[0069] It can be understood that in step S2, the first silicon nitride 5 is deposited on the surface of the first oxide layer 4, and the process method can be a high-density plasma chemical vapor deposition method, so that the first silicon nitride 5 covers the surface of the first oxide layer 4 and fills the first trench 3.1 and the second trench 3.2. Then, the first silicon nitride 5 outside the first trench 3.1 and the second trench 3.2 is completely etched away, and the first silicon nitride 5 is continuously etched to retain the first silicon nitride 5 located at the bottom of the first trench 3.1 and the second trench 3.2, and after the first silicon nitride 5 is etched, the longitudinal thickness of the first silicon nitride 5 in the first trench 3.1 and the second trench 3.2 is 0.2-1 micrometer.

[0070] It can be understood that in step S3, the second silicon nitride 6 is deposited on the surface of the first oxide layer 4 and the first silicon nitride 5, and the first polysilicon 7 is deposited on the surface of the second silicon nitride 6, and the first polysilicon 7 fills the remaining area of ​​the groove. Then, the first polysilicon 7 outside the first groove 3.1 and the second groove 3.2 is completely etched away, and the top surface height of the first polysilicon 7 retained in the first groove 3.1 and the second groove 3.2 is 0-0.5 microns lower than the top surface of the second silicon nitride 6 (e.g., Fig. 9 A dimension shown in ).

[0071] It can be understood that in step S3, the thickness of the first oxide layer 4 is 30-500 nanometers, and the thickness of the second silicon nitride layer 6 is 30-500 nanometers.

[0072] It can be understood that in step S4, the first polysilicon 7 in the first trench 3.1 is continuously etched, and the distance between the first polysilicon 7 in the first trench 3.1 and the upper surface of the epitaxial layer 2 is 1-2 microns (eg Fig.10 ), that is, the first polysilicon 7 in the first trench 3.1 is 1-2 microns lower than the upper surface of the epitaxial layer 2.

[0073] It can be understood that in step S5, a high-density plasma chemical vapor deposition process is used to deposit the second oxide layer 8 in the first trench 3.1 and the second trench 3.2, and the second oxide layer 8 completely fills the first trench 3.1 and the second trench 3.2. Then, the second oxide layer 8 that is higher than the top plane of the second silicon nitride 6 is completely ground off, so that the height of the second oxide layer 8 is flush with the second silicon nitride 6, and then part of the second oxide layer 8 in the first trench 3.1 is etched, so that the longitudinal thickness of the second oxide layer 8 retained in the first trench 3.1 is 0.2-0.8 microns.

[0074] It can be understood that in step S6, the second silicon nitride 6 that is higher than the top plane of the second oxide layer 8 is completely etched away, so that the height of the second silicon nitride 6 in the first trench 3.1 is flush with the second oxide layer 8. Then, the first oxide layer 4 is etched away, and the first oxide layer 4 on both sides of the second silicon nitride 6 and the first oxide layer 4 below and on both sides of the first silicon nitride 5 are retained. Specifically, the first oxide layer 4 that is higher than the top plane of the second silicon nitride 6 in the first trench 3.1 is completely etched away, so that the first oxide layer 4 in the first trench 3.1 is flush with the second silicon nitride 6. At this time, part of the sidewall of the first trench 3.1 is exposed.

[0075] It can be understood that in step S6, while etching the first oxide layer 4, a portion of the second oxide layer 8 above the first polysilicon 7 is also synchronously etched away. After this step, the longitudinal thickness of the second oxide layer 8 is 0.15-0.6 microns.

[0076] It can be understood that in step S7, the region of the trench 3 with the exposed sidewall is oxidized to grow a third oxide layer 9, and one end of the third oxide layer 9 is connected to one end of the first oxide layer 4. Specifically, an oxidation process of 800-1100 degrees Celsius is adopted, and oxygen atoms react with silicon atoms on the sidewalls of the first trench 3.1 and the second trench 3.2 to generate the third oxide layer 9, and the third oxide layer 9 is the gate oxide layer of the MOSFET, and the thickness of the third oxide layer 9 is 15-80 nanometers.

[0077] It can be understood that in step S7, the type of MOSFET is the same as the doping type of the second polysilicon 10. For example, when the MOSFET is an N-type MOSFET, the doping type of the second polysilicon 10 is N-type; when the MOSFET is a P-type MOSFET, the doping type of the second polysilicon 10 is P-type, and the second polysilicon 10 is the polysilicon gate of the MOSFET.

[0078] It can be understood that in step S7, the second polysilicon 10 in the second groove 3.2 is completely etched away, and the top surface height of the second polysilicon 10 retained in the first groove 3.1 is 0-0.2 microns lower than the upper surface of the epitaxial layer 2, that is, the top surface height of the second polysilicon 10 retained in the first groove 3.1 is 0-0.2 microns away from the top of the first groove 3.1.

[0079] It can be understood that in step S8, the body region 11 and the source region 12 are formed in sequence, and the dielectric layer 13 is deposited on the second polysilicon 10, the second oxide layer 8 and the third oxide layer 9. Specifically, the dielectric layer 13 is deposited on the second oxide layer 8 and the second silicon nitride 6 in the second trench 3.2 area, and the dielectric layer 13 is deposited on the third oxide layer 9 and the second polysilicon 10 surface to grow the dielectric layer 13 upward. Then, the first contact hole 15.1, the second contact hole 15.2 and the third contact hole 15.3 are formed by photolithography and etching processes, wherein the first contact hole 15.1 passes through the dielectric layer 13 to the second polysilicon 10, the second contact hole 15.2 passes through the dielectric layer 13, the second oxide layer 8 to the first polysilicon 7 in sequence, and the third contact hole 15.3 passes through the dielectric layer 13, the third oxide layer 9, the source region 12 to the body region 11 in sequence.

[0080] It can be understood that in step S8, the first polysilicon 7 in the first trench 3.1 is the shielding gate of the MOSFET, and the second polysilicon 10 in the first trench 3.1 is the polysilicon gate of the MOSFET, that is, each trench (the first trench 3.1) in the cell region contains a shielding gate (the first polysilicon 7) and a polysilicon gate (the second polysilicon 10), and the polysilicon gate is located above the shielding gate, and between the two is a polysilicon interlayer dielectric, i.e., the second oxide layer 8. The first polysilicon 7 in the second trench 3.2 is the wiring area of ​​the shielding gate of the MOSFET, and the first polysilicon 7 in the first trench 3.1 and the first polysilicon 7 in the second trench 3.2 are integrated (continuous), and since the first polysilicon 7 in the first trench 3.1 is buried under the second polysilicon 10 and cannot be drilled out, it can only be drilled out in the area of ​​the second trench 3.2.

[0081] It can be understood that after step S8, the following steps are also included:

[0082] Step S9: depositing metal in the first contact hole 15.1, the second contact hole 15.2 and the third contact hole 15.3 to obtain the first metal connection line 16.1, the second metal connection line 16.2 and the third metal connection line 16.3 respectively. Fig.21 shown.

[0083] It can be understood that in step S9, the first metal connection 16.1, the second metal connection 16.2 and the third metal connection 16.3 are respectively connected to the first contact hole 15.1, the second contact hole 15.2 and the third contact hole 15.3, that is, the first metal connection 16.1 is the metal connection of the second polysilicon 9, i.e., the polysilicon gate, the second metal connection 16.2 is the metal connection of the first polysilicon 7, i.e., the shielding gate, and the third metal connection 16.3 is the metal connection of the source region, i.e., the source electrode, and the metal connection 16.2 of the shielding gate and the metal connection 16.3 of the source region are metal interconnected in this step (not shown in the figure).

[0084] See also Figure 2 , the above step S6 specifically includes:

[0085] Step S61 : using an over-etching process to etch the second silicon nitride 6 on the top of the second oxide layer 8 , so that the second silicon nitride 6 is flush with the second oxide layer 8 .

[0086] Step S62 : Based on the isotropy of the etching process, the second silicon nitride 6 forms a first recessed area on both sides of the second oxide layer 8 .

[0087] Step S63: using an over-etching process to etch the first oxide layer 4 on the top of the second silicon nitride 6, so that the first oxide layer 4 is flush with the second silicon nitride 6, and the second oxide layer 8 is etched away partially at the same time.

[0088] Step S64 : Based on the isotropy of the etching process, the first oxide layer 4 forms second recessed areas on both sides of the second silicon nitride 6 .

[0089] It can be understood that in step S61, in order to ensure that the second silicon nitride 6 in the removed area is completely etched away, an over-etching margin of 10 to 30% is set. In addition, due to the isotropy of the etching process, silicon nitride recesses (i.e., first recessed areas, such as Fig.14 ).

[0090] It can be understood that in step S63, in order to ensure that the first oxide layer 4 in the removed area is completely etched away, an over-etching margin of 10 to 30% is set. In addition, due to the isotropy of the etching process, a first oxide layer depression (i.e., a second depression area, such as Fig.15 ).

[0091] Compared with the prior art, the method for manufacturing the shielded gate trench MOSFET provided by the present invention has the following beneficial effects:

[0092] 1. The shielded gate trench MOSFET manufactured by the method of this case has a dielectric layer under the shielding gate including a first oxide layer, a first silicon nitride and a second silicon nitride, and a dielectric layer on the side of the shielding gate including a first oxide layer and a second silicon nitride. That is to say, the thickness of the dielectric layer under the shielding gate is thicker than the thickness of the dielectric layer on the side, so the electric field strength at the bottom of the trench can be weakened, avoiding the problem of a stronger electric field at the bottom of the trench in the prior art. Therefore, this case improves the breakdown voltage of the MOSFET.

[0093] 2. A dielectric layer (second oxide layer) deposited by high-density plasma chemical vapor deposition is used as the polysilicon interlayer dielectric, and silicon nitride (second silicon nitride) is used as a stop layer for chemical mechanical polishing and a barrier layer for oxide layer corrosion. The formed polysilicon interlayer dielectric (second oxide layer) has a better isolation effect on the shielding gate (first polysilicon) and the polysilicon gate (second polysilicon), which can reduce the leakage between the shielding gate and the polysilicon gate and improve the performance of the MOSFET.

[0094] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for manufacturing a shielded gate trench MOSFET, characterized in that: The following steps are involved: Step S1: growing an epitaxial layer on the surface of the substrate, forming a first trench and a second trench in the epitaxial layer, and forming a first oxide layer on the surfaces of the first trench and the second trench; Step S2: generating a first silicon nitride on the surface of the first oxide layer, etching the first silicon nitride, and retaining a portion of the first silicon nitride at the bottom of the first trench and the second trench; Step S3: depositing a second silicon nitride on the first oxide layer and the first silicon nitride surface, depositing a first polysilicon on the second silicon nitride surface, and etching the first polysilicon so that the height of the first polysilicon is lower than the first trench and the second trench; Step S4: etching the first polysilicon in the first trench so that the height of the first polysilicon in the first trench is lower than the height of the first polysilicon in the second trench; Step S5, depositing a second oxide layer in the first trench and the second trench, grinding the second oxide layer so that the height of the second oxide layer is flush with the second silicon nitride, and etching a portion of the second oxide layer in the first trench; Step S6: etching the second silicon nitride so that the height of the second silicon nitride in the first trench is flush with the second oxide layer, and etching the first oxide layer so that the first oxide layer in the first trench is flush with the second silicon nitride; Step S61: using an over-etching process to etch the second silicon nitride on the top of the second oxide layer so that the second silicon nitride is flush with the second oxide layer; Step S62: Based on the isotropy of the etching process, the second silicon nitride forms a first recessed area on both sides of the second oxide layer; Step S63: using an over-etching process to etch the first oxide layer on the top of the second silicon nitride, so that the first oxide layer is flush with the second silicon nitride, and the second oxide layer is etched away partially at the same time; Step S64: Based on the isotropy of the etching process, the first oxide layer forms a second recessed area on both sides of the second silicon nitride; Step S7: growing a third oxide layer on the sidewalls of the first trench and the second trench, the third oxide layer being connected to one end of the first oxide layer, depositing second polysilicon, etching a portion of the second polysilicon in the first trench, and etching away all of the second polysilicon in the second trench; Step S8: forming a body region and a source region in sequence, depositing a dielectric layer, drilling holes at the positions of the first trench and the second trench to obtain a first contact hole and a second contact hole, and drilling holes between adjacent first trenches to obtain a third contact hole; In step S8, the first contact hole passes through the dielectric layer to the second polysilicon, the second contact hole passes through the dielectric layer, the second oxide layer to the first polysilicon in sequence, and the third contact hole passes through the dielectric layer, the third oxide layer, the source region to the body region in sequence; In the above step S2, after etching the first silicon nitride, the longitudinal thickness of the first silicon nitride in the first trench and the second trench is 0.2-1 micrometer; In the above step S4, the first polysilicon in the first trench is 1-2 microns lower than the upper surface of the epitaxial layer; In the above step S5, the longitudinal thickness of the second oxide layer retained in the first trench is 0.2-0.8 micrometers.

2. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The depth of the first groove and the second groove is 1.5-15 microns.

3. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The thickness of the first oxide layer is 30-500 nanometers, and the thickness of the second silicon nitride layer is 30-500 nanometers.

4. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: In the above step S3, after etching the first polysilicon, the top surface of the first polysilicon in the first trench and the second trench is 0-0.5 microns lower than the top surface of the second silicon nitride.

5. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The type of the MOSFET is the same as the doping type of the second polysilicon.

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