Analog calculation method for solving large-scale linear equations based on variable resistor array

Abstract

The present invention discloses a simulation calculation method for solving large-scale linear equations based on a variable resistor array. The method divides the matrix A of the linear equation problem Ax=b into two k ×2 k sub-matrices, the known vector b is also decomposed into 2 k sub-vectors, and then perform a series of matrix multiplications or inversions on these sub-matrices to obtain 2 k The solution of the unknown vector x is restored by combining the sub-vector solutions. The element values ​​of these sub-matrices are mapped to the conductance values ​​of the variable resistor array, and the matrix multiplication or matrix inversion (i.e., solving a system of linear equations) is realized by reconfigurable connection with the operational amplifier circuit. The present invention realizes continuous calculation in the full analog domain, avoids the huge energy, area and time overhead required for digital-to-analog / analog-to-digital conversion, and has a wide range of application scenarios in the fields of machine learning, scientific computing, optimization, etc.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor, analog computing and integrated circuit, and specifically relates to an analog computing method for solving large-scale linear equations based on a variable resistor array. Background Art

[0002] The problem of linear equations exists in almost all fields of science and engineering, such as weather forecasting based on scientific computing, genetic analysis, training of machine learning algorithms, and massive MIMO in wireless communications. At present, both the cloud and the edge are facing the trend of explosive growth of data, and big data processing poses a severe challenge to the performance of computing systems. However, with the gradual failure of Moore's Law and the inherent defects of the separation of storage and computing in the von Neumann architecture, traditional digital computers are difficult to meet the needs of big data computing. In recent years, analog computing based on arrays of variable resistor devices (such as resistive memory) has received widespread attention. On the one hand, it can realize in-situ computing of data, greatly saving energy consumption and delay of data transportation. On the other hand, it can provide high parallelism of computing, greatly improving the speed of matrix operations.

[0003] By connecting the variable resistor array and the operational amplifier into a feedback loop, the circuit can realize the function of matrix inversion in one step and is applied to solving linear equations (D.Ielmini, Z.Sun, G.Pedretti, Mathematical problemsolving circuit comprising resistive elements, US Patent 16650883, 2020). However, due to the limited scale of the variable resistor array that can be prepared, it is difficult to solve large-scale linear equations using this circuit. In practical applications, the matrix dimension of the linear equations may be tens of thousands, while the scale of the variable resistor array is generally in the hundreds. Therefore, in order to realize the use of variable resistor arrays to solve large-scale linear equations, it is imperative to develop a scalable analog calculation method. Summary of the invention

[0004] The object of the present invention is to provide an analog calculation method based on a variable resistor array for solving large-scale linear equations.

[0005] The specific technical scheme of the present invention is as follows:

[0006] A simulation calculation method for solving a large-scale linear equation system based on a variable resistor array comprises the following steps:

[0007] 1) constructing a variable resistor array circuit, the variable resistor array circuit comprising a plurality of variable resistor arrays arranged in a logically coherent manner, the matrix multiplication or inversion operation of the plurality of variable resistor arrays sharing a set of operational amplifiers, the ports of each variable resistor array in four directions being connected to horizontal lines and vertical lines through switches, and the connection between the horizontal lines and the vertical lines being controlled by a crosspoint switch array;

[0008] 2) Split the matrix A of the linear equation problem Ax=b into 2 k ×2 k submatrices, the element values ​​of the submatrices are mapped to the conductance values ​​of the above variable resistor arrays. The known vector b is decomposed into 2 k sub-vectors as input vectors, the variable resistor array is reconfigurably connected to the operational amplifier, and continuous matrix multiplication or matrix inversion operations are completed in sequence to obtain 2 k sub-vector solutions, which are combined together to recover the solution of the unknown vector x.

[0009] The analog calculation method of the present invention includes two basic operations: matrix multiplication and matrix inversion, both of which are implemented by reconfigurable connections between a variable resistor array and an operational amplifier circuit. Taking k=1 as an example, A is divided into There are four sub-matrices of the form, of which only A is required 1 and A 4 is a square matrix, correspondingly A 2 and A 3 It may be a square matrix or a general rectangular matrix. Assume that the submatrix A 4 Calculated by The present invention will sequentially replace A 1 Perform matrix inversion operation on A 3 Perform matrix multiplication on A 4s Perform matrix inversion operation on A 2 Perform matrix multiplication on A 1 The present invention is based on the matrix multiplication of the variable resistor array or the inherent inversion function of the inversion circuit, and changes the positive and negative signs of the input vectors of these two types of operations in turn.

[0010] Furthermore, the present invention only includes one group of operational amplifiers, although there are multiple variable resistor arrays involved in the calculation. Through the time division multiplexing method, all variable resistor arrays are reconfigurably connected to the operational amplifiers in turn, that is, the variable resistor arrays and the operational amplifiers are two discrete modules. By changing the connection between the two and the operational amplifier feedback resistor, the output of the operational amplifier can represent the result of matrix multiplication or inversion.

[0011] The sub-vector addition involved in the present invention can be naturally incorporated into the matrix inversion operation. When the input vector has two items, namely the sum of the sub-vector of b and the result vector of the previous matrix multiplication, the matrix inversion operation with the sum vector as input is implemented through two groups of input ports, without the need for a separate vector addition operation.

[0012] The input of each variable resistor array is transmitted by a digital-to-analog converter and / or a sample-and-hold input circuit, wherein the input of the digital-to-analog converter is provided by an input buffer.

[0013] The beneficial effects of the present invention are as follows:

[0014] The present invention provides a simulation calculation method for solving any large-scale linear equations based on a variable resistor array, which can be used for large-scale problem solving and related applications, and the sub-matrix algorithm process is all implemented in the analog domain, and the intermediate results are simulated and stored using a sampling and holding circuit, and directly used as the input of the next operation in the process, which greatly saves the energy consumption and delay caused by digital-to-analog / analog-to-digital conversion. In addition, the variable resistor array of the present invention shares a group of operational amplifiers, and matrix operations are carried out through time-division multiplexing reconfigurable operational amplifier circuits according to the algorithm process, which significantly improves the utilization efficiency of the operational amplifier and reduces the area overhead of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit structure diagram for calculating matrix multiplication in one step using a variable resistor array;

[0016] Figure 2 It is a circuit structure diagram for realizing matrix inversion in one step by using a variable resistor array;

[0017] Figure 3 It is a circuit structure diagram of the matrix inversion with vector addition as input of the present invention;

[0018] Figure 4 It is a structural diagram of a reconfigurable circuit applicable to matrix multiplication and matrix inversion of the present invention;

[0019] Figure 5 It is a schematic diagram of the original matrix divided into sub-matrices;

[0020] Figure 6 It is a calculation flow chart of solving the original linear equations of the present invention;

[0021] Figure 7 is an operation flow chart of a reconfigurable circuit in a specific embodiment of the present invention;

[0022] Figure 8 yes Figure 7 Step 1 of the operation process;

[0023] Fig. 9 yes Figure 7Step 2 of the operation process;

[0024] Fig.10 yes Figure 7 Step 3 of the operation process;

[0025] Fig.11 yes Figure 7 Step 4 of the operation process;

[0026] Fig.12 yes Figure 7 Step 5 of the operation process;

[0027] Fig.13 It is a diagram of the analog computing architecture based on the sub-matrix variable resistor array of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the following is a further detailed description in conjunction with the accompanying drawings. The description herein is only used to explain the present invention and is not intended to limit the present invention.

[0029] The present invention provides a simulation calculation method for solving large-scale linear equations based on a variable resistor array. The method relies on the matrix multiplication and inversion operations of the basic variable resistor array. The original problem is solved by performing these two types of operations on the arrays corresponding to different sub-matrices in sequence.

[0030] Figure 1 A circuit that performs matrix multiplication using a variable resistor array (assuming N rows and N columns) and a group of transimpedance amplifiers (TIA, N pieces). The horizontal lines in the array are word lines, and the vertical lines are bit lines. There is a variable resistor device (such as a resistive memory) at the intersection of each word line and each bit line. The conductance of the N×N devices constitutes a conductance matrix G. The voltage applied to the N bit lines of the variable resistor array constitutes the input voltage vector v in A TIA consists of an operational amplifier and a feedback resistor, assuming the conductance of the latter is G 0 According to Kirchhoff's current law and feedback theory, the vector formed by the TIA output voltage satisfies Figure 1 Formula (1) in , that is

[0031]

[0032] It can be regarded as the result of mapping an N×N matrix A on the variable resistor array, v in Represents a known N×1 input vector y, v out represents the calculation result, which is an N×1 output vector x. Then, Figure 1The circuit performs a multiplication between the matrix A and the vector y, and this operation has an inherent negation function, that is,

[0033] x=-A·y.

[0034] It should be noted that Figure 1 The circuit shown does not limit A to be a positive matrix. For matrices with negative elements, mapping can be achieved by subtracting two positive matrices. The two positive matrices are represented by two variable resistor arrays, and the subtraction operation is achieved by a group of analog inverters. The circuit structure is similar to Figure 1 The same. Therefore, Figure 1 The circuit can be used to represent the multiplication of any real matrix and any real vector. In addition, although the above discussion considers the case where A is a square matrix, Figure 1 The circuit does not have this restriction and is applicable to the case where A is an arbitrary rectangular matrix.

[0035] Figure 2 A circuit that uses a variable resistor array (N rows, N columns) and a set of operational amplifiers (N units) to perform matrix inversion. The word line of the variable resistor array is connected to the negative input terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the bit line of the variable resistor array to form a negative feedback loop. The conductance of the variable resistor array forms a matrix G, and the input voltage vector v in Through a set of input resistors (conductance value G 0 ) is connected to the array word line. According to the "virtual short and virtual break" characteristics of the operational amplifier and Kirchhoff's current law in the array, the vector formed by the operational amplifier output voltage satisfies Figure 2 Formula (2) in , that is

[0036]

[0037] Mapping matrix A, v in Represents the known input vector y, v out represents the unknown output vector x. Then, Figure 2 The circuit performs the solution of the linear equation problem Ax = -y, and obtains

[0038] x=-A -1 ·y,

[0039] Among them, A -1 represents the inverse matrix of A. Therefore, this circuit performs a matrix inversion operation and it also has an inherent negation function. Figure 2 In the circuit, N word lines correspond to N bit lines through feedback connection one by one. Therefore, the circuit requires that the matrix A is a square matrix, which is consistent with the requirement of matrix inversion. Figure 1 Same, Figure 2The circuit does not restrict A to be a positive real matrix; it can represent the inversion operation of any real matrix.

[0040] Figure 3 The matrix inversion circuit of the present invention with vector sum as input has the same basic structure as Figure 2 Same as above, except for the number of input voltage vectors: Figure 2 The circuit has only one input voltage vector, Figure 3 There are two, v in1 and v in2 , respectively through two sets of input resistors (the conductivity value is G 0 ) connected to the array word line. Figure 3 In the equation, the vector formed by the operational amplifier output voltage satisfies formula (3), that is,

[0041]

[0042] The solution to the mathematical problem it maps to is

[0043] x=-A -1 ·(y 1 +y 2 ),

[0044] where y 1 and 2 are two known vectors as input. In the simulation calculation method for solving large-scale linear equations provided by the present invention and its implementation based on variable resistor array, Figure 1 , Figure 2 and Figure 3 The circuit constitutes three basic matrix operations.

[0045] Figure 4 The invention is a reconfigurable circuit suitable for matrix multiplication and matrix inversion operations. The reconfigurable circuit can switch the working mode by controlling the connection switch. When the feedback resistor of the operational amplifier is connected and the line from the output end to the bit line is disconnected, the circuit works in the matrix multiplication mode, and accordingly, a group of input voltages are applied to the bit line of the variable resistor array at this time; when the output end of the operational amplifier is connected to the line of the bit line and the feedback resistor line is disconnected, the circuit works in the matrix inversion mode, and one or two groups of input voltages are applied to the word line of the variable resistor array through the input resistor.

[0046] Figure 5 Schematic diagram of dividing an N×N original square matrix A into 2×2 sub-matrices. 1 and A 4 are square matrices of size M×M and (NM)×(NM), respectively, where M is a positive integer less than N, and M is generally considered to be equal to or close to N / 2. 2 and A3 The sizes are M×(NM) and (NM)×M respectively.

[0047] Figure 6 The figure is a flow chart of solving large-scale linear equations based on variable resistor arrays in the present invention. The known vector b of the original linear equation problem is divided into two sub-vectors f and g, with dimensions of M and NM respectively; the unknown vector x is divided into two sub-vectors y and z, with dimensions of M and NM respectively. The algorithm will calculate the unknown vectors y and z to obtain the solution of x.

[0048] The algorithm consists of the following five steps:

[0049] 1. Solve the linear equation system A 1 y t =f. Due to the inversion function of the matrix inversion circuit, the vector solution is

[0050] 2. Develop Matrix A 3 With vector y t The input vector is -y. t , due to the negation function of the matrix multiplication circuit, the resulting vector is g t =A 3 y t ;

[0051] 3. Carry out vector addition -g s =-g+g t , and solve the linear equation system A 4s z=g s The input vector of the matrix inversion circuit is -g s - By applying -g and g simultaneously t Two vectors are realized, and the vector solution is z = A 4s -1 g s . Submatrix A 4s Based on A 4 Get, that is The present invention considers A 4s has been precomputed and replaces the original submatrix A 4 Circumstances;

[0052] 4. Develop Matrix A 2 Multiplication with vector z. The input vector is z, and due to the negation function of the matrix multiplication circuit, the result vector is -f t =-A 2 z;

[0053] 5. Carry out vector addition f s =-f t +f, and solve the linear system A1 y=f s The input vector of the matrix inversion circuit is f s - By applying -f t and f are realized by two vectors, and the vector solution is

[0054] By combining the vectors z and -y obtained by the submatrix algorithm, the solution x of the original linear equations problem can be restored.

[0055] Figure 7 The present invention is a schematic diagram of the operation of executing a sub-matrix algorithm based on a variable resistor array. 2×2 sub-matrices are mapped by 4 variable resistor arrays respectively, and each sub-matrix array can form a reconfigurable connection with an operational amplifier (OA) to work in a matrix multiplication or matrix inversion mode. The input of the circuit is provided by a digital-to-analog converter (DAC) and a sample-and-hold input circuit (Input S&H). The output voltage of each step of the matrix operation is analog stored using a sample-and-hold output circuit (Output S&H), which transmits the voltage vector to the input circuit Input S&H (analog copy) as the input of the next operation, and the signal of the output circuit Output S&H will be reset to zero. The analog voltage of the output circuit Output S&H can be converted to the digital domain through an analog-to-digital converter (ADC).

[0056] Figure 8 As the first step of the operation flow, the sub-matrix A is solved by reconfigurable connection array 1 and OA circuit. 1 The linear equations of , the input voltage vector is provided by the DAC.

[0057] Fig. 9 In step 2 of the operation flow, the sub-matrix A is executed by reconfiguring the connection array 3 and the OA circuit. 3 The input voltage vector is provided by Input S&H.

[0058] Fig.10 In the third step of the operation flow, the submatrix A is solved by reconfigurable connection array 4 and OA circuit. 4s The two input voltage vectors are provided by DAC and Input S&H respectively, and the output vector is converted to the digital domain through ADC.

[0059] Fig.11 In step 4 of the operation flow, the sub-matrix A is executed by reconfiguring the connection array 2 and the OA circuit. 2 The input voltage vector is provided by Input S&H.

[0060] Fig.12For step 5 of the operation flow, the submatrix A is solved by reconfigurable connection array 1 and OA circuit. 1 The two input voltage vectors are provided by DAC and Input S&H respectively, and the output vector is converted to the digital domain through ADC.

[0061] exist Fig.10 Step 3 of Fig.12 In step 5, the digital signals converted by the ADC are stored in the output buffer and combined into the solution of the original linear equations. Multiple output circuits Output S&H can also be implemented by using only one ADC through a multiplexer (MUX).

[0062] Fig.13 The present invention is based on the analog computing architecture diagram of the sub-matrix variable resistor array. Each variable resistor array has a set of interconnection lines in the four directions, horizontal lines in the horizontal direction and vertical lines in the vertical direction. Each variable resistor array can be connected to the interconnection lines through ports in four directions, accessed to DAC and / or Input S&H, and connected to the operational amplifier OA circuit for matrix multiplication or matrix inversion working mode. The connection between the horizontal lines and the vertical lines is controlled by the crosspoint switch array. Each variable resistor array can form a reconfigurable connection with the operational amplifier OA, and the operational amplifier OA participates in each step of the operation. The input of the variable resistor array circuit is provided by a digital-to-analog converter (DAC) and a sampling and holding input circuit (Input S&H). The output voltage of each step of the matrix operation is analog stored using a sampling and holding output circuit (Output S&H), which transmits the voltage vector to the input circuit Input S&H (analog copy) as the input of the next operation, and the signal of the output circuit Output S&H will be reset to zero. The analog voltage of the output circuit Output S&H can be converted to the digital domain through an analog-to-digital converter (ADC). The known vectors of the original linear equations are provided to the DAC from the input buffer, and the solutions of the linear equations are stored in the output buffer through the ADC.

Claims

1. A simulation calculation method for solving a large-scale linear equation system based on a variable resistor array, comprising the following steps: 1) constructing a variable resistor array circuit, the variable resistor array circuit comprising a plurality of variable resistor arrays arranged in a logically coherent manner, the matrix multiplication or inversion operation of the plurality of variable resistor arrays sharing a set of operational amplifiers, the ports of each variable resistor array in four directions being connected to horizontal lines and vertical lines through switches, and the connection between the horizontal lines and the vertical lines being controlled by a crosspoint switch array; 2) Split the matrix A of the linear equation problem Ax=b into 2 k ×2 k submatrices, the element values ​​of the submatrices are mapped to the conductance values ​​of the above variable resistor array. The known vector b is decomposed into 2 k sub-vectors as input vectors, the variable resistor array is reconfigurably connected to the operational amplifier, and continuous matrix multiplication or matrix inversion operations are completed in sequence to obtain 2 k The above sub-vector solutions are combined together to restore the solution of the unknown vector x.

2. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: For a matrix containing negative elements, mapping is achieved by subtracting two positive matrices, and the two positive matrices are represented by two variable resistor arrays respectively, and the subtraction operation is implemented by a group of analog inverters.

3. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The variable resistor array and the operational amplifier perform matrix multiplication operations. Specifically, there is a variable resistor device at the intersection of each word line and each bit line in the variable resistor array. The conductance of the N×N variable resistor devices constitutes a conductance matrix G. The voltage applied to the N bit lines of the variable resistor array constitutes an input voltage vector v in , the feedback conductances of the N operational amplifiers connected to the N word lines are all G0, and the vector formed by the output voltages of the above operational amplifiers satisfies formula (1), that is, The result of mapping an N×N matrix A on the variable resistor array, v in Represents a known input vector y,x = -A·y,v out represents the unknown output vector x.

4. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The variable resistor array and the operational amplifier perform a matrix inversion operation. Specifically, the word line of the variable resistor array is connected to the negative input terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the bit line of the variable resistor array to form a negative feedback loop. The vector formed by the output voltage of the operational amplifier satisfies formula (2), that is, The result of mapping an N×N matrix A on the variable resistor array, v in Represents a known input vector y, x = -A -1 y, v out represents the unknown output vector x.

5. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: Sub-vector addition is incorporated into the matrix inversion operation. The sub-vector of b is added to the result vector of the previous matrix multiplication through two sets of input ports. The vector formed by the output voltage of the operational amplifier satisfies formula (3), that is, The result of mapping an N×N matrix A on the variable resistor array, v in1 and v in2 Denotes known input vectors y1 and y2, x = -A -1 (y1+y2), v out represents the unknown output vector x.

6. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The matrix multiplication or matrix inversion operation is switched by controlling the crosspoint switch array. Specifically, when the line from the output of the operational amplifier to the bit line of the variable resistor array is disconnected, it is in the matrix multiplication mode, and accordingly, a group of input voltages are applied to the bit line of the variable resistor array; when the line from the output of the operational amplifier to the bit line of the variable resistor array is connected, it is in the matrix inversion mode, and at this time, one or two groups of input voltages are applied to the word line of the variable resistor array through the input resistor.

7. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The input of each variable resistor array is transmitted by a digital-to-analog converter and / or a sample-and-hold input circuit, wherein the input of the digital-to-analog converter is provided by an input buffer.

8. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The output voltage of the variable resistor array at each step is analogically stored using a sample-and-hold output circuit, and the sample-and-hold output circuit transmits the voltage vector to the input circuit as the input for the next operation.

9. The simulation calculation method for solving large-scale linear equations based on variable resistor arrays as claimed in claim 1, characterized in that: The analog voltage of the output circuit can be converted into the digital domain through an analog-to-digital converter.

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