Dynamic mapping method for multi-bank access, electronic device and storage medium

Abstract

The present invention relates to the field of chip design, and in particular to a dynamic mapping method, electronic device and storage medium for multi-bank access, which obtains the address of a target memory bank bank0 by parsing an access request command cmd0; if the number of state machines currently allocated to a bank is greater than a preset allocation threshold, a mapping relationship between bank0 and a target state machine FSM0 is established through dynamic mapping, and the steps of dynamic mapping include: if there is a state machine with an unallocated bank, a state machine FSM0 of an unallocated bank is allocated to bank0, and a mapping relationship between FSM0 and bank0 is established; and at the same time, the state machine FSM0 is released. i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i It reduces area overhead and also improves the timing of logic design.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a dynamic mapping method for multi-bank access, electronic equipment and storage medium. Background Art

[0002] The processor accesses the memory through the memory controller (MC). When accessing the memory, the memory controller needs to strictly comply with the access timing requirements of the memory particles, that is, the memory controller needs to strictly control the access state and keep it consistent with the state inside the particle. Among them, the memory is usually divided into multiple banks (memory banks). The timing requirements between access commands between banks are significantly better than the timing requirements between access commands within the same bank. By using interleaved access of banks, the memory access efficiency can be significantly improved and the memory throughput can be significantly improved. A state machine is allocated in the memory controller, and the state machine is used to control the legal access to the banks in the memory particles. Among them, the state machine is responsible for managing the state of each bank, such as idle, activated, precharged, etc., to ensure that interleaved access is maximized and the overall data throughput is improved under the premise of strictly complying with the access timing requirements of the memory particles. Usually, the number of banks in the memory is equal to the number of state machines in the memory controller, and one bank is allocated to one state machine to form a one-to-one mapping relationship. For example, if the particle to be accessed has 64 banks, 64 state machines will be synchronously mapped in the memory controller.

[0003] Currently, the overall efficiency of the memory system is further improved by increasing the number of banks in the memory. In theory, the more banks there are, the more requests the memory can process simultaneously, which is particularly important for high-efficiency, large-capacity application scenarios. However, when the number of banks increases to 128 or 256, or even more banks, relying on the traditional method of adding a one-to-one state machine inside the memory controller at the same time will bring the following defects:

[0004] First, the rapid growth of design area;

[0005] Second, as the number of banks increases, the complexity inside the memory controller also increases, making it more difficult to converge the design timing. Summary of the invention

[0006] In view of the above technical problems, the technical solution adopted by the present invention is: a dynamic mapping method for multi-bank access, the method comprising the following steps:

[0007] S100, parsing the access request command cmd0, and obtaining the address of the target memory bank bank0 to be accessed.

[0008] S200, if the number of state machines currently allocated to the memory bank bank is greater than a preset allocation threshold, a mapping relationship between the bank0 and the target state machine FSM0 is established through dynamic mapping, the dynamic mapping step comprising:

[0009] S210, if there is currently a state machine with an unassigned bank, an unassigned bank state machine FSM0 is assigned to the bank0, and the FSM0 establishes a mapping relationship between the FSM0 and the bank0 by binding the address of the bank0, so that the FSM0 tracks and manages the access status of the bank0; at the same time, the state machine FSM0 is released i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i .

[0010] S220, if there is no state machine of an unallocated bank currently, the cmd0 is put into a waiting queue to wait for a state machine of an unallocated bank that is released after the mapping relationship is released.

[0011] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0012] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0013] The present invention has at least the following beneficial effects:

[0014] Through dynamic mapping, the number of state machines does not need to increase linearly one-to-one with the increase in the number of banks, thereby reducing the area overhead caused by the surge in the number of state machines. The reduction in the number of state machines also improves the timing of logic design, reduces complexity, and is easier to converge than existing technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a dynamic mapping method for multi-bank access provided in the first embodiment of the present invention;

[0017] Figure 2 A flowchart of the steps of dynamic mapping provided in Embodiment 1 of the present invention;

[0018] Figure 3 A schematic diagram of the structure of a dynamic mapping system for multi-bank access provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1 , which shows a dynamic mapping method for multi-bank access, the method comprising the following steps:

[0021] S100, parsing the access request command cmd0, and obtaining the address of the target memory bank bank0 to be accessed.

[0022] Among them, the dynamic mapping method is applicable to a memory controller.

[0023] The access request command carries the bank address information and command type, and the timing parameters specified for each memory type that the command needs to follow. The bank address is the address of the bank in the memory that needs to be accessed. The command type is such as ACTIVATE, READ, WRITE, PRECHARGE, etc., which are used to guide the memory controller to execute the corresponding operation sequence. The timing parameters are used to define the minimum number of cycles that must be waited between commands to ensure the correct execution of the operation.

[0024] A bank is an independent storage area in the memory, which can read and write data independently. A memory includes multiple banks.

[0025] S200, if the number of state machines currently allocated to the memory bank bank is greater than a preset allocation threshold, a mapping relationship between the bank0 and the target state machine FSM0 is established through dynamic mapping.

[0026] The state machine has multiple states, each of which represents a different stage or preparation of a bank operation. For example, the "idle" state may represent waiting for a new command.

[0027] Among them, the state machine in the memory controller is used to manage and control the complex timing of memory access, ensuring that all operations follow the strict timing requirements of memory particles. The memory controller first receives the access request command cmd0 from the CPU and parses cmd0 to determine the command type and target Bank. Then, based on the parsing results, the memory controller instructs the state machine to transition to the corresponding state. Based on the command type and current state parsed by the memory controller, the state machine generates specific control signals that command the bank to perform various operations such as read, write, refresh, precharge, etc., such as row address select (RAS), column address select (CAS), write enable (WE), etc. Once the operation is completed, the state machine migrates to the next appropriate operation state based on the operation results and any newly received commands.

[0028] The mapping relationship is a mapping relationship between a bank and a state machine, which is a one-to-one mapping relationship. The mapping relationship is not fixed. After the mapping relationship between the state machine and the bank is released, the mapping relationship between the state machine and other banks can be re-established.

[0029] See also Figure 2 , further, the step of dynamic mapping includes:

[0030] S210, if there is currently a state machine with an unassigned bank, an unassigned bank state machine FSM0 is assigned to the bank0, and the FSM0 establishes a mapping relationship between the FSM0 and the bank0 by binding the address of the bank0, so that the FSM0 tracks and manages the access status of the bank0; at the same time, the state machine FSM0 is released i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i .

[0031] The state machine with unallocated bank means that the state machine has not established a mapping relationship with any bank in the memory and is not occupied.

[0032] It should be noted that when the number of state machines in the allocated bank is greater than the allocation threshold, a small number of state machines in the unallocated bank may also exist in the memory controller.

[0033] As an example, when the total number of state machines in the memory controller is 10, the total number of banks in the memory is 64, and the preset allocation threshold is 7. When the number of allocated state machines is 8, there may be a margin of two state machines in the system to allocate one state machine to bank0.

[0034] Among them, in order to make the state machine in the memory controller recyclable. When a state machine is consumed, the memory controller attempts to release a pair of mapping relationships and release the corresponding state machine for subsequent access request commands. Through dynamic mapping, the number of state machines does not need to increase linearly one-to-one with the increase in the number of banks, thereby reducing the area overhead caused by the surge in the number of state machines. The reduction in the number of state machines also improves the timing of logic design.

[0035] As a preferred embodiment, in S210, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between include: when the FSM i An access request command is detected hitting an activated bank i When the FSM is not released i With bank i The mapping relationship between them; until the current continuous access ends, the FSM is released i With bank i When there is a hit bank, maintaining the current mapping relationship can reduce state transition time and reallocation overhead, directly speed up the execution of subsequent commands, and improve access efficiency.

[0036] As a preferred embodiment, in S210, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between the two also include: when there is a command that is about to time out in the command queue, and the target memory bank accessed by the command that is about to time out is bank i , without releasing the FSM i With bank i until no bank is accessed in the queue i After the command is about to time out, release the FSM i With bank i By giving priority to commands that are about to time out, the overall execution time and waiting time of tasks can be effectively reduced, and the system's response speed to external requests or internal scheduling can be improved. Avoiding command timeouts reduces the need for error handling and retransmission caused by timeouts, thereby reducing the waste of system resources.

[0037] Optionally, the command in the command queue has a timeout tag, and the timeout tag is used to count the remaining time of the current command. Other methods for marking commands that are about to time out all fall within the protection scope of the present invention.

[0038] As a preferred embodiment, in S210, the release state machine FSMi With bank i The mapping relationship between banks also satisfies the demapping conditions: i Can be interleaved with other commands in the command queue, then the FSM is not released i With bank i The interleaving operation can improve the processing efficiency of commands, so the interleaving operation needs to be considered before demapping to improve the processing efficiency.

[0039] As a preferred embodiment, the method further includes: S10, obtaining a new command, and when the priority of an existing command in the command queue is higher than the new command, adding the new command to the waiting queue. That is, if the priority of the new command is lower than that of the existing command, the command with the higher priority is processed first.

[0040] It should be noted that, ideally, the demapping speed is equal to the remapping speed, so that the memory controller reaches a balanced state. i With bank i The mapping relationship between them is subject to the restrictions of the demapping conditions. Therefore, it may happen that: a state machine FSM0 that is not assigned to a bank is assigned to bank0, but the current mapping relationship cannot be released due to the restrictions of the demapping conditions, resulting in no mapping relationship being released, that is, the demapping speed is lower than the remapping speed.

[0041] S220, if there is no state machine of an unallocated bank currently, the cmd0 is put into a waiting queue to wait for a state machine of an unallocated bank that is released after the mapping relationship is released.

[0042] As a preferred embodiment, S220 also includes:

[0043] S221, when there is an unallocated bank state machine FSM j When a candidate access request command cmd is taken out from the waiting queue w,j .

[0044] S222, obtaining the cmd w,j The address of the target bank.

[0045] S223, compare the address of the target bank with the FSM j Establish a mapping relationship between them.

[0046] As a preferred embodiment, in S221, the cmd is taken out from the waiting queue. w,jFollow the efficiency priority principle. The efficiency priority principle means that when scheduling tasks or allocating resources, tasks that can produce the greatest efficiency or benefits will be given a higher execution priority.

[0047] Optionally, the effectiveness priority principle is a command priority principle or an efficiency priority principle. Among them, the task priority principle is to set the priority of the task according to preset standards such as the urgency and importance of the task, so as to ensure that the critical or high-priority commands are executed first. The efficiency priority principle is based on how to schedule tasks to achieve the highest efficiency of resource utilization, that is, to give priority to those commands that can be completed with the least resource consumption or the shortest time, thereby improving the overall work efficiency of the system.

[0048] In summary, the first embodiment of the present invention provides a dynamic mapping method for multi-bank access, which obtains the address of the target memory bank bank0 by parsing the access request command cmd0; if the number of state machines of the currently allocated memory bank bank is greater than the preset allocation threshold, a mapping relationship between the bank0 and the target state machine FSM0 is established through dynamic mapping. The steps of dynamic mapping include: if there is a state machine of an unallocated bank, an unallocated bank state machine FSM0 is allocated to the bank0, and a mapping relationship between the FSM0 and the bank0 is established; at the same time, the state machine FSM i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i If there is no state machine with an unallocated bank, cmd0 is placed in a waiting queue to wait for a state machine with an unallocated bank. Through dynamic mapping, the number of state machines does not need to increase linearly one-to-one with the increase in the number of banks, thereby reducing the area overhead caused by the surge in the number of state machines. The reduction in the number of state machines also improves the timing of logic design.

[0049] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0050] Embodiment 1 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0051] Embodiment 1 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0052] Embodiment 2

[0053] A second embodiment of the present invention provides a multi-bank access dynamic mapping system, the system comprising a command storage unit, a mapping management table unit, a mapping and demapping logic unit, a dynamic mapping execution unit and a refresh management unit.

[0054] Furthermore, the command storage unit is used to store a command queue and a waiting queue, and the commands in the command queue carry the address of the target memory bank.

[0055] It should be noted that the command queue and waiting queue in the first embodiment are also applicable to the second embodiment and will not be described in detail.

[0056] The address of the target memory bank is the same as that in the first embodiment and will not be described in detail.

[0057] Furthermore, the mapping management table unit is used to record and manage the mapping relationship between the state machine and the memory bank.

[0058] The mapping management table records the current multiple mapping relationships in the memory controller, each of which is a mapping relationship between a state machine and a bank. The mapping management table will synchronize the state of each bank in the current mapping relationship to the dynamic mapping execution unit and the refresh management unit. If the existing mapping relationship is subsequently released and a new mapping relationship is rebuilt, the newly created mapping relationship will also be synchronized to the mapping management table in a timely manner.

[0059] Further, a mapping and demapping logic unit is used to obtain an access request command cmd0 from the command queue. If the number of mapping relationships in the mapping management table unit is greater than a preset allocation threshold, it is determined whether there is a state machine with an unallocated bank. If so, an unallocated bank state machine FSM0 is allocated to the target memory bank bank0 of cmd0. The FSM0 establishes a mapping relationship between FSM0 and bank0 by binding the address of bank0, so that the FSM0 tracks and manages the access status of bank0. At the same time, the state machine FSM0 is released. i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. iIf there is no state machine of unallocated bank, the cmd0 is placed in the waiting queue to wait for the state machine of unallocated bank; the established mapping relationship and the released mapping relationship are sent as dynamic mapping information to the dynamic mapping execution unit.

[0060] The function of the mapping and demapping logic unit is the same as that of S200 in the first embodiment, and will not be described in detail.

[0061] As a preferred embodiment, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between include: when the FSM i An access request is detected hitting an activated bank i When FSM is not released i With bank i The mapping relationship between them; until the current continuous access ends, the FSM is released i With bank i The mapping relationship between them.

[0062] As a preferred embodiment, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between the two also include: when there is a command that is about to time out in the command queue, and the target memory bank accessed by the command that is about to time out is bank i , without releasing the FSM i With bank i until no bank is accessed in the queue i After the command is about to time out, release the FSM i With bank i The mapping relationship between them.

[0063] As a preferred embodiment, the release state machine FSM i With bank i The mapping relationship between banks also satisfies the demapping conditions: i Can be interleaved with other commands in the command queue, then the FSM is not released i With bank i The mapping relationship between them.

[0064] Furthermore, the dynamic mapping execution unit is used to manage the legal switching between the established mapping relationship and the released mapping relationship according to the dynamic mapping information.

[0065] Among them, legal switching refers to the process of flexibly and efficiently reallocating resources and control logic to adapt to the seamless transition of dynamic task requirements under the premise of ensuring data integrity and system stability. For example, state consistency check, state machine synchronization, timing and protocol compliance, resource release and allocation, etc. Among them, state consistency check is used to first verify whether the current system state allows such operations before trying to switch the mapping relationship; ensure that there are no ongoing read and write operations or in a critical state (such as refresh cycle) to avoid data loss or damage. State machine synchronization is used to ensure that the state of the state machine is consistent with the new mapping relationship and correctly reflects the current Bank's active state, including updating the internal state of the state machine, control signals and timing parameters. Timing and protocol compliance is used to switch the mapping relationship in strict accordance with the timing specifications of the memory controller and DRAM, including but not limited to the precharge cycle, the delay from activation to read and write commands, etc., to avoid errors caused by timing violations. Resource release and allocation is used to release all hardware resources associated with it before releasing the mapping relationship, such as the occupation of control lines, address buses and data buses, and then efficiently reallocate these resources when establishing a new mapping relationship.

[0066] As a preferred embodiment, the dynamic mapping execution unit is also used to synchronize the mapping relationship established after execution to the mapping management table unit, and synchronize the mapping relationship released after execution to the refresh management unit. The established mapping relationship is synchronized to the mapping management table unit, so that it can schedule memory resources more efficiently, allocate appropriate banks for new tasks or processes, and improve the utilization efficiency of system resources. The released mapping relationship is synchronized to the refresh management unit, which can reduce operational errors and system failures that may be caused by information asynchronization.

[0067] As a preferred embodiment, the dynamic mapping execution unit is also used to synchronize the state information of the state machine of the de-mapping relationship to the refresh management unit. In this way, the refresh management unit can accurately know which banks have been de-mapped based on the latest state information, so that the refresh operation is only performed on the valid banks that need to be maintained, avoiding invalid processing of de-mapped or invalid banks, and improving the efficiency and accuracy of the refresh operation.

[0068] Furthermore, the refresh management unit is used to manage the refresh operation of the bank after the mapping relationship is released.

[0069] Among them, for the bank that has been unmapped, the data stored in it still exists and must remain valid for possible future remapping and use. If it is not refreshed, the data stored in the bank may become unreliable due to charge loss, eventually leading to data errors or even loss.

[0070] As a preferred embodiment, the system further includes: an access management unit, which is used to classify and manage the categories of access request commands according to the current state of the state machine and assign label information to the command storage unit. It should be noted that the access management unit classifies the access commands according to the current state of the Bank and the command type, and adds a specific label to each type of command. The label information can help the command storage unit to parse and execute commands more effectively, and also facilitate subsequent management and optimization, such as giving priority to high-priority commands.

[0071] Optionally, the label information is a priority label, an operation type label, a timeout label, etc. Other label information also falls within the protection scope of the present invention.

[0072] As a preferred embodiment, the access management unit is also used to obtain a new command, and when the priority of the existing command in the command queue is higher than the new command, the new command is added to the waiting queue. By giving priority to high-priority tasks, limited system resources can be used more efficiently.

[0073] In summary, the second embodiment of the present invention provides a dynamic mapping system for multi-bank access, which includes a command storage unit, a mapping management table unit, a mapping and demapping logic unit, a dynamic mapping execution unit and a refresh management unit. The system dynamically establishes a mapping relationship between a state machine and a bank, and then releases a mapping relationship, so that the target bank accessed by a command in a memory controller can always be assigned a corresponding state machine. The number of state machines does not need to increase linearly one-to-one with the increase in the number of banks, thereby reducing the area overhead caused by the surge in the number of state machines. The reduction in the number of state machines also improves the timing of logic design.

[0074] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0075] Embodiment 2 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0076] Embodiment 2 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0077] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0078] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A dynamic mapping method for multi-bank access, characterized in that: The method comprises the following steps: S100, parsing the access request command cmd0, and obtaining the address of the target memory bank bank0 to be accessed; S200, if the number of state machines currently allocated to the memory bank bank is greater than a preset allocation threshold, a mapping relationship between the bank0 and the target state machine FSM0 is established through dynamic mapping, the dynamic mapping step comprising: S210, if there is currently a state machine with an unassigned bank, an unassigned bank state machine FSM0 is assigned to the bank0, and the FSM0 establishes a mapping relationship between the FSM0 and the bank0 by binding the address of the bank0, so that the FSM0 tracks and manages the access to the bank0; at the same time, the state machine FSM0 is released i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i ; S220, if there is no state machine of an unallocated bank currently, the cmd0 is put into a waiting queue to wait for a state machine of an unallocated bank that is released after the mapping relationship is released.

2. The method according to claim 1, characterized in that The S220 also includes: S221, when there is an unallocated bank state machine FSM j When a candidate access request command cmd is taken out from the waiting queue w,j ; S222, obtaining the cmd w,j The address of the target bank; S223, compare the address of the target bank with the FSM j Establish a mapping relationship between them.

3. The method according to claim 2, characterized in that In S221, the cmd is taken out from the waiting queue. w,j Follow the principle of performance priority.

4. The method according to claim 1, characterized in that In S210, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between include: When the FSM i An access request command is detected hitting an activated bank i When the FSM is not released i With bank i The mapping relationship between them; until the current continuous access ends, the FSM is released i With bank i The mapping relationship between them.

5. The method according to claim 1, characterized in that: In S210, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between them also include: When there is a command in the command queue that is about to time out, and the target memory bank accessed by the command that is about to time out is bank i , without releasing the FSM i With bank i until no bank is accessed in the queue i After the command is about to time out, release the FSM i With bank i The mapping relationship between them.

6. The method according to claim 1, characterized in that In S210, the release state machine FSM i With bank i The demapping conditions satisfied by the mapping relationship between them also include: If bank i If it can be interleaved with other commands in the command queue, the FSM will not be released. i With bank i The mapping relationship between them.

7. The method according to claim 1, characterized in that The method further comprises: S10, obtaining a new command, and when the priority of an existing command in the command queue is higher than that of the new command, adding the new command to the waiting queue.

8. The method according to claim 3, characterized in that The effectiveness priority principle is a command priority principle or an efficiency priority principle.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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