FINFET with fin height in drain region lower than fin height in source region and related method

Abstract

The present disclosure provides a FINFET in which the fin height in the drain region is lower than the fin height in the source region and a related method. A FinFET includes a semiconductor fin, and a source region and a drain region located in the same semiconductor fin. The drain region has a first fin height located above the trench isolation; and the source region has a second fin height located above the trench isolation. The first fin height is less than the second fin height. FinFETs can be used, for example, in scaled lateral diffused metal oxide semiconductor (LDMOS) applications and exhibit reduced parasitic capacitance for improved radio frequency (RF) performance. The drain extension region can have a first fin height, and the channel region can have a second fin height. A method for manufacturing a FinFET is also disclosed.

Description

Technical Field

[0001] This disclosure relates to power amplifier devices, and more specifically, to fin field-effect transistors (FinFETs) having semiconductor fins in which the drain region has a lower fin height than the source region in the same fin, located above trench isolation. The lower fin height in the drain region and drain extension reduces gate-drain parasitic capacitance. Background Technology

[0002] Radio frequency (RF) devices employ laterally diffused metal-oxide-semiconductor (LDMOS) FinFETs. An LDMOS device includes a p-well with a source region and an n-well with a drain region within the semiconductor fin. A gate extends over both the p-well and n-well, with a channel in the p-well and a relatively long drain extension in the n-well. The longer drain extension reduces gate-drain capacitance and improves RF gain. The longer drain extension can be formed in various forms within an LDMOS device. For example, an LDMOS shallow trench isolation (LDMOS-STI) device includes shallow trench isolation (STI) within the drain extension region in the n-well of the device, while an LDMOS dummy gate (LDMOS-DP) device does not have an STI in the n-well but includes a second floating (dummy) gate located above the drain extension region in the n-well of the device.

[0003] For example, LDMOS FinFETs are used as power amplifiers for wireless networks with power outputs of 3.3-5 volts. One challenge these devices face is that the longer drain extension introduces higher on-resistance (R0). on This reduces the power efficiency of power amplifier applications. To address this, scaled LDMOS FinFETs without STI or dummy gates are preferred because they significantly reduce Ri by using a lower drain extension region. on However, scaling up LDMOS FinFETs also disadvantageously increases the gate-drain parasitic capacitance (C). gd And reduce RF gain. Summary of the Invention

[0004] One aspect of this disclosure relates to a fin field-effect transistor (FinFET) comprising: a semiconductor fin having trench isolation adjacent to it; a drain region located in the semiconductor fin having a first fin height above the trench isolation; a source region located in the same semiconductor fin as the drain region having a second fin height above the trench isolation, wherein the first fin height is less than the second fin height; and a gate extending across the semiconductor fin.

[0005] Another aspect of this disclosure includes a laterally diffused metal-oxide-semiconductor (LDMOS) fin field-effect transistor (FinFET) comprising: a semiconductor fin having a trench isolation adjacent thereto; a drain region located in the semiconductor fin having a first fin height above the trench isolation; a source region located in the same semiconductor fin as the drain region having a second fin height above the trench isolation; a drain extension region located in the same semiconductor fin as the source and drain regions having the first fin height above the trench isolation; a gate extending across the semiconductor fin; and a channel region located in the same semiconductor fin as the source and drain regions and below the gate region, the channel region being located between the drain extension region and the source region, the channel region having the second fin height above the trench isolation, wherein the first fin height is less than the second fin height.

[0006] Another aspect of this disclosure relates to a method comprising: forming a trench isolation adjacent to a semiconductor fin to create a first fin height over the trench isolation in a first region of the semiconductor fin, and creating a second fin height over the trench isolation in a second region of the semiconductor fin, wherein the first fin height is less than the second fin height; and forming a fin field-effect transistor (FinFET) using the semiconductor fin having a drain region located in the first region and a source region located in the second region.

[0007] The foregoing and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein the same reference numerals denote the same elements, and wherein:

[0009] Figure 1 A schematic plan view of the overall layout of a FinFET is shown for the purpose of describing embodiments of the present disclosure.

[0010] Figures 2A to 2B The respective traverses according to embodiments of the present disclosure are shown. Figure 1 The cross-sectional view of the recessed trench isolation cut by lines AA and BB in the figure.

[0011] Figures 3A to 3B The respective traverses according to embodiments of the present disclosure are shown. Figure 1 The cross-sectional view of another recessed trench isolation cut by lines AA and BB in the middle.

[0012] Figure 4The following is illustrated according to an embodiment of the present disclosure. Figure 1 The image shows a cross-sectional view of the step located in the trench isolation adjacent to the semiconductor fin, taken by line DD.

[0013] Figure 5 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The cross-sectional view of the line CC in the diagram forms a dummy gate.

[0014] Figure 6 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The cross-sectional view of the line DD in the diagram forms a dummy gate.

[0015] Figure 7 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The cross-sectional view of the source / drain region formed by the line CC in the diagram.

[0016] Figure 8 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The image shows a cross-sectional view of the source / drain regions formed by the line DD.

[0017] Figure 9 A cross-sectional view of the drain region epitaxial portion according to an embodiment of the present disclosure is shown.

[0018] Figure 10 A cross-sectional view of the source region epitaxial portion according to an embodiment of the present disclosure is shown.

[0019] Figure 11 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The image shows a cross-sectional view of a FinFET and a scaled LDMOS FinFET, taken from the CC line.

[0020] Figure 12 The following is illustrated according to an embodiment of the present disclosure. Figure 1 The image shows a cross-sectional view of a FinFET and a scaled LDMOS FinFET, taken from the line DD.

[0021] Note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals denote the same elements between the figures. DETAILED DESCRIPTION

[0022] In the following description, reference is made to the accompanying drawings, which form a part of this disclosure, and specific exemplary embodiments in which the present teachings can be practiced are illustrated. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely exemplary.

[0023] It will be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, it can be directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly above" another component, there are no intermediate components. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0024] References to "one embodiment" or "embodiment" and other variations thereof in the specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrase "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of any of the following, such as "A / B," "A and / or B," and "at least one of A and B," is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As a further example, in the cases of “A, B and / or C” and “at least one of A, B and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0025] Embodiments of this disclosure provide a FinFET including a semiconductor fin and a source region and a drain region located within the semiconductor fin. A gate extends across the semiconductor fin. Capacitive coupling (C) exists between the gate and the epitaxial drain region. pc -epi) for gate-drain parasitic capacitance (C gdThe gate-drain parasitic capacitance (C) has a significant impact and is the only parasitic capacitance component of a FinFET. Embodiments of this disclosure provide a drain region with a first fin height located above the trench isolation; and a source region with a second fin height located above the trench isolation. The first fin height is smaller than the second fin height. For example, the lower fin height in the drain region and drain extension region of a scaled LDMOS FinFET significantly reduces the gate-drain parasitic capacitance (C). gd Therefore, FinFETs used in scaled LDMOS applications, such as those for power amplifiers, exhibit reduced parasitic capacitance to improve radio frequency (RF) performance. The channel region of an LDMOS FinFET can also have a second fin height.

[0026] Figures 1 to 12 FinFET 100 is formed according to various embodiments of this disclosure. Figure 1 , Figures 11 to 12 ) and LDMOS FinFET 102 ( Figure 1 , Figures 11 to 12 A diagram illustrating the FinFET 100 method. For descriptive purposes, the FinFET 100 ( Figure 1 , Figures 11 to 12 It can be implemented as a scaled LDMOS FinFET 102. Figure 1 , Figures 11 to 12 That is, in the case where there is no STI in the n-well or dummy gate. It should be emphasized that the teachings of this disclosure can also be applied to other types of MOS devices.

[0027] Figure 1 A schematic plan view of the overall layout of the FinFET 100 is shown for the purpose of describing embodiments of the present disclosure. Figure 1 This includes a set of view lines AA, BB, CC, and DD referenced for the purpose of describing this disclosure. Figure 1 A FinFET 100 is shown, which includes semiconductor fins 110 (e.g., four fins) extending across the page and a gate 112 extending across the semiconductor fins 110. Although four semiconductor fins 110 are shown, it should be understood that any number of trenches 144 can be created. Figure 2A To form any number of semiconductor fins 110. Figure 1 In the middle, view line AA will provide a higher fin height ( Figure 1 The source region 114 (not shown in the image) spans the semiconductor fin 110 (indicated by brackets indicating the length of the fin 110). View line BB is where a lower fin height will be provided ( Figure 1The drain region 116 (indicated by brackets indicating the length of fin 110) spans semiconductor fin 110. In the case where FinFET 100 is used as an LDMOS device, it may include a p-well 118 (dashed box) located within one longitudinal dimension of semiconductor fin 110, and an n-well 120 (dashed box) located within another longitudinal dimension of semiconductor fin 110. Drain extension region 122 is located in n-well 120 and below gate 112. Channel region 124 is located in p-well 118 and below gate 112. View line CC is a cross-sectional view along selected semiconductor fin 110, and view line DD is a cross-sectional view along trench isolation 126 located adjacent to semiconductor fin 110. For any particular stage of the method, the drawing number indicates the particular stage. Drawings with the symbol “A” span view line AA, and drawings with the symbol “B” span view line BB. Other drawings will refer to other view lines (CC, DD) where appropriate.

[0028] Figure 2A -B to Figure 3A -B illustrates the formation of a trench isolation 126 adjacent to the semiconductor fin 110 to create a first fin height FH1 above the trench isolation 126 in a first region 130 (e.g., drain region 116) of the semiconductor fin 110. Figure 2A -B、 Figure 3B ), and create a second fin height FH2 in the second region 132 (e.g., source region 114) of the semiconductor fin 110 above the trench isolation 126. Figure 3A Cross-sectional view of ).

[0029] Figure 2A -B shows a cross-sectional view of the preliminary structure 140. At this stage, semiconductor fins 110 have been formed on the semiconductor substrate 142 using any techniques now known or developed later. The semiconductor fins 110 and the substrate 142 may include, but are not limited to, silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of materials with the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Those comprising one or more III-V compound semiconductors with defined compositions, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates include those having the composition Zn. A1 Cd A2 Se B1 Te B2The semiconductor is a group II-VI compound semiconductor, where A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, some or all of the semiconductor fins and / or the substrate may be strained.

[0030] Despite Figure 2A -B and Figure 3A -B is not shown, but at this stage, an n-well 120 has already been formed in the semiconductor fin 110. Figure 1 ) and p-well 118 ( Figure 1 P-well 118 may include p-type dopant, which may include, but is not limited to, boron (B), indium (In), and gallium (Ga); n-well 120 may include n-type dopant, which may include, but is not limited to, phosphorus (P), arsenic (As), or antimony (Sb). Wells 118 and 120 may be formed using any semiconductor doping techniques now known or developed in the future (e.g., ion implantation and / or in-situ doping).

[0031] Trench isolation 126 is formed between adjacent semiconductor fins 110 to electrically separate the adjacent semiconductor fins 110. Trench isolation 126 may include any form of trench isolation, such as shallow trench isolation (STI) located between semiconductor fins 110. Trench isolation 126 may include any interlayer dielectric now known or developed later. Suitable dielectric materials may include, but are not limited to: silicon dioxide; carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymer thermosetting materials; silicon carbide; SiCOH dielectric; fluorine-doped silicon oxide; spin-coated glass; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB) based polymer dielectrics; and any silicon-containing low-k dielectric. Examples of spin-coated low-k films with SiCOH type components using silsesquioxane chemistry include HOSP. TM (Available from Honeywell), JSR5109 and 5108 (Available from Japan Synthetic Rubber), Zirkon TM (Available from Shipley Microelectronics, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond. TM (Available from Applied Materials) and CoralTM (Available from Lam Research). An example of HSQ material is FOX. TM (Available from Dow Corning). In a non-limiting example, the formation of trench isolation 126 may include performing in-situ vapor generation (ISSG) oxidation, polysilicon liner deposition, and dielectric (in trench 144 between semiconductor fins 110). Figure 2A Flowable chemical vapor deposition (FCVD) and annealing for improving the quality of dielectric materials. Other dielectric formation processes can be used.

[0032] Figures 2A to 2B Also shown is the formation of a trench isolation 126 adjacent to the semiconductor fin 110 to create a first fin height FH1 above the trench isolation 126 in the first and second regions 130, 132 of the semiconductor fin 110. Figure 1 As shown, each region 130, 132 includes a longitudinal extent of the semiconductor fin 110. Any desired first fin height FH1 for the first region 130 (e.g., drain region 116 or drain extension region 122) can be created by controlling the etching employed. As described above, the first fin height FH1 will ultimately be the lower fin height located between regions 130, 132 in each respective semiconductor fin 110. Recessing may include etching the dielectric of the trench isolation 126.

[0033] Etching generally refers to the removal of material from a substrate (or a structure formed on the substrate) and is typically performed using an in-place mask to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid), where the solvent can be selected based on its ability to selectively dissolve a given material (e.g., oxide) while leaving other materials (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates electrically neutral high-energy radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputtering etching utilizes high-energy ions of a rare gas to bombard the wafer. These ions approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to produce deep, narrow features. Recessing can include using any suitable etching chemistry, such as RIE, for the dielectric of trench isolation 126.

[0034] refer to Figure 2B In which a lower first fin height FH1 is desired above the trench isolation 126 ( Figure 3B A mask 146 is formed over the first region 130 of the wafer. The mask 146 may include any mask material layer now known or developed later, such as a spin-coated hard mask (SOH). The mask material may be formed over the entire wafer and patterned to cover the area where a lower fin height FH1 is ultimately desired to be located above the trench isolation 126. Figure 3B The first region 130, and exposes the desired higher fin height FH2 within it. Figure 3A The second region 132 of the mask 146. In one embodiment, the edge 147 of the mask 146 ( Figure 1 This defines the transition between the first fin height FH1 and the second fin height FH2. Edge 147 ( Figure 1 The transition is located above the gap 113 between the p-well 118 and the n-well 120 in the semiconductor fin 110. As will be further described herein, this transition creates a step 148 in the trench isolation 126 adjacent to the semiconductor fin 110. Figure 3B and Figure 4Although step 148 is shown as vertical, it should be understood that some angling and / or undulation of the surface is also possible.

[0035] Figures 3A to 3B The trench isolation 126 adjacent to the semiconductor fin 110 is further recessed to create a second fin height FH2 above the trench isolation 126 in the second region 132 of the semiconductor fin 110 (e.g., source region 114 and channel region 124). Figure 3A A cross-sectional view of the result. Recessing can include using any suitable etch chemistry, such as RIE, against the dielectric of trench isolation 126. As shown, recessing further deepens trench 144 by removing the dielectric of trench isolation 126. Any desired depth for the second region 132 (e.g., source region 114) can be created by controlling the etching employed. For example, the first fin height FH1 can be between 40% and 60% of the second fin height FH2, and more specifically, can be approximately 50% of the second fin height FH2. In most cases, the higher second fin height FH2 is the height normally used for FinFETs at any particular technology node. Figure 3B In this process, mask 146 has been removed from the first region 130, resulting in the retention of the first fin height FH1 above the trench isolation 126 in the first region 130 of the semiconductor fin 110. Mask 146 can be removed using any suitable process (e.g., ashing process).

[0036] To further illustrate the transition created within trench isolation 126, Figure 4 The trench isolation 126 superimposed on the adjacent semiconductor fin 110 is shown along Figure 1 A schematic cross-sectional view of line DD in the diagram. Parentheses indicate the locations of p-well 118, n-well 120, and the gap 113 between the wells. Although not shown for clarity, the source region 114 and the channel region 124 ( Figure 1 The drain region 116 and the drain extension region 122 will be located in a portion of the p-well 118 of the semiconductor fin 110. Figure 1 The transition between the first fin height FH1 and the second fin height FH2 is located in the n-well 120 of the semiconductor fin 110. As shown, the transition between the first fin height FH1 and the second fin height FH2 is located in the gap 113 between the p-well 118 and the n-well 120 in the semiconductor fin 110. The transition creates a step in the trench isolation 126 adjacent to the semiconductor fin 110.

[0037] Figures 5 to 10 This illustrates the formation of a FinFET 100 using a semiconductor fin 110 having a drain region 116 located in a first region 130 and a source region 114 located in a second region 132. Figures 11 to 12 Cross-sectional view of FinFET 100. Figures 11 to 12 This can be formed using any semiconductor processing technique now known or developed later. For simplicity, this document will only describe one non-limiting example of a process in the form of a replacement metal gate (RMG) process. The RMG process can include any RMG technique now known or developed later, and therefore will not be described in detail here. The RMG process can include, for example, forming a dummy gate 150 on semiconductor fin 110. It should be understood that the dummy gate 150 is placed to reserve a location for the final metal gate and to allow for processes that might otherwise damage the metal gate.

[0038] Figure 5 The edge of the dummy gate 150 located above a portion of the p-well 118, the gap 113, and a portion of the n-well 120 is shown. Figure 1 A cross-sectional view of line CC in the diagram; Figure 6 The edge of the dummy gate 150 above the step 148 in the trench isolation 126 is shown. Figure 1 A cross-sectional view of line DD in the diagram. A gate dielectric layer 152 may be formed on the semiconductor fin 110. The gate dielectric layer 152 may, for example, comprise silicon oxide. The dummy gate 150 may comprise a sacrificial material block 154, such as polycrystalline or amorphous silicon, and a cap layer 156 (e.g., silicon nitride) on top of the sacrificial material block 154. The dummy gate 150 may be shaped using any patterning process now known or developed later.

[0039] Figures 7 to 10 Cross-sectional views of the source / drain regions 114 and 116 are shown. Figure 7 This illustrates the formation of source / drain regions 114, 116 in the semiconductor fin 110. Figure 1 A cross-sectional view of line CC in the diagram; Figure 8 This illustrates the formation of source / drain regions 114, 116 in the semiconductor fin 110. Figure 1 A cross-sectional view of line DD in the diagram. Figure 9 This illustrates the formation of a drain region epitaxial portion 170 above the trench isolation 126 in the semiconductor fin 110. Figure 1 A cross-sectional view of line BB; Figure 10 This illustrates the process of forming the epitaxial portion 172 of the source region in the semiconductor fin 110. Figure 1A cross-sectional view of line AA. Drain region 116 is formed with a drain region epitaxial portion 170 located above trench isolation 126, and source region 114 is formed with a source region epitaxial portion 172 located above trench isolation 126. At this stage, dummy gate 150 has been trimmed to the desired shape and isolation material 160 (e.g., silicon nitride) has been added. Source / drain regions 114, 116 can be formed using any semiconductor doping technique now known or developed later. For example, source / drain regions 114, 116 can be formed by mask-oriented doping, where ion implantation is performed followed by doping (e.g., annealing to drive in dopant). Source / drain regions 114, 116 can be doped with n-type dopant, such as dopant concentrations higher than those of n-well 120. Since these implantation steps are well known in the art, no further details are provided.

[0040] Furthermore, source / drain regions 114 and 116 can be formed by epitaxial growth on semiconductor fins 110. The terms "epitaxygmal growth" and "epitaxygmal formation and / or growth" refer to the growth of semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has the same crystallinity as the semiconductor material on the deposition surface. During epitaxial growth, the chemical reactants provided by the source gas are controlled and system parameters are set so that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move on the surface and orient themselves towards the crystal arrangement of atoms on the deposition surface. Therefore, the epitaxial semiconductor material can have the same crystallinity as the deposition surface, wherein the epitaxial semiconductor material can be formed on the deposition surface. Here, due to different fin heights FH1, FH2 ( Figure 3A -B), such as Figure 1 , Figure 9 and Figure 10 As shown, the drain region epitaxial portion 170 is formed with a first width W1, and the source region epitaxial portion 172 is formed with a second width W2. As shown, because the second fin height FH2 ( Figure 3A The second width W2 of the source pole region epitaxial portion 172 is larger than that of the first fin height FH1. Figure 3B The first width W1 of the drain region epitaxial portion 170 is [width]. Similarly, the source region epitaxial portion 172 may also be higher than the drain region epitaxial portion 170. For example... Figure 9 As shown, the drain region 116 may include another drain region extension 174 extending below the upper surface 176 of the trench isolation 126.

[0041] refer to Figure 11 and Figure 12 The RMG process continues. A dummy gate of 150 ( Figures 7 to 8The dummy gate 150 can be removed using any process now known or developed later (e.g., any "dummy gate pull" technique). In one example, the dummy gate 150 is etched away. In this case, the dummy gate 150 can be removed, for example, by RIE. Gate 112 (more specifically, a metal gate) can be formed at the location vacated by the dummy gate 150. Gate 112 may include a gate dielectric layer 152. Gate dielectric layer 152 may also include any high dielectric constant (high K) material now known or developed later, such as, but not limited to: metal oxides, such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3); or metal silicates, such as hafnium oxide (HfO2). A1 Si A2 O A3 ) or hafnium silicate oxynitride (Hf A1 Si A2 O A3 N A4 A1, A2, A3, and A4 represent relative proportions, each greater than or equal to zero, and A1 + A2 + A3 + A4 (where 1 is the total relative molar amount). Gate 112 may also include one or more conductive elements 178 for providing a gate terminal for the transistor. For example, although not shown for clarity, gate 112 may include a work function metal layer and a gate conductor situated above the work function metal. Depending on whether it is for an NFET or PFET device, the work function metal layer may include various metals, but may include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polysilicon (poly-Si), and / or combinations thereof. The gate conductor may include any gate conductor now known or developed later, such as copper (Cu). For example, a nitride gate cap (not shown) may also be formed on gate 112.

[0042] Forming the gate 112 for the FinFET 100 also includes forming a drain extension region 122 adjacent to the drain region 116 in the n-well 120 of the first region 130. The drain extension region 122 has a lower first fin height FHl. Figure 3B The drain extension region 122 extends from the edge 184 of the n-well 120 to the drain region 116. The gate 112 forming for the FinFET 100 also includes a channel region 124 formed adjacent to the source region 114 in the p-well 118 of the second region 132. Therefore, the channel region 124 has a higher second fin height FH2. Figure 3A ).

[0043] Additional processing may include forming any now-known or later-developed interconnects in the dielectric layer (not shown) above the FinFET 100 and LDMOS FinFET 102.

[0044] refer to Figure 1 , Figure 11 and Figure 12 The following describes a FinFET 100 according to embodiments of the present disclosure. As described above, the FinFET 100 can be used as a laterally diffused metal-oxide-semiconductor (LDMOS) FinFET 102, which also... Figure 1 , Figure 11 and Figure 12 As shown in the figure. FinFET 100 may include a semiconductor fin 110 having a trench isolation 126 adjacent to it. FinFET 100 may also include a drain region 116 located in the semiconductor fin 110, wherein the drain region 116 has a first fin height FH1 located above the trench isolation 126. Figure 3B The FinFET 100 also includes a source region 114 located in the same semiconductor fin 110 as the drain region 116, wherein the source region 114 has a second fin height FH2 located above the trench isolation 126. As described, the first fin height FH1 is smaller than the second fin height FH2, resulting in an asymmetric device. The first fin height FH1 ( Figure 3B The height of the second fin can be between 40% and 60%, for example, about 50%, of the second fin height FH2. The FinFET 100 also includes a gate 112 extending across the semiconductor fin 110.

[0045] The FinFET 100 may also include a drain extension region 122 located in the n-well 120 of the semiconductor fin 110. The drain extension region 122 is located in the first region 130 and therefore has a lower first fin height FHl. Figure 3B The channel region 124 is located below the gate 112 in the semiconductor fin 110 and between the source region 114 and the drain extension region 122. The channel region 124 is located in the second region 132 and therefore has a second fin height FH2. Figure 3A As described, the channel region 124 is located in the p-well 118 of the semiconductor fin 110, and the first fin height FH1 ( Figure 3B ) and second fin height FH2 ( Figure 3A The transition between the two is located in the gap 113 between the p-well 118 and the n-well 120 in the semiconductor fin 110. Figure 1 and Figure 11 (in) . respectively as Figure 9 and Figure 10As shown, the drain region 116 may further include a drain region epitaxial portion 170 located above the trench isolation 126, and the source region 114 may include a source region epitaxial portion 172 located above the trench isolation 126. The source region epitaxial portion 172 is wider than the drain region epitaxial portion 170, i.e., W2 > W1. Figure 9 As shown, the drain region 116 may include another drain region extension 174 extending below the upper surface 176 of the trench isolation 126. Figure 3A As shown in Figure -B, the trench isolation 126 has a first isolation height IH1 relative to the bottom 180 adjacent to the drain region 116 of the semiconductor fin 110 and a second isolation height IH2 relative to the bottom 180 adjacent to the source region 114 of the semiconductor fin 110. Due to the varying recessed shape of the trench isolation 126, the first isolation height IH1 is greater than the second isolation height IH2, which defines a step 148 located in the trench isolation 126 adjacent to the semiconductor fin 110. Figure 3B and Figure 4 ).like Figure 12 As shown, the gate 112 extends over a step 148 in a trench isolation 126 adjacent to the semiconductor fin 110.

[0046] Embodiments of this disclosure provide a FinFET 100, which, among other uses, can be used with a scaled LDMOS FinFET 102 for RF applications such as power amplifiers. The FinFET 100, having a lower fin height in, for example, the drain region 116 and drain extension region 122 of the scaled LDMOS FinFET 102, significantly reduces the gate-drain parasitic capacitance (C). gd Therefore, FinFET exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. Furthermore, FinFET 100 exhibits improved RF power gain.

[0047] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the said feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that an event or condition subsequently described may or may not occur, and the description includes instances where the event occurs and instances where the event does not occur.

[0049] As used throughout the specification and claims, approximate language may be used to modify any quantitative representation that may vary within permissible ranges without causing a change in the essential function it relates to. Therefore, values ​​modified by one or more terms such as “approximately,” “about,” and “substantially” are not limited to the specified precise values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Range limitations may be combined and / or interchanged herein and throughout the specification and claims, and such ranges are identified as including all subranges contained herein unless otherwise indicated by context or language. Unless otherwise dependent on the precision of the instrument used to measure the value, “approximately” applied to a particular value within a range simultaneously modifies two values ​​representing + / - 10% of said value.

[0050] All means or steps plus functional elements in the claims are intended to include any structure, material, action, and equivalent for performing a function in combination with other claimed elements of the specific claims. The description of this disclosure has been given for purposes of illustration and description, but it is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of this disclosure and to enable others skilled in the art to understand various embodiments of this disclosure with various modifications suitable for the contemplated particular purpose.

Claims

1. A fin field effect transistor FinFET, comprising: a semiconductor fin having trench isolation adjacent thereto; a drain region located in the semiconductor fin, the drain region having a first fin height located above the trench isolation; a source region located in the same semiconductor fin as the drain region, the source region having a second fin height located above the trench isolation, wherein the first fin height is less than the second fin height; and A gate extends across the semiconductor fin.

2. The fin field effect transistor FinFET according to claim 1, wherein: The first fin height is between 40% and 60% of the second fin height.

3. The fin field effect transistor FinFET according to claim 1, wherein: The drain region is adjacent to a drain extension region in an n-well of the semiconductor fin, wherein the drain extension region has the first fin height.

4. The fin field effect transistor FinFET according to claim 3, further comprising: A channel region is located in the semiconductor fin below the gate and between the source region and the drain extension region, wherein the channel region has the second fin height.

5. The fin field effect transistor FinFET according to claim 4, wherein: The channel region is located in a p-well of the semiconductor fin, and wherein a transition between the first fin height and the second fin height is located in a gap between the p-well and the n-well in the semiconductor fin.

6. The fin field effect transistor FinFET according to claim 1, wherein: The source region includes a source region epitaxial portion located above the trench isolation, and the drain region includes a drain region epitaxial portion located above the trench isolation, wherein the source region epitaxial portion is wider than the drain region epitaxial portion.

7. The fin field effect transistor FinFET according to claim 6, wherein: The drain region includes another drain region epitaxial portion extending below an upper surface of the trench isolation.

8. The fin field effect transistor FinFET according to claim 1, wherein: The trench isolation has a first isolation height relative to the bottom of the semiconductor fin adjacent to the drain region in the semiconductor fin and a second isolation height relative to the bottom of the semiconductor fin adjacent to the source region in the semiconductor fin, wherein the first isolation height is greater than the second isolation height, thereby defining a step located in the trench isolation adjacent to the semiconductor fin.

9. The fin field effect transistor FinFET according to claim 8, wherein: The gate extends over the step in the trench isolation adjacent to the semiconductor fin.

10. A lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET), comprising: a semiconductor fin having trench isolation adjacent thereto; a drain region located in the semiconductor fin, the drain region having a first fin height located above the trench isolation; a source region located in the same semiconductor fin as the drain region, the source region having a second fin height located above the trench isolation; a drain extension region located in the same semiconductor fin as the source region and the drain region, the drain extension region having the first fin height located above the trench isolation; a gate extending across the semiconductor fin; as well as a channel region located in the same semiconductor fin as the source region and the drain region and located below the gate, the channel region being located between the drain extension region and the source region, the channel region having the second fin height located above the trench isolation, Wherein, the first fin height is smaller than the second fin height.

11. The lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET) according to claim 10, wherein: The first fin height is between 40% and 60% of the second fin height.

12. The lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET) according to claim 10, wherein: The drain extension region is located in an n-well of the semiconductor fin, and the channel region is located in a p-well of the semiconductor fin.

13. The lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET) according to claim 12, wherein: A transition between the first fin height and the second fin height is located in a gap between the p-well and the n-well in the semiconductor fin.

14. The lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET) according to claim 10, wherein: The source region includes a source region epitaxial portion located above the trench isolation, and the drain region includes a drain region epitaxial portion located above the trench isolation, wherein the source region epitaxial portion is wider than the drain region epitaxial portion.

15. The lateral diffused metal oxide semiconductor (LDMOS) fin field effect transistor (FinFET) according to claim 10, wherein: The trench isolation in the drain region is higher than the trench isolation in the source region relative to a bottom of the semiconductor fin.

16. A method for forming a fin field effect transistor (FinFET), comprising: forming a trench isolation adjacent to a semiconductor fin to create a first fin height above the trench isolation in a first region of the semiconductor fin and a second fin height above the trench isolation in a second region of the semiconductor fin, wherein the first fin height is less than the second fin height, and the first region and the second region are located in the same semiconductor fin; and The FinFET is formed using the semiconductor fin having a drain region in the first region and a source region in the second region.

17. The method according to claim 16, wherein: Forming the FinFET further includes: forming a drain extension region adjacent to the drain region in the n-well of the first region, wherein the drain extension region has the first fin height; and A channel region is formed in the p-well of the second region adjacent to the source region, wherein the channel region has the second fin height.

18. The method according to claim 17, wherein: A transition between the first fin height and the second fin height is located in a gap between the p-well and the n-well in the semiconductor fin.

19. The method according to claim 16, wherein: The first fin height is between 40% and 60% of the second fin height.

20. The method according to claim 16, wherein: Forming the FinFET further includes forming the source region having a source region epitaxial portion located above the trench isolation, and forming the drain region having a drain region epitaxial portion located above the trench isolation, wherein the source region epitaxial portion is wider than the drain region epitaxial portion.

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