Method for forming sidewall structure of embedded flash memory

Abstract

The present invention provides a method for forming a sidewall structure of an embedded flash memory, wherein the embedded flash memory includes a flash memory area and a logic area, wherein the flash memory area includes a flash memory unit, and the logic area includes a logic unit. The method for forming the sidewall structure of the embedded flash memory includes: providing a layout of a floating gate layer and a layout of a logic gate layer of the embedded flash memory; determining the layout data of an actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer; selecting a corresponding sidewall material layer and a forming process of the sidewall structure according to the layout data of the actual sidewall material layer covering pattern and a preset width of the sidewall structure. By adopting an embodiment of the present invention, a suitable sidewall material layer and a forming process of the sidewall structure can be selected according to the obtained layout data of the actual sidewall material layer covering pattern and in combination with the preset width of the sidewall structure, thereby accurately controlling the width of the sidewall structure of the embedded flash memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a sidewall structure of an embedded flash memory. Background Art

[0002] In embedded flash memory, both the flash memory cells in the flash memory area and the logic cells in the logic area have spacer structures. The spacer structure (word line spacer structure, hereinafter referred to as spacer structure) in the flash memory cell is located on the side of the floating gate layer of the flash memory cell, and its width will greatly affect the anti-programming crosstalk performance (programdisturb inhibit) of the flash memory cell. If the width of the spacer structure of the flash memory cell is too narrow, it will also cause PTC (programming crosstalk failure). The spacer structure of the logic cell in the logic area is located on the side of the logic gate layer of the MOS cell, and its width has a great influence on the breakdown voltage (BV) of the logic cell (especially the high-voltage MOS cell, such as the 12V MOS cell). Increasing the width of the spacer structure is beneficial to improving the breakdown voltage (BV) of the logic cell.

[0003] At present, the above-mentioned sidewall structures in the flash memory unit and the logic unit are usually formed simultaneously, for example, a sidewall material layer of a certain thickness is deposited to at least cover the top surface and side surfaces of the floating gate layer and the top surface and side surfaces of the logic gate layer. Then, the sidewall material layer is etched to remove the sidewall material layer located on the above-mentioned top surface, so that the sidewall material layer remaining on the side surface is the sidewall structure.

[0004] In specific implementation, the same process for forming the sidewall material layer has a large difference in the thickness of the sidewall material layer formed on different embedded flash memory products, which in turn leads to a large difference in the width of the sidewall structure formed subsequently. The large difference is a big problem when selecting the process for forming the sidewall structure of the embedded flash memory. Moreover, the large difference also leads to large fluctuations in the anti-programming crosstalk performance and breakdown voltage performance of different embedded flash memory products. Summary of the invention

[0005] The object of the present invention is to provide a method for forming a sidewall structure of an embedded flash memory, so as to accurately control the width of the sidewall structure of the embedded flash memory.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a sidewall structure of an embedded flash memory, wherein the embedded flash memory includes a flash memory area and a logic area, the flash memory area includes a flash memory unit, and the logic area includes a logic unit. The method for forming the sidewall structure of the embedded flash memory includes: providing a layout of a floating gate layer and a layout of a logic gate layer of the embedded flash memory, the floating gate layer is located in the flash memory unit, and the logic gate layer is located in the logic unit; according to the layout of the floating gate layer and the layout of the logic gate layer, determining the layout data of an actual sidewall material layer covering pattern of the embedded flash memory, the actual sidewall material layer covering pattern is a pattern of the sidewall material layer covering the floating gate layer and the logic gate layer; according to the layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure, selecting a corresponding sidewall material layer and a formation process of the sidewall structure to form the sidewall structure.

[0007] Optionally, the layout data of the actual spacer material layer coverage pattern includes layout density of the actual spacer material layer coverage pattern and / or specific surface area data of the actual spacer material layer coverage pattern.

[0008] Optionally, the method for determining the layout density of the actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer includes: obtaining a first layout density according to the layout density of the logic gate layer; and obtaining a second layout density according to the layout density of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer, the layout density of the actual sidewall material layer covering pattern of the embedded flash memory being the sum of the first layout density and the second layout density.

[0009] Optionally, the second layout density is the product of the layout density of the floating gate layer, the expansion width coefficient of the floating gate layer, and the height difference coefficient.

[0010] Optionally, the method for determining the specific surface area data of the actual sidewall material layer coverage pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer includes: obtaining first specific surface area data according to the layout perimeter data of the logic gate layer; and obtaining second specific surface area data according to the layout perimeter data of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer, the specific surface area data of the actual sidewall material layer coverage pattern of the embedded flash memory is the sum of the first specific surface area data and the second specific surface area data.

[0011] Optionally, the second specific surface area data is the product of the layout perimeter data of the floating gate layer, the expansion width coefficient of the floating gate layer and the height difference coefficient.

[0012] Optionally, the height difference coefficient is the sum of the height of the flash memory unit and the height of the logic gate layer divided by the height of the logic gate layer.

[0013] Optionally, the expansion width coefficient is the sum of the widths of the bit line structure of the flash memory area and the floating gate layer of the flash memory area divided by the width of the floating gate layer of the flash memory area.

[0014] Optionally, the method for selecting the corresponding formation process of the side wall material layer according to the layout data of the actual side wall material layer covering pattern and the preset width of the side wall structure includes: establishing a data model of the layout data of the actual side wall material layer covering pattern and the width of the side wall structure according to the historical layout data of the actual side wall material layer covering pattern and the historical width data and historical formation process data of the corresponding side wall structure; and selecting the formation process of the side wall structure according to the data model and the layout data of the actual side wall material layer covering pattern.

[0015] Optionally, the method for selecting the forming process of the sidewall structure according to the data model and the layout data of the actual sidewall material layer covering pattern includes: selecting the forming process of the corresponding sidewall structure and obtaining the corresponding theoretical width of the sidewall structure according to the data model and the layout data of the actual sidewall material layer covering pattern; adjusting the forming process of the sidewall structure based on the theoretical width of the sidewall structure and the preset width of the sidewall structure.

[0016] In summary, the method for forming the sidewall structure of the embedded flash memory provided by the present invention has the following beneficial effects:

[0017] By providing the layout of the floating gate layer and the layout of the logic gate layer of the embedded flash memory; determining the layout data of the actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer; selecting the corresponding sidewall material layer and the formation process of the sidewall structure according to the layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure. According to the embodiment of the present invention, the appropriate sidewall material layer and the formation process of the sidewall structure can be selected according to the obtained layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure, so as to accurately control the width of the sidewall structure of the embedded flash memory.

[0018] Furthermore, in an embodiment of the present invention, the layout density or specific surface area data of the floating gate layer in the flash memory area and the logic gate layer in the logic area can be combined with their corresponding expansion width coefficients and height difference coefficients to accurately obtain the layout density or specific surface area data of the actual sidewall material layer covering pattern.

[0019] Furthermore, in an embodiment of the present invention, by utilizing the established layout data of the actual side wall material layer covering pattern, the thickness of the side wall structure layer, and the data model of the corresponding formation process, the actual side wall material layer covering pattern layout data of the new product and the preset width of the side wall structure are substituted, so that the appropriate side wall structure formation process can be conveniently and accurately selected. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0021] Figure 1 A flow chart of a method for forming a sidewall structure of an embedded flash memory provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of the embedded flash memory provided in an embodiment of the present application.

[0023] In the attached figure:

[0024] 10-substrate; 10a-flash memory area; 10b-logic area;

[0025] 20-logic gate layer; 31-floating gate structure; 31a-floating gate layer; 32-bit line structure;

[0026] 40-Side wall structure. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0029] The invention provides a method for forming a sidewall structure of an embedded flash memory, so as to accurately control the width of the sidewall structure of the embedded flash memory.

[0030] Figure 1 A flow chart of a method for forming a sidewall structure of an embedded flash memory provided in an embodiment of the present application.

[0031] like Figure 1 As shown, this embodiment provides a method for forming a sidewall structure of an embedded flash memory, comprising:

[0032] S01: providing a layout of a floating gate layer and a layout of a logic gate layer of the embedded flash memory, wherein the floating gate layer is located in the flash memory unit, and the logic gate layer is located in the logic unit;

[0033] S02: determining layout data of an actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer, wherein the actual sidewall material layer covering pattern is a pattern of the sidewall material layer covering the floating gate layer and the logic gate layer; and

[0034] S03: selecting a corresponding spacer material layer and a forming process of the spacer structure according to the layout data of the actual spacer material layer covering pattern and the preset width of the spacer structure to form the spacer structure.

[0035] The embedded flash memory in this embodiment may be an embedded split-gate flash memory, such as a word-gate (word-line) shared split-gate flash memory.

[0036] Please refer to Figure 2 The embedded flash memory includes a flash memory area 10a and a logic area 10b. A flash memory unit is formed in the flash memory area 10a for storing data, and a logic unit is formed in the logic area 10b for controlling and driving the flash memory unit. The flash memory unit includes a bit line structure 32 and a floating gate structure 31. The bit line structure 32 is connected to one side of the floating gate structure 31, and the word line structure to be formed later is connected to the other side of the floating gate structure 31 relative to the bit line structure 32. Among them, the bit line structure 32 includes a bit line and a corresponding bit line dielectric layer (not shown in the figure), the floating gate structure 31 includes a floating gate layer 31a and a floating gate dielectric layer located under the floating gate layer, a control gate dielectric layer located on the floating gate layer, a control gate layer and an isolation dielectric layer, etc. The sidewall structure 40 (word line sidewall layer) to be formed is located on one side of the word line structure, and the word line structure to be formed is isolated from the floating gate layer 31a by the sidewall structure 40. For the convenience of description, the sidewall structure 40 located in the flash memory area 10a is referred to as the word line sidewall layer.

[0037] Please refer to Figure 2, the logic unit may be, for example, a MOS unit, including a logic gate layer 20 and an active area structure, wherein the logic gate layer 20 covers the surface of the substrate 10, the logic gate layer 20 is isolated from the active area structure by a logic gate dielectric layer, the active area structure is formed in the surface of the substrate, the active area structure includes a conductive channel under the logic gate layer 20 and a source-drain structure connected to both sides of the conductive channel and located on both sides of the logic gate layer 20, and a sidewall structure 40 is subsequently formed to cover the sidewall of the logic gate layer. After the sidewall structure 40 is formed, the sidewall structure 40 may be used to perform further process treatment on the source-drain structure, such as forming a source-drain extension region (LDD), forming a source region, forming a self-aligned silicide, etc. Among them, the material of the sidewall structure 40 may be silicon oxide, silicon nitride, or a silicon oxide-silicon nitride-silicon oxide composite layer (ONO layer).

[0038] Preferably, the sidewall structure 40 of the flash memory area 10a and the sidewall structure 40 of the logic area 10b can be formed simultaneously, and the specific process is, for example: forming a sidewall material layer covering the substrate surface pattern (flash memory unit and logic unit) on the substrate surface of the flash memory area 10a and the logic area 10b, and then etching the sidewall material layer, leaving only the sidewall material layer located on the side of the logic gate layer 20 or the sidewall material layer located on the side wall of the floating gate structure 31, and thus forming the corresponding sidewall structure 40. It should be understood that the sidewall material layer is also retained on the side of the bit line structure 32, but Figure 2 Not shown in the figure.

[0039] The method for forming the sidewall structure of the embedded flash memory will be described in detail below with reference to the flow chart.

[0040] Embodiment 1

[0041] First, step S01 is performed to provide a layout of a floating gate layer and a layout of a logic gate layer of an embedded flash memory, wherein the floating gate layer is located in a flash memory unit, and the logic gate layer is located in a logic unit.

[0042] The layout of the floating gate layer and the layout of the logic gate layer can be obtained in the imported product layout information during the product stage of importing the embedded flash memory.

[0043] Next, step S02 is performed to determine the layout density of the actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer. The actual sidewall material layer covering pattern is the pattern of the sidewall material layer covering the floating gate layer and the logic gate layer. The specific method may include, for example:

[0044] S021: obtaining a first layout density according to the layout of the logic gate layer; and,

[0045] S022: Obtain a second layout density according to the layout of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer. The actual layout density of the sidewall material layer covering pattern of the embedded flash memory is the sum of the first layout density and the second layout density.

[0046] In step S021, the spacer material layer covers the logic gate layer in the logic area to form a spacer structure in the logic area. The layout of the logic gate layer can be directly used to represent the layout of the spacer material layer covering pattern in the logic area. Next, the layout area of ​​all logic gate layers in a reference unit area (e.g., a die) is compared with the reference unit area to obtain the layout density (percentage) of the logic gate layer as the first layout density, so as to facilitate comparison and calculation with the layout density of the same flash memory product or other flash memory products.

[0047] In step S022, a method similar to that in step S021 can be used to obtain the layout density of the floating gate layer of the flash memory area under the same reference unit area. Then, the layout density of the floating gate layer is multiplied by an expansion width coefficient to represent the layout density of the sidewall material layer covering pattern in the flash memory area, wherein the expansion width coefficient is the sum of the widths of the bit line structure of the flash memory area and the floating gate structure of the flash memory area divided by the width of the floating gate structure of the flash memory area. In specific implementation, the width of the floating gate layer in the layout can be used to represent the width of the floating gate structure. Preferably, the width of the bit line structure and the floating gate structure actually measured can be used to calculate the expansion width coefficient to improve the accuracy of the calculation. It should be understood that the sidewall material layer not only covers the floating gate structure in the flash memory area, but also covers the corresponding bit line structure, but the width of the bit line structure cannot be directly obtained using the layout information.

[0048] Further, the layout density of the sidewall material layer covering the pattern in the flash memory area obtained above is multiplied by a height difference coefficient to be used as the second layout density, wherein the height difference coefficient is the sum of the height of the bit line structure or floating gate structure of the flash memory area (higher than the substrate) and the height of the logic gate layer of the logic area divided by the height of the logic gate layer of the logic area. It should be understood that the key to selecting the sidewall material layer of the same formation process to cover the substrate area (including the flash memory area and the logic area) with the same layout density and the thickness of the sidewall material layer formed on the substrate area having a large difference is that the height of the pattern (layout) on the substrate surface is inconsistent, that is, the higher the height of the pattern on the substrate surface, the thinner the thickness of the sidewall material layer formed, which is equivalent to increasing the density of the pattern to reduce the thickness of the sidewall material layer. In practice, if the height of the bitline structure or the floating gate structure is inconsistent, it is represented by the arithmetic mean or weighted mean (with its width as the corresponding weight) of the height of the bitline structure and the height of the floating gate structure.

[0049] Then, the actual layout density of the sidewall material layer covering pattern of the embedded flash memory is the sum of the first layout density and the second layout density.

[0050] It should be noted that if the heights of the flash memory cells in the flash memory area or the logic cells in the logic area are different, the above-mentioned method can be used to group and calculate the layout density of the actual side wall material layer covering pattern of each according to the height of the flash memory cells or the logic cells, and then the layout densities of the above-mentioned different heights are added together as the layout density of the actual side wall material layer covering pattern of the embedded flash memory.

[0051] In a specific embodiment, the width of the bit line structure is 1400 angstroms, and the width of the floating gate structure (floating gate layer) is 2730 angstroms. The expansion width coefficient = (2730 + 1400) / 2730 = 1.51, the height of the logic gate layer is 1800 angstroms, and the heights of the bit line structure and the floating gate structure are 2250 angstroms. The height difference coefficient = (1800 + 2250) / 1800 = 1.25. It can be obtained that the actual polysilicon layout density of the sidewall material layer covering pattern = 1.51 * 1.25 * floating gate layer layout density + logic gate layer layout density.

[0052] Next, step S03 is executed to select the corresponding sidewall material layer and the formation process of the sidewall structure according to the layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure. In this embodiment, the layout data of the sidewall material layer covering pattern may be its layout density, and the specific method may include, for example:

[0053] S031: establishing a data model of the layout density of the actual spacer material layer covering pattern and the width of the spacer structure according to the historical layout density of the actual spacer material layer covering pattern and the historical width data and historical formation process data of the corresponding spacer structure;

[0054] S032: Selecting a forming process of the sidewall structure according to the data model and the layout density of the actual sidewall material layer covering pattern.

[0055] In step S031, based on the strong correlation between the thickness of the sidewall material layer (i.e., the width of the sidewall structure) and the breakdown voltage data in the WAT test, the breakdown voltage data of the embedded flash memory product can be used to represent the thickness of the corresponding sidewall material layer. Among them, the historical data of different embedded flash memory products under the same sidewall structure formation process can be selected as much as possible, and the variable factors are concentrated on the breakdown voltage data and the layout data of the sidewall material layer covering pattern to reduce the influence of other factors; then the above method is used to obtain the layout density of the actual sidewall material layer covering pattern from the historical data, and the layout density of the above actual sidewall material layer covering pattern is binary fitted with the corresponding breakdown voltage data to obtain the data model of the layout density of the actual sidewall material layer covering pattern and the width of the sidewall structure.

[0056] It should be noted that the above-mentioned process for forming the spacer structure may include a process for depositing the spacer material layer and a process for etching the spacer material layer.

[0057] In practice, multiple data models can be established by classifying or grouping the degree of fit of the layout density of different actual side wall material layer covering patterns according to different formation processes, so that a certain data model corresponds to a certain type (several types) of embedded products or a partial layout density range of a certain type of embedded products, so as to further improve the control accuracy of the width of the side wall structure of the embedded flash memory.

[0058] In a specific embodiment, the data model obtained by fitting the historical data can be, for example: breakdown voltage = -10.61722 + 0.9281161 * actual layout density of the sidewall material layer covering pattern, R 2 =0.687384.

[0059] In step S032, the preset breakdown voltage can be used to represent the preset width of the sidewall structure to improve the fit with the actual effect accordingly. The actual layout density of the sidewall material layer covering pattern is substituted into the above-mentioned data model with a higher fit to obtain the theoretical breakdown voltage under the formation process of the sidewall material layer, and the theoretical breakdown voltage is compared with the preset breakdown voltage, and then on this basis, the formation process of the sidewall material layer is fine-tuned to accurately control the thickness of the sidewall material layer.

[0060] Among them, if a certain embedded flash memory corresponds to multiple data models, the layout density of its actual side wall material layer covering pattern can be substituted into the above-mentioned multiple data models respectively, and the data model with the smallest difference between the theoretical width of the obtained side wall structure and the preset width can be selected to obtain the formation process of the side wall structure, so as to realize precise control of the width of the side wall structure.

[0061] Embodiment 2

[0062] The method for forming the sidewall structure of the embedded flash memory provided in the second embodiment is similar to that in the first embodiment, the difference is that the layout data of the actual sidewall material layer coverage pattern of the embedded flash memory determined according to the layout of the floating gate layer and the layout of the logic gate layer in the second embodiment is the specific surface area data of the actual sidewall material layer coverage pattern. Since the formed sidewall material layer mainly covers the side and top surfaces of the logic unit or the flash memory unit, it is more accurate to use the specific surface area to represent the actual sidewall material layer coverage pattern. The specific surface area data in this embodiment is different from the conventional specific surface area, and the specific method may, for example, include:

[0063] S023: obtaining first specific surface area data according to the layout perimeter data of the logic gate layer; and

[0064] S024: Obtain second specific surface area data according to the layout perimeter data of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer. The specific surface area data of the actual sidewall material layer coverage pattern of the embedded flash memory is the sum of the first specific surface area data and the second specific surface area data.

[0065] In step S023, the layout perimeter data of all logic gate layers in a reference unit (eg, a die) is used to represent its specific surface area data, that is, the sum of the perimeters of the layouts of all logic gate layers is used as the first specific surface area data.

[0066] In step S024, similar to the first embodiment, the layout perimeter data of all floating gate layers in a reference unit (e.g., a die) is multiplied by the expansion width coefficient of the floating gate layer multiplied by the height difference coefficient to obtain the second specific surface area data. Then, the sum of the first specific surface area data and the second specific surface area data is used as the specific surface area data of the actual sidewall material layer covering pattern of the embedded flash memory.

[0067] Other subsequent processes, such as establishing a data model based on the specific surface area data of the actual side wall material layer covering pattern and the width of the side wall structure, and selecting the corresponding side wall material layer and the side wall structure formation process based on the data model, the actual layout data of the side wall material layer covering pattern and the preset width of the side wall structure are similar to the method in Example 1.

[0068] Of course, in specific implementation, the method in Example 1 can be used in combination with the method in Example 2, that is, the method in Example 1 and the method in Example 2 can be used in a cross-comparison manner.

[0069] In summary, the method for forming the sidewall structure of the embedded flash memory provided by the present invention has the following beneficial effects:

[0070] By providing the layout of the floating gate layer and the layout of the logic gate layer of the embedded flash memory; determining the layout data of the actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer; selecting the corresponding sidewall material layer and the formation process of the sidewall structure according to the layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure. According to the embodiment of the present invention, the appropriate sidewall material layer and the formation process of the sidewall structure can be selected according to the obtained layout data of the actual sidewall material layer covering pattern and the preset width of the sidewall structure, so as to accurately control the width of the sidewall structure of the embedded flash memory.

[0071] Furthermore, in an embodiment of the present invention, the layout density or specific surface area data of the floating gate layer in the flash memory area and the logic gate layer in the logic area can be combined with their corresponding expansion width coefficients and height difference coefficients to accurately obtain the layout density or specific surface area data of the actual sidewall material layer covering pattern.

[0072] Furthermore, in an embodiment of the present invention, by utilizing the established layout data of the actual side wall material layer covering pattern, the thickness of the side wall structure layer, and the data model of the corresponding formation process, the actual side wall material layer covering pattern layout data of the new product and the preset width of the side wall structure are substituted, so that the appropriate side wall structure formation process can be conveniently and accurately selected.

[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a sidewall structure of an embedded flash memory, wherein the embedded flash memory comprises a flash memory area and a logic area, wherein the flash memory area comprises a flash memory unit, and the logic area comprises a logic unit, wherein: The method for forming the sidewall structure of the embedded flash memory comprises: Providing a layout of a floating gate layer and a layout of a logic gate layer of the embedded flash memory, wherein the floating gate layer is located in the flash memory unit, and the logic gate layer is located in the logic unit; Determine layout data of an actual sidewall material layer covering pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer, wherein the actual sidewall material layer covering pattern is a pattern of the sidewall material layer covering the floating gate layer and the logic gate layer, and the layout data includes layout density of the actual sidewall material layer covering pattern and / or specific surface area data of the actual sidewall material layer covering pattern; According to the layout data of the actual side wall material layer covering pattern and the preset width of the side wall structure, the corresponding side wall material layer and the forming process of the side wall structure are selected to form the side wall structure, wherein a data model of the layout data of the actual side wall material layer covering pattern and the width of the side wall structure is established according to the historical layout data of the actual side wall material layer covering pattern and the historical width data and historical forming process data of the corresponding side wall structure; according to the data model and the layout data of the actual side wall material layer covering pattern, the forming process of the corresponding side wall structure is selected and the theoretical width of the corresponding side wall structure is obtained; based on the theoretical width of the side wall structure and the preset width of the side wall structure, the forming process of the side wall structure is adjusted.

2. The method for forming a sidewall structure of an embedded flash memory according to claim 1, characterized in that: The method for determining the layout density of the actual sidewall material layer coverage pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer includes: According to the layout density of the logic gate layer, a first layout density is obtained; and, A second layout density is obtained according to the layout density of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer, and the layout density of the actual sidewall material layer covering pattern of the embedded flash memory is the sum of the first layout density and the second layout density.

3. The method for forming a sidewall structure of an embedded flash memory according to claim 2, characterized in that: The second layout density is the product of the layout density of the floating gate layer, the expansion width coefficient of the floating gate layer, and the height difference coefficient.

4. The method for forming a sidewall structure of an embedded flash memory according to claim 1, characterized in that: The method for determining the specific surface area data of the actual sidewall material layer coverage pattern of the embedded flash memory according to the layout of the floating gate layer and the layout of the logic gate layer comprises: Obtaining first specific surface area data according to the layout perimeter data of the logic gate layer; and According to the layout perimeter data of the floating gate layer and the height difference coefficient between the floating gate layer and the logic gate layer, the second specific surface area data is obtained, and the specific surface area data of the actual sidewall material layer covering pattern of the embedded flash memory is the sum of the first specific surface area data and the second specific surface area data.

5. The method for forming a sidewall structure of an embedded flash memory according to claim 4, characterized in that: The second specific surface area data is the product of the layout perimeter data of the floating gate layer, the expansion width coefficient of the floating gate layer, and the height difference coefficient.

6. The method for forming a sidewall structure of an embedded flash memory according to any one of claims 2 to 5, characterized in that: The height difference coefficient is the sum of the height of the flash memory unit and the height of the logic gate layer divided by the height of the logic gate layer.

7. The method for forming a sidewall structure of an embedded flash memory according to claim 3 or 5, characterized in that: The expansion width coefficient is the sum of the widths of the bit line structure of the flash memory area and the floating gate layer of the flash memory area divided by the width of the floating gate layer of the flash memory area.

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