A universal IIC bus circuit and transmission method thereof

Abstract

The present invention discloses a universal IIC bus circuit and a transmission method thereof, comprising: a host, a plurality of IIC-controlled external devices, an open-drain circuit, an SDA line and an SCL line, wherein the host comprises a digital filter module, a shift register module, an address latch module, a timing control module, and an internal register module. The timing control module is used to generate the required timing for data transmission, and the timing is simplified by adding a counter to the timing control circuit. A digital filter module is added to the external SDA line and SCL line to filter out external input noise, so that data transmission can be better performed, and the transmission speed can be adjusted by adding an open-drain circuit externally. The present invention has a simpler structure and design, a higher transmission efficiency, a higher portability, and a smaller chip area when implemented.

Description

Technical Field

[0001] The invention belongs to the technical field of digital circuits, and in particular relates to a universal IIC bus circuit and a transmission method thereof. Background Art

[0002] The IIC bus is a simple, bidirectional binary synchronous serial bus developed by Philips that supports half-duplex communication. In addition to being connected to an external power supply, clock line, and ground line, the IIC bus consists of two lines, the clock line SCL and the data line SDA. Both SDA and SCL are signal lines that are connected to a high level through a pull-up resistor. When the bus is idle, both signal lines remain at a high level.

[0003] Chinese patent: CN103823782 A, 2014.05.28 (reference 1) discloses an IIC bridge communication method, device and system, such as Figure 1 As shown, the system includes: an IIC input module, a bridge state module and an IIC output module. The IIC input module is used to receive a first data signal, a first enable signal, a second data signal and a second enable signal according to a first clock signal, and generate an IIC input data signal according to the first data signal, the first enable signal, the second data signal and the second enable signal, and is used to transparently transmit the second clock signal; the bridge state module is used to generate an IIC output data signal from the IIC input data signal; the IIC output module signal is used to generate a third data signal, a third enable signal, a fourth data signal and a fourth enable signal according to the IIC output data signal, and send the third data signal, the third enable signal, the fourth data signal and the fourth enable signal according to the first clock signal. This system can continuously transmit a lot of data information, but the communication process is cumbersome, the entire circuit structure is complex, and the portability is poor.

[0004] Chinese patent CN206097101 U, 2017.04.12 (reference 2) discloses a multi-channel IIC expansion circuit system, including: an IIC bus module, an expansion circuit processing module and a parallel bus module, one end of the expansion circuit processing module is connected to the IIC bus module, the other end of the expansion circuit processing module is connected to the parallel bus module, and the IIC bus module has 8 IIC buses. This circuit can increase the transmission speed, but it is also necessary to add an expansion circuit processing module for assistance, which will increase the complexity and difficulty of the design and increase the area of ​​the chip. Summary of the invention

[0005] The purpose of the present invention is to provide a universal IIC bus circuit and a transmission method thereof, so as to solve the technical problem of how to simplify the internal timing, filter out clutter, and adjust the transmission speed.

[0006] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0007] A universal IIC bus circuit comprises a host, an open-drain circuit, an SCL line and an SDA line, and more than two external devices;

[0008] The host is used to transmit commands and perform shift storage of data;

[0009] The host is written in code and implemented through digital synthesis;

[0010] The open-drain circuit is connected to the SCL line and the SDA line of the host, and is used to pull up the level and adjust the data transmission speed;

[0011] The external device is connected to the host;

[0012] The SCL line is connected to the host and is used to transmit timing signals;

[0013] The SDA line is connected to the host and is used to transmit data signals;

[0014] The host includes a digital filter module, a shift register module, an address latch module, a timing control module, and an internal register module;

[0015] The digital filter module is connected to the external SCL line and SDA line to filter out the noise of the external input signal;

[0016] The shift register module performs specific read and write operations;

[0017] The address latch module is used to latch the control word of internal data;

[0018] The timing control module is used to control the timing during the transmission process;

[0019] The internal register module is used to latch internal address bits and data bits;

[0020] A counter module is provided inside the internal register module for counting.

[0021] Furthermore, the open-drain circuit uses a transistor, a resistor and a Schmitt trigger to form an open-drain output. The output end of the open-drain output is equivalent to the collector of the transistor. By adding a pull-up resistor, it is made to perform current-type driving, and the transmission speed is changed by adjusting the pull-up resistor.

[0022] Furthermore, the two or more external devices are devices of the same type, and the SCL line and the SDA line are used by the host to operate the two or more external devices, wherein when a timing signal is provided to the two or more external devices via a single SCL line, the SDA line transmits a data signal to the corresponding two or more external devices, connecting the two or more external devices to the internal register module of the host.

[0023] Furthermore, the external device performs a corresponding write operation or a read operation based on the SCL timing signal and the corresponding SDA data signal, and transmits a data signal to the corresponding external device through the SDA line according to the SCL timing signal and the address information of the external device.

[0024] Furthermore, the counter module has a self-starting capability. By counting the transmission timing, after the transmission starts, when the first data bit is transmitted, the counter module is 0, when the second data bit is transmitted, the counter module is 1, when the seventh data bit is transmitted, the counter module is 6, and when the eighth response bit is transmitted, the counter module is 7, and then cleared to zero, thereby simplifying the transmission process.

[0025] Furthermore, the digital filtering module utilizes a D flip-flop, an AND gate and a NOR gate to filter out noise of an external input signal through the cascade of the D flip-flops, and delays the transmission gate by adding a D flip-flop to avoid the generation of a metastable state through the delay.

[0026] Furthermore, the same external devices are configured to have different addresses.

[0027] A transmission method of a universal IIC bus circuit, comprising a host writing data to an external device and a host reading data from the external device;

[0028] The host writes data to the external device including the following steps:

[0029] Step 1: The host sends a start signal and device address to the external device;

[0030] Step 2: The host sends data to the external device;

[0031] Step 3, the host sends a stop signal to end the sending process;

[0032] The host reads data from the external device including the following steps:

[0033] Step a, the host sends a start signal and device address to the external device;

[0034] Step b, the host sends an address to be read to the external device;

[0035] Step c, the host receives data from the external device;

[0036] Step d: The host sends a stop signal to the external device to end the entire receiving process.

[0037] A universal IIC bus circuit and a transmission method thereof of the present invention have the following advantages:

[0038] 1) The present invention can filter out noise of the input signal by adding a digital filter module in the host, and has wider versatility. By adding a counter module internally for counting, the timing can be simplified and the design difficulty is reduced;

[0039] 2) By adding an open-drain circuit in the present invention, data can be written and read, and the transmission speed can be adjusted;

[0040] 3) The host module in the present invention is generated by code synthesis, which eliminates the need for other auxiliary circuits. By adding an open-drain circuit, a higher speed can be achieved, and the encoding circuit is implemented by digital synthesis, so it has better portability for different processes and is more conducive to on-chip implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of a universal IIC bus circuit structure of the present invention;

[0042] Figure 2 It is a module schematic diagram of the host in the present invention;

[0043] Figure 3 It is a schematic diagram of a counter of the present invention;

[0044] Figure 4 is a schematic diagram of an open-drain circuit of the present invention;

[0045] FIG5( a ) is a schematic diagram of a digital filter module for an SCL line of the present invention;

[0046] FIG5( b ) is a schematic diagram of a digital filter module of an SDA line of the present invention;

[0047] Figure 6 This is the filtering principle diagram of the digital filtering module. DETAILED DESCRIPTION

[0048] In order to better understand the purpose, structure and function of the present invention, a universal IIC bus circuit and a transmission method thereof of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0049] Figure 1 1 is a schematic diagram of the system structure of a universal IIC synchronous communication according to an embodiment of the present invention. Figure 1As shown, the whole system includes a host, an SCL line, an SDA line, an open-drain circuit and four external devices. The four external devices are a first device, a second device, a third device and a fourth device, and the external devices are devices of the same type. The host is mainly used to transmit commands and perform data shift registers, the open-drain circuit is used to pull up the level and adjust the data transmission speed, and the SCL line and the SDA line are used to transmit timing signals and data signals respectively.

[0050] The host includes a digital filter module, a shift register module, an address latch module, a timing control module, and an internal register module. The internal register module includes a first internal register, a second internal register, a third internal register, and a fourth internal register. The digital filter module is used to filter out the noise of the external SCL timing signal and the SDA data signal; the shift register module processes the data according to the read-write enable signal under the control of the timing control module; the address latch module is used to latch the internal control word; the timing control module is used to control the internal transmission timing; the internal register module is used to count the number of bytes during the transmission process;

[0051] The host is connected to each of the first device, the second device, the third device and the fourth device, that is, the first device is connected to the first internal register of the host, the second device is connected to the second internal register of the host, the third device is connected to the third internal register of the host, and the fourth device is connected to the fourth internal register of the host. The external SCL line and SDA line provide timing signals and data signals to the host, and the single SCL line provides timing signals to the first device, the second device, the third device and the fourth device through the host. The host transmits data information to the corresponding external device through the single SDA line according to the SCL timing signal and address information.

[0052] The host reads and writes the first device, the second device, the third device, and the fourth device through the SDA line and the SCL line. The host is the core of the entire circuit design. Figure 2 It is a schematic block diagram of the internal structure of a host of a general-purpose IIC bus.

[0053] In an optional embodiment, the same external device can be configured to have different addresses. For example, the first device, the second device, the third device, and the fourth device are of the same type but have different configured addresses. In this way, the host transmits a data signal to the corresponding external device through the SDA data signal according to the SCL timing signal and the address information.

[0054] When the communication content is not the same, the host can pre-eliminate unused external devices, and then communicate with the used external devices through the host. In addition, the communication mechanism can detect unresponsive devices at any time. For example, after the SDA line sends a byte of data to the first device through the host, the first device will generate a response bit, and then transmit the response bit to the host. If the host does not receive the response bit, it is considered that the first device has no response, so no data will be transmitted to the first device in the future. The entire transmission timing is controlled by the timing control module. The timing control module is the core of the entire IIC bus circuit and is used to implement the timing of the IIC bus. The timing is simplified by adding a counter module to the timing control module. Figure 3 is based on Figure 2 The schematic diagram of the counter module in the MCU is composed of three D flip-flops and has self-starting capability. When data transmission starts, the counter module starts and records the number of bits of data transmitted each time. When the first data bit is transmitted, the counter module is 000, when the second data bit is transmitted, the counter module is 001, and so on. When the eighth data bit is transmitted, the counter module is 111, and then the counter module is reset to count for the next data.

[0055] Connect the host's SCL line and SDA line to the open-drain circuit, and adjust the transmission speed by adjusting the open-drain circuit. Figure 4 is based on Figure 1 Schematic diagram of open-drain circuit. The open-drain circuit is used to connect different devices and match the electrical levels. When the pin of the open-drain circuit is not connected to an external pull-up resistor, it can only output a low level. If it is necessary to have the function of outputting a high level at the same time, a pull-up resistor is required. By changing the pull-up resistor, the transmission level can be changed. The larger the pull-up resistor value, the lower the speed and the lower the power consumption. The smaller the pull-up resistor value, the higher the speed and the higher the power consumption.

[0056] In the process of external signal transmission from open drain circuit to internal circuit, since there are a lot of noises in external timing signal and data signal, a digital filter module is added to the host to filter out the noises. The digital filter module is used to connect the external SCL line and SDA line, and the signal can be filtered through the filter module. Figure 5 is based on Figure 2 The schematic diagram of the digital filter module is composed of six D flip-flops, AND gates and NOR gates. Since the SCL line and SDA line are connected externally, glitches may occur during signal transmission. At this time, the received data needs to be filtered to avoid interference from noise. The noise generally exists for 1-3 clock cycles. Therefore, the input signal is set to beat four times to filter the signal. Figure 6As shown, the first is that a low-level signal appears. When the signal is at a low level, a high-level glitch phenomenon occurs. If the four beats entering the register are all high levels, it can be considered that the real signal has changed, rather than being affected by the glitch. At this time, the signal enters a high-level state. Otherwise, it is a short-term high level caused by the glitch, and the low-level state needs to be kept unchanged. The second is that a high-level signal appears. When the signal is at a high level, a low-level glitch phenomenon occurs. If the four beats entering the register are all low levels, it can be considered that the real signal has changed, rather than being affected by the glitch. At this time, the signal enters a low-level state. Otherwise, it is a short-term high level caused by the glitch, and the high-level state needs to be kept unchanged.

[0057] A transmission method of a universal IIC bus circuit, comprising a host writing data to an external device and a host reading data from the external device;

[0058] The host writes data to the external device including the following steps:

[0059] Step 1: The host sends a start signal and device address to the external device;

[0060] Step 2: The host sends data to the external device;

[0061] Step 3, the host sends a stop signal to end the sending process;

[0062] The host reads data from the external device including the following steps:

[0063] Step a, the host sends a start signal and device address to the external device;

[0064] Step b, the host sends an address to be read to the external device;

[0065] Step c, the host receives data from the external device;

[0066] Step d: The host sends a stop signal to the external device to end the entire receiving process.

[0067] During the IIC bus transmission process, when SCL is high, the level on the SDA line changes from high to low to indicate the start of transmission; when SCL is low, the level on the SDA line changes from low to high to indicate the end of transmission, and the host sends the start transmission and stop transmission signals. When the host sends the start transmission signal, the host enters the busy state. After a period of time after the host sends the stop transmission signal, the host enters the idle state. If the host receives a repeated start signal instead of a stop transmission signal, the host continues to be busy.

[0068] In the process of signal transmission, the IIC host first sends a start transmission signal, then the host sends a 7-bit address bit of the external device and a 1-bit read / write enable signal. If the addressed external device is in an idle state, it sends a response bit to the host. Then the host and the external device start data transmission under the action of the clock signal. The data transmission of the IIC bus is byte-by-byte transmission, and each byte must be 8 bits. The highest bit of the data is transmitted first. The number of bytes transmitted each time is not limited. After each byte of data is transmitted, a response bit must be followed. During the clock pulse of the response, the host releases the SDA line, and the SDA line is high. During the clock pulse of the response, the host must pull SDA down so that it remains at a stable low level during the high level of this clock pulse. Usually, the addressed external device must generate a response after receiving each byte. When the external device cannot respond to the host's address, the host must keep the data line SDA at a high level. The host then generates a stop transmission condition to terminate the transmission or generates a repeated start transmission signal to start a new transmission.

[0069] The open-drain circuit of the IIC bus is used to connect different signal levels. It is used to connect the SDA line and the SCL line externally and is connected to a high level through a pull-up resistor. When the bus is idle, both external signal lines remain at a high level and do not consume current. By adjusting the size of the pull-up resistor, the transmission level can be changed, thereby changing the transmission speed. The larger the pull-up resistor, the lower the speed and the lower the power consumption; the smaller the pull-up resistor, the higher the speed and the greater the power consumption.

[0070] The host performs corresponding read operations or write operations on the external device through an internal shift register.

[0071] During the entire transmission process, the SCL timing signal and SDA data signal first enter the digital filter module inside the host of the IIC interface, and then enter the internal shift register to determine whether it is a read operation or a write operation. Next, the control word of the internal signal is sent to the address latch module, and the address and data of the timing signal are sent to the internal register module. Finally, the internal timing control module controls the transmission of internal data to the external device.

[0072] In general, in the digital circuit for realizing the universal IIC bus of this embodiment, the host can communicate with different external devices. Optionally, the SDA timing signal and the SCL data signal can be connected to more than two external devices through the host, and the addresses of the more than two external devices are different from each other. Data is transmitted through the host using the SDA line according to the SCL timing signal and the address information of the external device.

[0073] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A universal IIC bus circuit, characterized in that: It includes a host, an open-drain circuit, an SCL line and an SDA line, and two or more external devices; The host is used to transmit commands and perform shift storage of data; The host is written in code and implemented through digital synthesis; The open-drain circuit is connected to the SCL line and the SDA line of the host, and is used to pull up the level and adjust the data transmission speed; The external device is connected to the host; The SCL line is connected to the host and is used to transmit timing signals; The SDA line is connected to the host and is used to transmit data signals; The host includes a digital filter module, a shift register module, an address latch module, a timing control module, and an internal register module; The digital filter module is connected to the external SCL line and SDA line to filter out the noise of the external input signal; The shift register module performs specific read and write operations; The address latch module is used to latch the control word of internal data; The timing control module is used to control the timing during the transmission process, and flexibly convert the open-drain output and the push-pull output to improve the flexibility of the system; The internal register module is used to latch internal address bits and data bits; A counter module is provided inside the internal register module for counting.

2. The universal IIC bus circuit according to claim 1, characterized in that: The open-drain circuit uses a transistor, a resistor and a Schmitt trigger to form an open-drain output. The output end of the open-drain output is equivalent to the collector of the transistor. By adding a pull-up resistor, it is made into a current-type drive. By adjusting the pull-up resistor, the transmission speed is changed.

3. The universal IIC bus circuit according to claim 2, characterized in that: The two or more external devices are devices of the same type, and the SCL line and the SDA line are used by the host to operate the two or more external devices, wherein when a timing signal is provided to the two or more external devices via a single SCL line, the SDA line transmits a data signal to the corresponding two or more external devices, connecting the two or more external devices to the internal register module of the host.

4. The universal IIC bus circuit according to claim 3, characterized in that: The external device performs a corresponding write operation or a read operation based on the SCL timing signal and the corresponding SDA data signal, and transmits a data signal to the corresponding external device through the SDA line according to the SCL timing signal and the address information of the external device.

5. The universal IIC bus circuit according to claim 4, characterized in that: The counter module has a self-starting capability. By counting the transmission timing, after the transmission starts, when the first data bit is transmitted, the counter module is 0, when the second data bit is transmitted, the counter module is 1, when the seventh data bit is transmitted, the counter module is 6, and when the eighth response bit is transmitted, the counter module is 7, and then cleared to 0, thereby simplifying the transmission process.

6. The universal IIC bus circuit according to claim 5, characterized in that: The digital filtering module utilizes a D flip-flop, an AND gate and a NOR gate to filter out noise of an external input signal through the cascade connection of the D flip-flops, and delays the transmission gate by adding a D flip-flop to avoid the generation of a metastable state through the delay.

7. The universal IIC bus circuit according to claim 6, characterized in that: The same external devices are configured to have addresses that are different from each other.

8. A transmission method for a universal IIC bus circuit according to any one of claims 1 to 7, characterized in that: It includes the host writing data to the external device and the host reading data from the external device; The host writes data to the external device including the following steps: Step 1: The host sends a start signal and device address to the external device; Step 2: The host sends data to the external device; Step 3, the host sends a stop signal to end the sending process; The host reads data from the external device including the following steps: Step a, the host sends a start signal and device address to the external device; Step b, the host sends an address to be read to the external device; Step c, the host receives data from the external device; Step d: The host sends a stop signal to the external device to end the entire receiving process.

Images