Array substrate and preparation method thereof

Abstract

The embodiment of the present application provides an array substrate and a preparation method thereof, comprising a substrate; an electrode layer, comprising a first electrode portion and a second electrode portion that are not connected to each other; a gate, arranged on a side of the first electrode portion away from the substrate; the gate, the first electrode portion and the second electrode portion are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the pattern of the first electrode portion and the gate portion overlap, and the first electrode portion is located between the substrate and the gate; a gate insulating layer, located on the gate; a metal oxide layer, arranged on the gate insulating layer, the metal oxide layer comprising a conductor portion, a third electrode portion and a first semiconductor portion; the third electrode portion and the conductor portion are configured to be formed simultaneously by a conductorization process. The array substrate and the preparation method thereof provided by the embodiment of the present application can reduce the cost of the array substrate and improve the manufacturing efficiency of the array substrate.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of display substrates, and more specifically, to an array substrate and a method for preparing the same. Background Art

[0002] Fringe Field Switching (FFS) technology is currently a technology used in the field of liquid crystal display. It has the advantages of fast response speed, wide viewing angle, high light transmittance, etc. It is widely used in terminal devices such as notebook monitors, desktop monitors and TVs. It is also a display technology that has developed rapidly in recent years. The core of this technology is thin film transistor (TFT) technology, but the TFT of FFS liquid crystal panel is usually made of two layers of indium tin oxide ITO, which makes the production process of FFS liquid crystal panel more complicated and uses 1-2 more masks than ordinary liquid crystal panels. This leads to increased cost of FFS liquid crystal panel and reduced manufacturing efficiency. Summary of the invention

[0003] The embodiments of the present application provide an array substrate and a method for manufacturing the same, aiming to reduce the cost of the array substrate and improve the manufacturing efficiency of the array substrate.

[0004] A first aspect of an embodiment of the present application provides an array substrate, comprising:

[0005] substrate;

[0006] An electrode layer, comprising a first electrode portion and a second electrode portion which are not connected to each other;

[0007] a gate, arranged on a side of the first electrode portion away from the substrate; the gate, the first electrode portion and the second electrode portion are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the pattern of the first electrode portion and the gate overlap, the first electrode portion is located between the substrate and the gate, and contacts the substrate and the gate, the first electrode portion is a transparent metal oxide semiconductor, and the first electrode portion acts as a buffer layer to reduce stress between the gate and the substrate;

[0008] A gate insulating layer, located on the gate;

[0009] A metal oxide layer, disposed on the gate insulating layer, the metal oxide layer comprising a conductor portion, a third electrode portion and a first semiconductor portion, wherein the first semiconductor portion is an active layer;

[0010] Conductor parts are arranged on opposite sides of the first semiconductor part; the conductor parts are formed by the semiconductor metal oxide layer around the first semiconductor part being conductive, and the conductor parts include a first conductor part and a second conductor part separated from each other, the first conductor part is a drain, and the second conductor part is a source or a connection part connected to the source;

[0011] The third electrode portion is opposite to the second electrode portion and is insulated from the second electrode portion; one of the second electrode portion and the third electrode portion is a pixel electrode, and the other is a common electrode; the third electrode portion and the conductor portion are configured to be formed simultaneously using a conductorization process.

[0012] Optionally, a passivation layer is provided on a side of the first semiconductor portion away from the substrate, and an orthographic projection of the passivation layer on the substrate covers an orthographic projection of the gate on the substrate.

[0013] Optionally, a channel length of the first semiconductor portion as an active layer does not exceed 3 μm.

[0014] Optionally, the second conductor portion is electrically connected to the second electrode portion through a via hole penetrating the gate insulating layer.

[0015] Optionally, the metal oxide layer further includes a second semiconductor portion, and the second semiconductor portion is connected to the first conductor portion;

[0016] The array substrate further includes a data line, which is arranged on a side of the second semiconductor portion away from the substrate, and an orthographic projection of the second semiconductor portion on the substrate is located within an orthographic projection of the data line on the substrate, and the data line contacts the second semiconductor portion.

[0017] Optionally, the array substrate further includes a wiring, the wiring is arranged on a side of the third electrode portion away from the substrate, and an orthographic projection of the wiring on the substrate is located within an orthographic projection of the second electrode portion on the substrate.

[0018] Optionally, the third electrode portion includes a conductor sub-portion and a semiconductor sub-portion, the third electrode portion covered by the wiring is the semiconductor sub-portion, and the third electrode portion not covered by the wiring is the conductor sub-portion.

[0019] Optionally, the routing line and the data line are arranged on the same layer.

[0020] Optionally, the second electrode portion is a planar electrode, and the third electrode portion includes a plurality of parallel strip electrodes.

[0021] Optionally, the material of the metal oxide layer includes: indium gallium zinc oxide, indium gallium tin oxide or indium gallium zinc tin oxide.

[0022] A second aspect of the embodiments of the present application provides a display panel, comprising the array substrate provided in the first aspect of the embodiments of the present application.

[0023] A third aspect of an embodiment of the present application provides a method for preparing an array substrate, the method comprising:

[0024] providing a substrate;

[0025] An electrode layer is formed on the substrate, the electrode layer comprising a first electrode portion and a second electrode portion which are not connected to each other; a gate is formed on a side of the first electrode portion away from the substrate; the gate, the first electrode portion and the second electrode portion are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the pattern of the first electrode portion and the gate overlap, the first electrode portion is located between the substrate and the gate, and contacts the substrate and the gate, the first electrode portion is a transparent metal oxide semiconductor, and the first electrode portion acts as a buffer layer to reduce stress between the gate and the substrate;

[0026] forming a gate insulating layer on the electrode portion and the gate;

[0027] A metal oxide layer is formed on the gate insulating layer, the metal oxide layer includes a conductor part, a third electrode part and a first semiconductor part; the first semiconductor part is an active layer; conductor parts are arranged on opposite sides of the first semiconductor part; the conductor part is formed by conductorizing the semiconductor metal oxide layer around the first semiconductor part, the conductor part includes a first conductor part and a second conductor part separated from each other, the first conductor part is a drain, and the second conductor part is a source or a connecting part connected to the source; the third electrode part is arranged opposite to the second electrode part and insulated; one of the second electrode part and the third electrode part is a pixel electrode, and the other is a common electrode; the third electrode part and the conductor part are configured to be formed simultaneously by a conductorization process.

[0028] Beneficial effects:

[0029] The present application provides an array substrate and a preparation method thereof, wherein an electrode layer including a first electrode portion and a second electrode portion and a gate are simultaneously formed by using the same half-tone mask template on the same metal oxide semiconductor layer, and a metal oxide layer including a first conductor portion, a third electrode portion and a first semiconductor portion is provided, the first semiconductor portion is an active layer, the first conductor portion of the conductor portion is a drain, and the second conductor portion is a source or a connecting portion connected to the source, thereby forming a TFT structure; one of the second electrode portion and the third electrode portion is a pixel electrode, and the other is a common electrode; the third electrode portion and the conductor portion are simultaneously formed by a conductorization process, thus forming the entire array substrate, and by simultaneously forming the electrode layer and the gate, and utilizing the conductorization process to form the TFT structure of the array substrate, the photomask required in the manufacturing process of the array substrate can be reduced, thereby reducing the manufacturing cost of the array substrate and improving the manufacturing efficiency of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 is a structural schematic diagram of an array substrate proposed in one embodiment of the present application;

[0032] Figure 2 is a schematic diagram of a top view structure of an array substrate proposed in one embodiment of the present application;

[0033] Figure 3 is a flowchart of a method for preparing an array substrate according to an embodiment of the present application;

[0034] Figure 4 It is a schematic cross-sectional structure diagram of an array substrate after substrate manufacturing is completed according to an embodiment of the present application;

[0035] Figure 5 It is a schematic cross-sectional structure diagram of an array substrate after the electrode layer and the gate layer are manufactured, as proposed in one embodiment of the present application;

[0036] Figure 6 It is a schematic cross-sectional structure diagram of an array substrate proposed in an embodiment of the present application after patterning of an electrode layer and a gate layer is completed;

[0037] Figure 7 It is a schematic diagram of the cross-sectional structure of a patterned electrode layer and a gate layer of an array substrate after etching, as proposed in one embodiment of the present application;

[0038] Figure 8 It is a schematic cross-sectional structure diagram of an array substrate after the first electrode portion is manufactured according to an embodiment of the present application;

[0039] Fig. 9 It is a schematic cross-sectional structure diagram of an array substrate proposed in an embodiment of the present application after the first electrode portion, the second electrode portion and the gate are manufactured;

[0040] Fig.10 It is a schematic cross-sectional structure diagram of an array substrate after the gate insulating layer is manufactured according to an embodiment of the present application;

[0041] Fig.11 It is a schematic cross-sectional structure diagram of an array substrate after the metal oxide layer and the data line layer are manufactured according to an embodiment of the present application;

[0042] Fig.12 It is a schematic cross-sectional structure diagram of an array substrate after patterning of a metal oxide layer and a data line layer is completed, as proposed in one embodiment of the present application;

[0043] Fig.13 It is a schematic diagram of the cross-sectional structure of a patterned metal oxide layer and a data line layer of an array substrate after etching, as proposed in one embodiment of the present application;

[0044] Fig.14 It is a schematic diagram of the cross-sectional structure of an array substrate after the photoresist on the metal oxide layer is removed, as proposed in one embodiment of the present application;

[0045] Fig.15 It is a schematic diagram of the cross-sectional structure of an array substrate after the photoresist on the data line layer is removed, as proposed in one embodiment of the present application;

[0046] Fig.16 It is a schematic cross-sectional structure diagram of an array substrate after passivation layer manufacturing is completed, as proposed in one embodiment of the present application;

[0047] Fig.17 It is a schematic diagram of the cross-sectional structure of an array substrate after the metal oxide layer is conductively converted according to an embodiment of the present application.

[0048] Explanation of the reference numerals: 10, substrate; 11, electrode layer; 111, first electrode portion; 112, second electrode portion; 12, gate; 13, gate insulating layer; 14, metal oxide layer; 141, conductor portion; 1411, first conductor portion; 1412, second conductor portion; 142, third electrode portion; 1421, conductor sub-portion; 1422, semiconductor sub-portion; 143, first semiconductor portion; 144, second semiconductor portion; 15, passivation layer; 16, data line; 17, routing; 20, gate layer; 30, data line layer. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] Embodiment 1

[0051] Reference Figure 1 As shown, an array substrate disclosed in an embodiment of the present application includes, from bottom layer to top layer, a substrate 10, an electrode layer 11, a gate 12, a gate insulating layer 13, a metal oxide layer 14, a passivation layer 15, a data line 16 and a routing line 17.

[0052] Specifically, the electrode layer 11 includes a first electrode portion 111 and a second electrode portion 112 which are not connected to each other, wherein the second electrode portion 112 serves as a pixel electrode or a common electrode of the array substrate. The electrode layer 11 can be made of a transparent material, such as ITO (indium tin oxide) or IZO (indium zinc oxide). The thickness of the electrode layer 11 is

[0053] Reference Figure 1 As shown, the gate 12 is located on the side of the first electrode portion 111 of the electrode layer 11 away from the substrate 10, and the patterns of the gate 12 and the first electrode portion 111 overlap, the first electrode portion 111 is located between the substrate 10 and the gate 12, and the first electrode portion 111 is in contact with the substrate 10 and the gate 12 at the same time. The first electrode portion 111 can be used as a buffer layer to reduce the stress between the gate 12 and the substrate 10. The gate 12 can be made of metal materials such as Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb, and the thickness of the gate 12 is

[0054] During the manufacturing process, the gate 12, the first electrode portion 111 and the second electrode portion 112 are simultaneously formed by using the same half-tone mask template for the same metal oxide semiconductor layer. That is, when manufacturing the gate 12 and the electrode layer 11, the electrode layer 11 and the gate layer 20 are sequentially covered on the substrate 10, and then the electrode layer 11 and the gate layer 20 are patterned using the same half-tone mask template, and then the gate 12, the second electrode portion 112 and the first electrode portion 111 covered by the gate 12 are formed through processes such as exposure, development, etching and stripping. In this way, the electrode layer 11 and the gate 12 can be manufactured using the same mask, thereby reducing the use of one layer of mask in the manufacturing process of the array substrate.

[0055] And, refer to Figure 2 As shown, the second electrode portion 112 is a planar electrode.

[0056] The gate insulating layer 13 covers the electrode layer 11 and the gate 12. After the gate insulating layer 13 is patterned, a via hole penetrating the gate insulating layer 13 to the second electrode portion 112 is formed on the gate insulating layer 13. The gate insulating layer 13 can be made of silicon oxide material or a composite material of silicon nitride and silicon oxide. The thickness of the gate insulating layer 13 is

[0057] The metal oxide layer 14 is disposed on the side of the gate insulating layer 13 away from the substrate 10. The metal oxide layer 14 may be selected from indium gallium zinc oxide, indium gallium tin oxide or indium gallium zinc tin oxide. The thickness of the metal oxide layer 14 is

[0058] Specifically, refer to Figure 1 As shown, the metal oxide layer 14 includes a conductor portion 141, a third electrode portion 142 and a first semiconductor portion 143. The conductor portion 141 and the third electrode portion 142 are formed simultaneously by a conductorization process, so that the conductor portion 141 and the third electrode portion 142 are conductive, and the first semiconductor portion is not conductorized.

[0059] The orthographic projection of the first semiconductor portion 143 on the substrate 10 is located within the orthographic projection of the gate 12 on the substrate 10 , and the first semiconductor portion 143 is used as an active layer of the array substrate.

[0060] Furthermore, through the conductorization process, there is no need to consider the risk of etching residues, so the channel length of the first semiconductor portion 143 as the active layer can be no more than 3μm. Compared with the current array substrate, the channel length is reduced, thereby effectively reducing the size of the TFT and improving the aperture ratio.

[0061] Reference Figure 1 As shown, the conductor portion 141 is formed by conductorizing the semiconductor metal oxide layer around the first semiconductor portion, and the conductor portion 141 includes a first conductor portion 1411 and a second conductor portion 1412 separated from each other, and the first conductor portion 1411 is used as a drain, and the second conductor portion 1412 is used as a source, so that the conductor portion 141 and the gate 12 can form a TFT (Thin Film Transistor) structure, and the second conductor portion 1412 is electrically connected to the second electrode portion 112 through a via hole penetrating the gate insulating layer 13 to transmit electrical signals to the second electrode portion 112.

[0062] Reference Figure 1 and Figure 2As shown, the third electrode portion 142 includes a plurality of parallel strip electrodes, and the third electrode portion 142 is arranged opposite to the second electrode portion and insulated. The third electrode portion 142 is used as a common electrode or a pixel electrode of the array substrate. When the second electrode portion is a pixel electrode, the third electrode portion is a common electrode; when the second electrode portion is a common electrode, the third electrode portion is a pixel electrode. At the same time, the third electrode portion and the conductor portion are formed simultaneously by conducting the same semiconductor metal oxide layer using a conductorization process.

[0063] Reference Figure 1 As shown, the passivation layer 15 is located on the side of the first semiconductor portion 143 away from the substrate 10, and the orthographic projection of the passivation layer 15 on the substrate 10 covers the orthographic projection of the gate 12 on the substrate 10. The passivation layer 15 can be made of silicon oxide or silicon oxynitride, and the thickness of the passivation layer 15 is

[0064] During the process of conducting the metal oxide layer, the passivation layer 15 can prevent the metal oxide layer 14 at the passivation layer 15 from being conducted, thereby forming the first semiconductor portion 143 .

[0065] Meanwhile, the metal oxide layer 14 further includes a second semiconductor portion 144 , and the second semiconductor portion 144 is connected to the conductor portion 141 that is not connected to the second electrode portion 112 .

[0066] Reference Figure 1 As shown, the data line 16 and the routing line 17 are arranged in the same layer, that is, the data line 16 and the routing line 17 are made by a single patterning process. A single patterning process refers to a process of forming a required layer structure by a single exposure. A single patterning process includes processes such as masking, exposure, development, etching and stripping. The data line 16 and the routing line 17 can be made of metal materials such as Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb. The thickness of the data line 16 and the routing line 17 is

[0067] The data line 16 is disposed on a side of the second semiconductor portion 144 away from the substrate 10, and the orthographic projection of the second semiconductor portion 144 on the substrate 10 is located within the orthographic projection of the data line 16 on the substrate 10, and the data line 16 contacts the second semiconductor portion 144. The data line 16 is used to transmit data signals of the TFT.

[0068] The data line 16 covers the metal oxide layer 14 during the conductorization process of the metal oxide layer, so that the metal oxide layer 14 at the data line 16 will not be conductorized, thereby forming the second semiconductor portion 144 .

[0069] Reference Figure 1As shown, the wiring 17 is arranged on a side of the third electrode portion 142 away from the substrate 10, and the orthographic projection of the wiring 17 on the substrate 10 is located within the orthographic projection of the second electrode portion 112 on the substrate 10. The third electrode portion 142 includes a conductor sub-portion 1421 and a semiconductor sub-portion 1422, wherein the third electrode portion 142 covered by the wiring 17 is not the semiconductor sub-portion 1422, and the third electrode portion 142 not covered by the wiring 17 is the conductor sub-portion 1421.

[0070] The wiring 17 connects the multiple strip electrodes of the third electrode portion 142 . When the third electrode portion is used as a common electrode, the resistance load of the third electrode layer 11 can be reduced, thereby improving the device performance of the array substrate.

[0071] During the conductorization process of the metal oxide layer 14 , the wiring 17 is also covered on the metal oxide layer 14 , so that the metal oxide layer 14 at the wiring 17 will not be conductorized, thereby forming a semiconductor sub-portion 1422 .

[0072] Embodiment 2

[0073] Based on the same inventive concept, an embodiment of the present application provides a display panel, including the array substrate provided in the first embodiment of the present application. The display panel may further include a flexible circuit board, a packaging cover plate, and the like.

[0074] The display panel may be a flexible display panel or a common display panel (which may be referred to as a rigid display). Exemplary products including the display panel may include: computer monitors, televisions, billboards, laser printers with display functions, telephones, mobile phones, personal digital assistants (PDAs), laptop computers, digital cameras, camcorders, viewfinders, vehicles, large-area walls, theater screens, or stadium signs, etc.

[0075] Embodiment 3

[0076] Figure 3 This is a flowchart of the steps of a method for preparing an array substrate according to an embodiment of the present application. Figure 3 As shown, an embodiment of the present application provides an array substrate standby method, which is applied to the array substrate described in any of the above embodiments, and the method includes:

[0077] Step 301: Provide a substrate 10.

[0078] Specifically, the step of providing the substrate 10 may include completing the manufacture of the substrate 10, such as Figure 4 shown.

[0079] Step 302: An electrode layer 11 is formed on a substrate 10, wherein the electrode layer 11 includes a first electrode portion 111 and a second electrode portion 112 which are not connected to each other; a gate 12 is formed on a side of the first electrode portion 111 away from the substrate 10; the gate 12, the first electrode portion 111 and the second electrode portion 112 are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the patterns of the first electrode portion 111 and the gate 12 coincide with each other, the first electrode portion 111 is located between the substrate 10 and the gate 12, and is in contact with the substrate 10 and the gate 12, the first electrode portion 111 is a transparent metal oxide semiconductor, and the first electrode portion 111 serves as a buffer layer to reduce the stress between the gate 12 and the substrate 10.

[0080] Specifically, step 302 includes the following sub-steps:

[0081] Step 3021: An electrode layer 11 and a gate layer 20 are sequentially formed on the substrate 10, wherein the electrode layer 11 covers the substrate 10, and the gate layer 20 covers the electrode layer 11. Figure 5 shown.

[0082] Specifically, the electrode layer 11 may be made of indium tin oxide or indium zinc oxide. The thickness of the electrode layer 11 is The gate layer 20 can be made of Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb. The thickness of the gate layer is

[0083] Step 3022: Use a halftone HTM mask to perform a yellow photo process to form a gate 12 pattern and a first electrode portion 111 pattern and a second electrode portion 112 pattern of the electrode layer 11, such as Figure 6 shown.

[0084] Specifically, the orthographic projection of the gate 12 on the substrate 10 overlaps with the orthographic projection of the first electrode portion 111 on the substrate 10 .

[0085] Step 3023: Remove the electrode layer 11 and the gate layer 20 without photoresist protection by etching process; specifically, remove the photoresist on the electrode layer 11 and the gate layer 20, such as Figure 6 Shown

[0086] Step 3024: removing the photoresist on the second electrode portion 112 by using an O2 ash process, and then removing the gate layer 20 on the second electrode portion 112 by an etching process to make the second electrode portion 112 transparent;

[0087] Specifically, the photoresist on the second electrode portion is removed, and the gate layer on the second electrode portion is removed. Figure 7 shown.

[0088] Step 3025: removing the photoresist on the gate 12 by using an O2 ash process;

[0089] The above steps can complete the formation of the gate 12, the first electrode portion 111 and the second electrode portion 112, wherein the second electrode portion 112 is used as a pixel electrode of the array substrate. Figure 8 and Fig. 9 shown.

[0090] Step 303 : forming a gate insulating layer 13 on the second electrode portion 112 and the gate 12 .

[0091] Specifically, a gate insulating layer 13 is deposited on the gate 12 and the second electrode portion 112, and the gate insulating layer 13 is subjected to photolithography and etching to pattern the gate insulating layer 13, such as Fig.10 shown.

[0092] The material of the gate insulating layer 13 can be silicon oxide or a combination of silicon nitride and silicon oxide. The thickness of the gate insulating layer 13 is A via hole penetrating the gate insulating layer 13 to the second electrode portion 112 is formed on the patterned gate insulating layer 13 .

[0093] Step 304: forming a metal oxide layer 14 on the gate insulating layer 13, the metal oxide layer 14 comprising a conductor portion 141, a third electrode portion 142 and a first semiconductor portion 143; the first semiconductor portion 143 is an active layer; conductor portions 141 are arranged on opposite sides of the first semiconductor portion 143; the conductor portion 141 is formed by conductorizing the semiconductor metal oxide layer around the first semiconductor portion 143, the conductor portion 141 comprises a first conductor portion 1411 and a second conductor portion 1412 separated from each other, the first conductor portion 1411 is a drain, and the second conductor portion 1412 is a source or a connection portion connected to the source; the third electrode portion 142 is arranged opposite to the second electrode portion 112 and insulated; one of the second electrode portion 112 and the third electrode portion 142 is a pixel electrode, and the other is a common electrode; the third electrode portion 142 and the conductor portion 141 are configured to be formed simultaneously by a conductorization process.

[0094] Specifically, step 304 includes the following sub-steps:

[0095] Step 3041 : depositing a metal oxide layer 14 and a data line layer 30 in sequence on the gate insulating layer 13 .

[0096] Specifically, the material of the metal oxide layer 14 can be selected from indium gallium zinc oxide, indium gallium tin oxide or indium gallium zinc tin oxide. The thickness of the metal oxide layer 14 is The material of the data line layer 30 can be Cu / Mo, Cu / Ti, Cu / MoTi or Cu / MoNb. The thickness of the data line layer 30 is like Fig.11 shown.

[0097] Step 3042 : Use a half-tone HTM mask to perform a yellow light process on the metal oxide layer 14 and the data line layer 30 to define the patterns of the data line 16 , the routing line 17 , and the metal oxide layer 14 .

[0098] Specifically, the pattern of the metal oxide layer 14 includes a planar portion located above the first electrode portion 111 and a plurality of strip portions located above the second electrode portion 112, wherein the planar portion contacts the second electrode portion 112 through a via hole on the gate insulating layer 13, the pattern of the data line 16 is located on the leftmost side of the planar portion of the metal oxide layer 14, and the pattern of the routing line 17 is located on the rightmost strip portion of the metal oxide layer, as shown in FIG. Fig.12 shown.

[0099] Step 3043: removing the pattern without photoresist protection, including the data line layer 30 and the metal oxide layer 14, through an etching process.

[0100] Specifically, the data line layer 30 and the metal oxide layer 14 without photoresist protection are removed. Fig.13 shown.

[0101] Step 3044: remove the photoresist at the surface portion of the metal oxide layer 14 not covered by the data line 16 pattern by an O2 ash process, and then remove the photoresist at the strip portion not covered by the routing line 17 pattern; and remove the data line layer 30 at the surface portion not covered by the data line 16 pattern by an etching process, and then remove the data line layer 30 at the strip portion not covered by the routing line 17 pattern. Fig.14 shown.

[0102] Step 3045: remove the photoresist on the data line 16 and the routing line 17 through an O2 ash process to form the data line 16 and the routing line 17.

[0103] Specifically, the data line 16 is used as a TFT data transmission signal line, and the wiring 17 is used to reduce the resistance load of the common electrode. Fig.15 shown.

[0104] Step 3046: deposit a passivation layer 15 on the metal oxide layer 14, the data line 16 and the routing line 17, and pattern the passivation layer 15 through yellow light and etching processes to expose the data line 16, the routing line 17 and the metal oxide layer 14 except for the area directly above the gate 12.

[0105] Specifically, the passivation layer 15 is patterned, such as Fig.16 shown.

[0106] Step 3047: Conduct the exposed metal oxide layer 14 by treating it with H2 or Ar plasma process.

[0107] Specifically, the data line 16, the passivation layer 15, and the metal oxide layer 14 under the wiring 17 are covered and therefore will not be conductorized, so that the metal oxide layer 14 under the data line 16 forms a second semiconductor portion 144, the metal oxide layer 14 under the passivation layer 15 forms a first semiconductor portion 143, and the first semiconductor portion 143 serves as the active layer of the TFT. The metal oxide layer 14 under the wiring 17 forms a semiconductor sub-portion 1422, and the planar portion of the metal oxide layer 14 on both sides of the first semiconductor portion 143 is conductorized to form a conductor portion 141, and the first conductor portion 1411 of the conductor portion 141 serves as the drain of the array substrate, and the second conductor portion 1412 serves as the drain of the array substrate, forming a TFT structure together with the gate 12. Multiple strip-shaped portions of the metal oxide layer 14 are conductorized to form a third electrode portion 142, and the third electrode portion 142 serves as a common electrode or pixel electrode of the array substrate. At the same time, the second conductor portion 1412 is electrically connected to the second electrode portion 112 through the via hole on the gate insulating layer 13, such as Fig.17 shown.

[0108] Since the conductorization of the metal oxide layer 14 will diffuse to a certain depth during the conductorization process, the orthographic projection of the first semiconductor portion 143 on the substrate 10 is located within the orthographic projection of the gate 12 on the substrate 10; by adjusting the opening size of the passivation layer 15 and the strength of the plasma process, the channel length of the first semiconductor portion 143 as the active layer can be made not to exceed 3μm, thereby reducing the length of the channel, thereby effectively reducing the size of the TFT and improving the aperture ratio.

[0109] The array substrate is prepared through the above steps, and only four mask processes are included in the entire manufacturing process, so the number of masks required to manufacture the array substrate is reduced, thereby reducing the manufacturing cost of the array substrate and improving the manufacturing efficiency. At the same time, the conductorization process is adopted, and the channel length of the manufactured TFT can be less than 3μm, which can effectively reduce the size of the TFT and thus improve the aperture ratio.

[0110] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] It should also be noted that, in this article, the orientation or position relationship indicated by the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. Without more restrictions, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or terminal device comprising the element.

[0112] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in this article using specific examples. The description of the above embodiments is only used to help understand the present application, and the content of this specification should not be understood as limiting the present application. At the same time, for those of ordinary skill in the art, according to the present application, there will be different forms of changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all the implementation methods here, and the obvious changes or modifications derived therefrom are still within the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An electrode layer, comprising a first electrode portion and a second electrode portion which are not connected to each other; a gate, arranged on a side of the first electrode portion away from the substrate; the gate, the first electrode portion and the second electrode portion are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the pattern of the first electrode portion and the gate overlap, the first electrode portion is located between the substrate and the gate, and contacts the substrate and the gate, the first electrode portion is a transparent metal oxide semiconductor, and the first electrode portion acts as a buffer layer to reduce stress between the gate and the substrate; A gate insulating layer, located on the gate; A metal oxide layer, disposed on the gate insulating layer, the metal oxide layer comprising a conductor portion, a third electrode portion and a first semiconductor portion, wherein the first semiconductor portion is an active layer; Conductor parts are arranged on opposite sides of the first semiconductor part; the conductor parts are formed by the semiconductor metal oxide layer around the first semiconductor part being conductive, and the conductor parts include a first conductor part and a second conductor part separated from each other by the first semiconductor part, the first conductor part is a drain, and the second conductor part is a source or a connection part connected to the source; The third electrode portion is opposite to the second electrode portion and is insulated from the second electrode portion; one of the second electrode portion and the third electrode portion is a pixel electrode, and the other is a common electrode; the third electrode portion and the conductor portion are configured to be formed simultaneously using a conductorization process.

2. The array substrate according to claim 1, characterized in that: A passivation layer is disposed on a side of the first semiconductor portion away from the substrate, and an orthographic projection of the passivation layer on the substrate covers an orthographic projection of the gate on the substrate.

3. The array substrate according to claim 1, characterized in that: The channel length of the first semiconductor portion as an active layer does not exceed 3 μm.

4. The array substrate according to claim 1, characterized in that: The second conductor portion is electrically connected to the second electrode portion through a via hole penetrating the gate insulating layer.

5. The array substrate according to claim 1, characterized in that: The metal oxide layer further includes a second semiconductor portion, wherein the second semiconductor portion is connected to the first conductor portion; The array substrate further includes a data line, which is arranged on a side of the second semiconductor portion away from the substrate, and an orthographic projection of the second semiconductor portion on the substrate is located within an orthographic projection of the data line on the substrate, and the data line contacts the second semiconductor portion.

6. The array substrate according to claim 5, characterized in that: The array substrate further includes a wiring, which is arranged on a side of the third electrode portion away from the substrate, and an orthographic projection of the wiring on the substrate is located within an orthographic projection of the second electrode portion on the substrate.

7. The array substrate according to claim 6, characterized in that: The third electrode portion includes a conductor sub-portion and a semiconductor sub-portion. The third electrode portion covered by the wiring is the semiconductor sub-portion, and the third electrode portion not covered by the wiring is the conductor sub-portion.

8. The array substrate according to claim 6, characterized in that: The routing line and the data line are arranged on the same layer.

9. The array substrate according to claim 1, characterized in that: The second electrode portion is a planar electrode, and the third electrode portion includes a plurality of parallel strip electrodes.

10. The array substrate according to claim 1, characterized in that: The material of the metal oxide layer includes: indium gallium zinc oxide, indium gallium tin oxide or indium gallium zinc tin oxide.

11. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 10.

12. A method for preparing an array substrate according to any one of claims 1 to 10, characterized in that: The method comprises: providing a substrate; An electrode layer is formed on the substrate, the electrode layer comprising a first electrode portion and a second electrode portion which are not connected to each other; a gate is formed on a side of the first electrode portion away from the substrate; the gate, the first electrode portion and the second electrode portion are configured to be formed simultaneously by using the same half-tone mask template for the same metal oxide semiconductor layer; the pattern of the first electrode portion and the gate overlap, the first electrode portion is located between the substrate and the gate, and contacts the substrate and the gate, the first electrode portion is a transparent metal oxide semiconductor, and the first electrode portion acts as a buffer layer to reduce stress between the gate and the substrate; forming a gate insulating layer on the second electrode portion and the gate; A metal oxide layer is formed on the gate insulating layer, the metal oxide layer includes a conductor part, a third electrode part and a first semiconductor part; the first semiconductor part is an active layer; conductor parts are arranged on opposite sides of the first semiconductor part; the conductor part is formed by conductorizing the semiconductor metal oxide layer around the first semiconductor part, the conductor part includes a first conductor part and a second conductor part separated from each other, the first conductor part is a drain, and the second conductor part is a source or a connecting part connected to the source; the third electrode part is arranged opposite to the second electrode part and insulated; one of the second electrode part and the third electrode part is a pixel electrode, and the other is a common electrode; the third electrode part and the conductor part are configured to be formed simultaneously by a conductorization process.

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