A digital multi-channel pulse amplitude analysis device

Abstract

The present invention discloses a digital multi-channel pulse amplitude analysis device, which includes: a signal conditioning module, a digital-to-analog conversion chip, an FPGA digital processing module, a memory, a multi-core DSP chip, a power supply module, a clock module and a display module. The pulse processing function of the analog circuit between the preamplifier and the digital-to-analog conversion chip sampling in the prior art is implemented using the FPGA digital processing module and the multi-core DSP chip, and processed by a first preset algorithm and a second preset algorithm. The specific process of the first preset algorithm and the second preset algorithm is that the signal output by the preamplifier is directly sampled by the digital-to-analog conversion chip after passing through a simple main amplification circuit, and then threshold positioning, pulse counting or accumulation discrimination, peak extraction, and pulse counting are implemented in the multi-core DSP chip, thereby making the digital multi-channel pulse amplitude analysis device in the embodiment of the present invention small in size, simple in structure, and convenient for debugging and modifying parameters.

Description

Technical Field

[0001] The invention relates to the technical field of digital circuit processing, and in particular to a digital multi-channel pulse amplitude analysis device. Background Art

[0002] The multi-channel pulse amplitude analysis device (DMCA for short) is one of the key components of the micro-area X-ray energy spectrum. Its function is to subdivide the energy equivalent as the channel address, and then extract and statistically obtain the energy spectrum data by extracting the peak value of the voltage pulse signal converted from the characteristic X-ray energy, and finally upload these spectral line data to the host computer for visualization. As the core component of data acquisition and processing in the spectrometer, DMCA is used to analyze the type and content of elements in the sample to be tested.

[0003] In the related art, the multi-channel pulse amplitude analyzer is mainly based on analog circuits, that is, the analog signal output by the preamplifier needs to be processed by multiple circuits such as pole-zero cancellation circuit, filter shaping circuit, pulse discrimination circuit, amplitude holding circuit, etc. before it can be sampled by the digital-analog circuit. Obviously, the analog circuit for pulse processing is not only bulky and complex in structure, but also quite inconvenient to debug the multi-channel pulse amplitude analyzer. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem that the analog circuit for pulse processing in the prior art is not only bulky and complex in structure, but also quite inconvenient to debug the multi-channel pulse amplitude analyzer, thereby providing a digital multi-channel pulse amplitude analysis device.

[0005] According to a first aspect, the present invention provides a digital multi-channel pulse amplitude analysis device, comprising:

[0006] A signal conditioning module, used for conditioning the analog signal output by the preamplifier to output a double exponential pulse signal of a preset amplitude;

[0007] A digital-to-analog conversion chip, connected to the signal conditioning module, for converting the conditioned double exponential pulse signal into a digital signal;

[0008] An FPGA digital processing module is connected to the digital-to-analog conversion chip and is used to drive the digital-to-analog conversion chip to work;

[0009] A multi-core DSP chip is connected to the FPGA digital chip and the memory, respectively, and is used to digitally process the digital signal according to a first preset algorithm using a first digital channel, digitally process the digital signal according to a second preset algorithm using a second digital channel, and send the digital signal processed by the first digital channel and the second digital channel to the memory for storage;

[0010] The power supply module is respectively connected to the signal conditioning module, the digital-to-analog conversion chip, the FPGA digital processing module, and the multi-core DSP chip.

[0011] In one embodiment, the digital multi-channel pulse amplitude analysis device further includes: a clock module connected to the FPGA digital processing module, and used to provide a clock signal of a first frequency for the FPGA digital chip.

[0012] In one embodiment, the digital multi-channel pulse amplitude analysis device further includes: a display module, connected to the multi-core DSP chip and the power module respectively, for displaying the digital signal processed by the first digital channel and the second digital channel.

[0013] In one implementation, the signal conditioning module includes: a calculus circuit and an amplification bias circuit, and the calculus circuit is connected to the amplification bias circuit.

[0014] In one implementation, the FPGA digital processing module includes:

[0015] A digital-to-analog driving unit, connected to the digital-to-analog conversion chip, and used to drive the digital-to-analog conversion chip to work;

[0016] a clock generating unit, connected to the clock module and the digital-analog driving unit respectively, and configured to output a clock signal of a second frequency and a clock signal of a third frequency to the digital-analog driving unit according to the clock signal of the first frequency output by the clock module;

[0017] A logic analysis unit, connected to the digital-to-analog driving unit, and configured to perform logic analysis on the digital signal output by the digital-to-analog conversion chip;

[0018] a data conversion unit, connected to the clock generating unit, and acquiring the clock signal of the third frequency output by the clock generating unit;

[0019] The communication interface unit is connected to the data conversion unit and is used to output the digital signal after digital processing.

[0020] In one implementation, the multi-core DSP chip includes: a plurality of mutually independent processors, wherein one processor is used to execute a master processing task, and the remaining processors are used to execute slave processing tasks.

[0021] In one embodiment, the first preset algorithm forms a trapezoidal pulse through threshold positioning and pulse input counting in a fast shaping manner.

[0022] In one embodiment, the second preset algorithm forms a trapezoidal pulse through pile-up determination, peak extraction, and pulse output counting in a slow shaping manner.

[0023] In one embodiment, the power module converts AC power with a voltage of 220V into DC power with voltages of ±5V, ±3.3V and 12V respectively.

[0024] In one implementation, the memory is a DDR3 memory.

[0025] The technical solution of the present invention has the following advantages:

[0026] In an embodiment of the present invention, a digital multi-channel pulse amplitude analysis device is provided, which includes: a signal conditioning module, a digital-to-analog conversion chip, an FPGA digital processing module, a memory, a multi-core DSP chip, a power supply module, a clock module and a display module. The analog circuit pulse processing function between the preamplifier and the digital-to-analog conversion chip sampling in the prior art is implemented using the FPGA digital processing module and the multi-core DSP chip, and processed by the first preset algorithm and the second preset algorithm. The specific process of the first preset algorithm and the second preset algorithm is that the signal output by the preamplifier is directly sampled by the digital-to-analog conversion chip after passing through a simple main amplification circuit, and then threshold positioning, pulse counting or accumulation discrimination, peak extraction, and pulse counting are implemented in the multi-core DSP chip, thereby making the digital multi-channel pulse amplitude analysis device in the embodiment of the present invention small in size, simple in structure, and convenient for debugging and modifying parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 This is a structural schematic diagram of a digital multi-channel pulse amplitude analysis device in an embodiment of the present invention;

[0029] Figure 2 is a specific circuit schematic diagram of a signal conditioning module in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure of the FPGA digital processing module in an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a specific working procedure of an FPGA digital processing module in an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of the processing process of multi-channel pulse digital signals in an embodiment of the present invention;

[0033] Figure 6 Schematic diagram of a double exponential pulse signal in an embodiment of the present invention;

[0034] Figure 7 Schematic diagram of the time domain variation of a trapezoidal pulse signal in an embodiment of the present invention.

[0035] Reference numerals:

[0036] 11-Signal conditioning module; 12-Digital-to-analog conversion chip; 13-FPGA digital processing module;

[0037] 14- memory; 15- multi-core DSP chip; 16- power module;

[0038] 17-clock module; 18-display module; 131-digital-analog drive unit;

[0039] 132-clock generating unit; 133-logic analyzing unit; 134-data converting unit;

[0040] 135-Communication interface unit. DETAILED DESCRIPTION

[0041] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0043] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0045] In the field of digital circuit processing technology, multi-channel pulse amplitude analyzers based on analog circuits are bulky and complex in structure, and it is also very inconvenient to debug them because they use multiple analog circuits to process pulses before they can be sampled by digital-to-analog circuits.

[0046] In view of this, an embodiment of the present invention provides a digital multi-channel pulse amplitude analysis device, such as Figure 1 As shown, it includes: a signal conditioning module 11, a digital-to-analog conversion chip 12, an FPGA digital processing module 13, a memory 14, a multi-core DSP chip 15, a power module 16, a clock module 17 and a display module 18.

[0047] Among them, Figure 1 In the embodiment, the signal conditioning module 11 is used to condition the analog signal output by the preamplifier to output a double exponential pulse signal with a preset amplitude.

[0048] like Figure 2 As shown, the signal conditioning module 11 includes: a calculus circuit and an amplification bias circuit, and the calculus circuit is connected to the amplification bias circuit. The calculus circuit is a differential-integral circuit with negative feedback. Figure 2 The voltage signal V output by the preamplifier i The negative input terminal of amplifier A1 is connected through resistor R1 and capacitor C1, the positive input terminal of amplifier A1 is grounded through resistor R3, capacitor C2 is connected in parallel with resistor R2, the input terminal is connected to the negative input terminal of amplifier A1, the output terminal is connected to the output terminal of amplifier A1, the output terminal is connected to the negative input terminal of amplifier A2 through resistor R4, the positive input terminal of amplifier A2 is connected to resistor R6 and sliding resistor R8 respectively through resistor R7, resistor R6 is connected to the positive power supply +VCC, sliding resistor R8 is connected to the negative power supply -VSS, the input terminal of sliding resistor R5 is connected to the negative input terminal of amplifier A2, and the output terminal of sliding resistor R5 is connected to the output voltage V oAmong them, the models of amplifier A1 and amplifier A2 are both OPA656.

[0049] Specifically, the signal conditioning module 11 can suppress noise interference by processing high-frequency (1MHz) analog signals. For example, the "staircase" signal output from the preamplifier of the X-ray detector is shaped and filtered through a differential-integral circuit and converted into a double exponential pulse signal, and then the double exponential pulse signal is amplified and biased through an amplifier-bias circuit, so that the amplitude of the output double exponential pulse signal is within the amplitude range of the digital-to-analog conversion chip 12, that is, within the input range of the ADC. Figure 6 As shown, this is a schematic diagram of a double exponential pulse signal.

[0050] Among them, Figure 1 In the embodiment, the digital-to-analog conversion chip 12 is connected to the signal conditioning module 11 and is used to convert the conditioned double exponential pulse signal into a digital signal.

[0051] Specifically, the chip model that can be used for the digital-to-analog conversion chip 12 is AD9613, which is a 12-bit high-speed and high-precision A / D conversion chip with a sampling frequency of up to 250MSPS and an allowed input analog voltage peak-to-peak value of up to 2Vp-p. The input end of the digital-to-analog conversion chip is connected to the output end of the signal conditioning module 11, and its output end is connected to the FPGA digital processing module 13 through a standard FMC interface.

[0052] Among them, Figure 1 In the embodiment, the FPGA digital processing module 13 is connected to the digital-to-analog conversion chip 12 and is used to drive the digital-to-analog conversion chip 12 to work.

[0053] In one embodiment, Figure 3 As shown, the FPGA digital processing module 13 includes: a digital-to-analog driving unit 131 , a clock generating unit 132 , a logic analyzing unit 133 , a data converting unit 134 , and a communication interface unit 135 .

[0054] The digital-to-analog driving unit 131 is connected to the digital-to-analog conversion chip 12 and is used to drive the digital-to-analog conversion chip 12 to work. The clock generating unit 132 is connected to the clock module 17 and the digital-to-analog driving unit 131, respectively, and is used to output a second frequency clock signal (250MHz) and a third frequency clock signal (200MHz) to the digital-to-analog driving unit 131 according to the first frequency clock signal (65MHz) output by the clock module 17. Figure 3In the embodiment, the logic analysis unit 133 is connected to the digital-to-analog driving unit 131 and is used to perform logic analysis on the digital signal output by the digital-to-analog conversion chip 12. The data conversion unit 134 is connected to the clock generation unit 132 and obtains the clock signal of the third frequency (200 MHz) output by the clock generation unit 132. The communication interface unit 135 is connected to the data conversion unit 134 and is used to output the digital signal after digital processing.

[0055] For example: the FPGA digital processing module 13 drives the high-speed digital-to-analog conversion chip 12 to sample the double exponential pulse signal output by the signal conditioning module 11. In the FPGA digital processing module 13, the clock module 17 multiplies the 65MHz clock frequency it generates, and converts it into 200MHz for the data conversion unit 134 through the clock generation unit 132, and converts it into 250MHz for the digital-to-analog driving unit 131, so that the digital-to-analog conversion chip 12 driven by the digital-to-analog driving unit 131 samples and obtains a digital signal output. The data flow of the digital-to-analog conversion chip 12 has two directions, one to the logic analysis unit 133 and the other to the data conversion unit 134; and then the data packets are sent out through the communication interface unit 135 (SRIO communication interface), which contain data header information, digital-to-analog conversion sampling data and DoorBell interrupt information. As the main device of SRIO communication, the FPGA digital processing module 13 uses the DirectIO transmission mode to directly write the digital-to-analog conversion sampling data into the shared memory of the multi-core DSP chip 15. Furthermore, the FPGA digital processing module 13 adopts a ping-pong operation to write data into the memory. When the amount of data written exceeds a set threshold, a DoorBell interrupt will be generated for the multi-core DSP chip.

[0056] Among them, Figure 1 In the embodiment, the memory 14 is connected to the multi-core DSP chip 15 for storing digital signals. The memory here is a DDR3 memory, and the chip model used by the memory 14 can be MT41K128M16JT and MT41K256M16TW. The memory 14 is connected to the multi-core DSP chip 15 through a data bus and frequently accesses data with the multi-core DSP chip 15.

[0057] Among them, Figure 1 In the embodiment, the multi-core DSP chip 15 is connected to the FPGA digital processing module 13 and the memory 14 respectively, and is used to digitally process the digital signal according to a first preset algorithm using a first digital channel based on the digital signal read from the memory 14, and to digitally process the digital signal according to a second preset algorithm using a second digital channel, and send the digital signal processed by the first digital channel and the second digital channel to the memory 14 for storage.

[0058] In one embodiment, the multi-core DSP chip 15 includes: a plurality of mutually independent processors, among which one processor is used to execute a main processing task, and the remaining processors are used to execute a slave processing task.

[0059] Specifically, in Figure 1 In the example, after the multi-core DSP chip 15 receives the data sent by the FPGA digital processing module 13, it immediately reads the data from the DDR3 memory and performs trapezoidal shaping processing on the data. The 8 independent cores of the multi-core DSP chip 15 are divided into two categories, core 0 is the master core, and cores 1 to 7 are slave cores. Core 0 first configures the network initialization and SRIO communication interface initialization, and then cores 0 to 7 initialize and configure IPC, successfully establishing communication links between the cores. The network communication thread of core 0 is responsible for monitoring whether the host computer has issued instructions. Once it receives the instruction from the host computer to collect data, it immediately responds to the DoorBell interrupt of the FPGA digital processing module 13 and issues data processing and analysis instructions to the slave core. After the slave core receives the instruction issued by the master core, it immediately reads the data sampled by the digital-to-analog conversion chip 12 from the shared memory DDR3 memory.

[0060] After the master core 0 responds to the DoorBell interrupt of the FPGA digital processing module 13, it sends Notify notification information to the slave cores 1 to 7 in sequence. After the slave core responds to the Notify interrupt of the master core, it immediately reads the signal data from the shared memory DDR3 memory. In order to prevent the master core from frequently notifying other cores that are busy processing data, the master core 0 sets a busy flag variable BusyFlag for each slave core 1 to 7. When other cores are using algorithms such as trapezoidal shaping to process data, the variable of the corresponding core is set to 1, and after processing the data, the variable is cleared again. Before notifying the core, the master core 0 will first check whether this flag variable is set to 1. If it is set to 1, the master core 0 will skip this core and turn to notify the next core. Figure 4 FIG. 1 is a schematic diagram of a specific working procedure of the FPGA digital processing module 13 .

[0061] Among them, Figure 1 In the figure, the power supply module 16 is connected to the signal conditioning module 11, the digital-to-analog conversion chip 12, the FPGA digital processing module 13, and the multi-core DSP chip 15 respectively.

[0062] In one embodiment, the power module 16 converts AC power with a voltage of 220V into DC power with voltages of ±5V, ±3.3V and 12V respectively.

[0063] Specifically, the power module 16 converts the AC power with a voltage of 220V into DC power with voltages of ±5V, ±3.3V and 12V respectively. Figure 1 In the figure, the ±5V power output port of the power module 16 is connected to the power interface of the signal conditioning module 11; the ±3V power output port of the power module is connected to the power interface of the digital-to-analog conversion chip 12; the 12V power output port of the power module 16 is connected to the power interface of the FPGA digital processing module 13, the multi-core DSP chip 15 and the display module 18.

[0064] Among them, Figure 1 In the embodiment, the display module 18 is connected to the multi-core DSP chip 15 and the power module 16 respectively, and is used to display the digital signal processed by the first digital channel and the second digital channel. The display module 18 here can be a terminal device or a computer display device. Through the display module, it is convenient for users to obtain digital signal information more intuitively.

[0065] In one embodiment, the first preset algorithm forms a trapezoidal pulse by threshold positioning and pulse input counting in a fast shaping manner.

[0066] In one embodiment, the second preset algorithm forms a trapezoidal pulse through pile-up determination, peak extraction, and pulse output counting in a slow shaping manner.

[0067] The algorithms for data processing in the multi-core DSP chip include trapezoidal shaping, threshold positioning, accumulation discrimination, peak extraction, and multi-channel counting. After the slave cores 1 to 7 respond to the notification of the master core 0, they immediately read the input sampled digital signal from the DDR3 memory for fast shaping and slow shaping. The threshold positioning algorithm is used to locate the effective pulse using the output signal of the fast shaping. The pulse accumulation is discriminated based on the pulse information of the threshold positioning using the output signal of the slow shaping. The pulses that have accumulated are discarded, and for the pulses that have not accumulated, the peak extraction algorithm is used to extract the pulse peak. Finally, the number of input pulses, the number of output pulses, and the pulse amplitude are counted and corrected, and the results of the multi-channel counting are sent to the display module through network communication for display.

[0068] Specifically, the digital multi-channel pulse amplitude analysis device (DMCA for short) in the embodiment of the present invention is one of the core parts of the micro-area energy spectrum, mainly including a signal conditioning module, a digital-to-analog conversion chip, an FPGA digital processing module, a memory, a multi-core DSP chip, a power module, a clock module and a display module. Among them, the trapezoidal forming includes: fast forming and slow forming. Figure 5 As shown, the input sampled digital signal is read out from the DDR3 memory, and then the digital signal is digitally shaped in two signal processing channels, namely, fast shaping and slow shaping. Figure 5In the method, the threshold positioning algorithm is used to locate the effective pulse using the output signal of fast shaping. The pulse accumulation is judged based on the pulse information of threshold positioning using the output signal of slow shaping, and the accumulated pulses are discarded. For the pulses without accumulation, the peak extraction algorithm is used to extract the pulse peak value, and the number of input pulses, the number of output pulses and the pulse amplitude are counted and corrected. Finally, the data is stored in the memory.

[0069] Among them, fast shaping and slow shaping are two routes for processing digital pulse signals. The shaping algorithms of these two routes are both trapezoidal shaping algorithms. The derivation process of the trapezoidal shaping algorithm of the double exponential pulse is as follows. Set the input signal to the double exponential function V i , whose expression is:

[0070]

[0071] Among them, τ1 is the time constant of the preamplifier, and τ2 is an auxiliary parameter. Let V o (t) is the output shaped trapezoidal pulse signal, and its expression in the time domain is:

[0072]

[0073] in,

[0074]

[0075] Where t is the horizontal axis time, u(t) is the unit step function; y1, y2, y3, y4 are the expressions of the four-segment functions that construct the trapezoid, t a is the width of the trapezoidal rising edge, t b -t a is the width of the trapezoidal flat top, t c -t b is the width of the trapezoidal falling edge. Figure 7 Shown is a schematic diagram of the time domain change of a trapezoidal pulse signal.

[0076] Through Z-transformation, the time series expression of the trapezoidal shaping algorithm of the double exponential pulse is introduced:

[0077]

[0078] Among them, V i [n] is the double exponential pulse sequence input to the algorithm, V o [n] is the trapezoidal pulse sequence output by the algorithm, n is the sequence number, n a =t a / T s , n b =t b / T s , n c=t c / T s , d1 and d2 represent intermediate variables for easy calculation and expression; T S is the sampling period of the digital-to-analog conversion chip. The difference between the two shapes lies in the different shaping parameter values, that is, the width of the trapezoidal rising edge (t a ) and the width of the trapezoidal flat top (t b -t a ) is different. The shaping parameters of fast shaping are smaller than those of slow shaping. The advantage of such setting is that fast shaping has little accumulation of pulses after shaping due to its small shaping parameters, which is beneficial to pulse positioning and pulse input counting, but not conducive to pulse amplitude extraction; slow shaping has large shaping parameters, which makes the flat top of the pulse after shaping wide and the noise small, which is beneficial to pulse amplitude extraction.

[0079] For threshold positioning, the threshold has two functions: one is to filter out low-amplitude pulses caused by noise, and the other is to find the position of valid pulses in the pulse group and count the number of valid pulses. The original pulse group is composed of many random pulses with different amplitudes. Among them, there are pulses with very low amplitudes caused by noise. Such pulses are invalid pulses and need to be identified and eliminated. If the pulses in the pulse group have a serious pile-up phenomenon under high counting rate, in order to find the valid pulses, the first thing to do is to find where these pulses are, and then count the number of valid pulses.

[0080] The threshold location algorithm uses the set threshold to filter low-amplitude pulses and find the location of valid pulses. The specific description of the algorithm is as follows:

[0081] Let the original signal sampling sequence be V i [n] (n = 1, 2, 3, ..., N), using small forming parameters to perform trapezoidal forming, which is the fast forming f mentioned above Fast , and get the output signal sequence V F [n].

[0082]

[0083] Fast forming signal sequence V F [n] Perform first-order difference processing to obtain the differential output signal sequence V D [n]. This differential output signal sequence is only used to locate pulses and filter noise pulses and is not used for subsequent data processing.

[0084] V D [n] = V F [n]-V F [n-1],n=2,3,4,...,N;

[0085] The differential signal sequence V D [n] and threshold V TH In contrast, if V D [n]>V TH , it is considered that a valid pulse has arrived, and the input pulse count C i Add one and assign the position information at this time to the pulse position parameter P, that is, P[C i ]=n. The essence here is to find the rising edge of the trapezoidal pulse, but there is often more than one rising edge sequence, so it is only necessary to assign the position information of the first point of the rising edge to P. For the same group of pulses, different positioning results are obtained by using different thresholds. The larger the threshold is, the less likely the pulse with a smaller amplitude can be located.

[0086] For pile-up discrimination, pulse pile-up refers to the phenomenon that the time interval between the arrival of two or more pulses is too short, resulting in partial overlap. Its existence makes it more difficult to extract the peak value of the pulse. However, the trapezoidal shaping algorithm can eliminate certain pulse pile-ups. After studying the parameters t of the trapezoidal shaping, a ,t b and t c The relationship between the time interval Δt between two adjacent pulses and the effect on eliminating pulse pile-up leads to the following conclusions: (1) When Δt <t a When t a <Δt <t b When t b <Δt <t c , the trapezoidal shaping algorithm can distinguish the two accumulated pulses, but cannot filter the two pulses into independent trapezoids; (4) When Δt>t c , the trapezoidal shaping algorithm can distinguish the two accumulated pulses, and can also filter the two pulses into independent trapezoids. Therefore, a criterion for judging whether pulse accumulation can be eliminated is given: if Δt ≥ t c , it means that the pulse accumulation can be eliminated and it is determined that no accumulation occurs; otherwise, it cannot be eliminated and it is determined that accumulation occurs.

[0087] For a set of pulse signal sequences, the effective pulse position parameter P in the set of pulse signal sequences has been obtained in the "threshold pulse positioning" link. Assuming that the number of effective pulses in a set of pulse signal sequences is M, whether the i-th pulse is piled up is divided into the following cases: (1) When i = 1, if P[i+1]-P[i]≥n c , then it is determined that the i-th pulse has not accumulated; (2) When i=2,3,4,…,M-1, if P[i]-P[i-1]≥nc And P[i+1]-P[i]≥n c , then it is determined that the i-th pulse has not accumulated; (3) When i = M, if P[i]-P[i-1]≥n c , then it is determined that no accumulation occurs for the i-th pulse.

[0088] As for peak extraction, peak extraction, as the name implies, is to extract the peak value of the pulse. The pulse signal obtained by the ideal trapezoidal shaping is a trapezoidal pulse with a flat top. Therefore, it is only necessary to extract the value of any point between the flat tops as the peak value of the pulse. However, in the actual sampled signal, due to the measurement problems of noise and time constants, the pulse signal obtained by the trapezoidal shaping is often not an ideal trapezoid. The embodiment of the present invention adopts a method of taking the average value of the first half of the points at the flat top as the peak value of the pulse. The characteristic of this method is that it greatly reduces the influence of τ1. Because the influence of τ1 is macroscopic and affects all points, while τ2 only affects the first few points, the peak value extracted by the method adopted in the embodiment of the present invention is the closest to the true value.

[0089] Assume that the number of valid pulses in a pulse signal sequence is M. If the ith pulse is judged as piled up, let V p [i]=0, otherwise, V p The solution of [i] is:

[0090]

[0091] Among them, N a [i] = t a / T S +P[i],N e [i]=(t a +t b ) / 2T S +P[i],V L The original signal sampling sequence is V i [n] The output signal sequence after slow shaping, that is:

[0092]

[0093] The digital multi-channel pulse amplitude analysis device in the embodiment of the present invention uses an FPGA digital processing module and a multi-core DSP chip to implement the pulse processing function of the analog circuit between the preamplifier and the digital-to-analog conversion chip sampling in the prior art, and processes it through a first preset algorithm and a second preset algorithm. The specific process of the first preset algorithm and the second preset algorithm is that the signal output by the preamplifier is directly sampled by the digital-to-analog conversion chip after passing through a simple main amplification circuit, and then threshold positioning, pulse counting or accumulation discrimination, peak extraction, and pulse counting are implemented in the multi-core DSP chip, thereby making the digital multi-channel pulse amplitude analysis device in the embodiment of the present invention small in size, simple in structure, and convenient for debugging and modifying parameters.

[0094] Each module or device in the digital multi-channel pulse amplitude analysis device in the embodiment of the present invention can perform the operation process according to the following steps:

[0095] Step 1: The signal conditioning module shapes, filters, amplifies and biases the "staircase" signal output by the X-ray detector preamplifier, and converts it into a double exponential pulse signal with an amplitude within the input range of the digital-to-analog conversion chip;

[0096] Step 2: The FPGA digital processing module drives the digital-to-analog conversion chip to sample the double exponential pulse signal output by the signal conditioning module, and sends it to the multi-core DSP chip through the communication interface;

[0097] Step 3: After the multi-core DSP chip receives the data sent by the FPGA digital processing module, the master core responds to the DoorBell interrupt of the FPGA digital processing module and notifies the slave core to read and process the data from the DDR3 memory.

[0098] Step 4: After the multi-core DSP chip performs trapezoidal shaping through the first preset algorithm and the second preset algorithm, it counts and corrects the number of input pulses, the number of output pulses and the pulse amplitude, and sends the multi-channel counting results to the display module through network communication for display.

[0099] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A digital multi-channel pulse amplitude analysis device, characterized in that: include: A signal conditioning module, used for conditioning the analog signal output by the preamplifier to output a double exponential pulse signal of a preset amplitude; A digital-to-analog conversion chip, connected to the signal conditioning module, for converting the conditioned double exponential pulse signal into a digital signal; An FPGA digital processing module is connected to the digital-to-analog conversion chip and is used to drive the digital-to-analog conversion chip to work; A multi-core DSP chip is connected to the FPGA digital chip and the memory, respectively, and is used to digitally process the digital signal according to a first preset algorithm using a first digital channel, digitally process the digital signal according to a second preset algorithm using a second digital channel, and send the digital signal processed by the first digital channel and the second digital channel to the memory for storage; A power supply module is respectively connected to the signal conditioning module, the digital-to-analog conversion chip, the FPGA digital processing module, and the multi-core DSP chip; It also includes: a clock module, connected to the FPGA digital processing module, and used to provide a clock signal of a first frequency for the FPGA digital chip; The FPGA digital processing module includes: A digital-to-analog driving unit, connected to the digital-to-analog conversion chip, and used to drive the digital-to-analog conversion chip to work; A clock generating unit, connected to the clock module and the digital-to-analog driving unit, respectively, for outputting a clock signal of a second frequency to the digital-to-analog driving unit and outputting a clock signal of a third frequency to the data conversion unit according to the clock signal of a first frequency output by the clock module; A logic analysis unit, connected to the digital-to-analog driving unit, and configured to perform logic analysis on the digital signal output by the digital-to-analog conversion chip; a data conversion unit, connected to the clock generating unit, and acquiring the clock signal of the third frequency output by the clock generating unit; A communication interface unit, connected to the data conversion unit, for outputting a digital signal after digital processing; The first preset algorithm forms a trapezoidal pulse through threshold positioning and pulse input counting in a fast shaping manner; The second preset algorithm forms a trapezoidal pulse through pile-up determination, peak extraction, and pulse output counting in a slow forming manner.

2. The digital multi-channel pulse amplitude analysis device according to claim 1, characterized in that: Also includes: The display module is connected to the multi-core DSP chip and the power module respectively, and is used to display the digital signal processed by the first digital channel and the second digital channel.

3. The digital multi-channel pulse amplitude analysis device according to claim 1, characterized in that: The signal conditioning module comprises: a calculus circuit and an amplification bias circuit, and the calculus circuit is connected to the amplification bias circuit.

4. The digital multi-channel pulse amplitude analysis device according to claim 1, characterized in that: The multi-core DSP chip includes: a plurality of mutually independent processors, among which one processor is used to execute a main processing task, and the remaining processors are used to execute a slave processing task.

5. The digital multi-channel pulse amplitude analysis device according to any one of claims 1 to 4, characterized in that: The power supply module converts the alternating current with a voltage of 220V into direct current with voltages of ±5V, ±3.3V and 12V respectively.

6. The digital multi-channel pulse amplitude analysis device according to any one of claims 1 to 4, characterized in that: The memory is a DDR3 memory.

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