Bump structure of semiconductor package component

Abstract

The present invention discloses a bump structure of a semiconductor element. The bump structure of the semiconductor package element is formed on a first dielectric layer, and the first dielectric layer is formed on a metal layer, and an opening is formed corresponding to the metal layer portion. The bump structure of the semiconductor package element includes an under-bump metal layer, a buffer layer and a metal bump; wherein the under-bump metal layer is formed on the metal layer portion exposed in the opening, the inner wall of the opening and the top surface of the dielectric layer, so that the metal bump is formed therein; the present invention forms the buffer layer between the portion of the under-bump metal layer located on the top surface of the dielectric layer and the top surface of the dielectric layer, so as to effectively absorb the thermal stress generated in the bonding step due to the different thermal expansion coefficients of the multi-layer materials in the bump structure, thereby avoiding the thermal stress from generating cracks in the bump structure after the bonding step.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging component, and in particular to a bump structure of the semiconductor packaging component. Background Art

[0002] Bump structures are commonly found in semiconductor packaging components, for example, formed on the chip of a flip-chip packaging component or on a redistribution layer. The bump structure can provide good conductivity. For the chip of a flip-chip packaging component, multiple bump structures are formed on the metal pads of the chip, allowing the chip to be directly bonded to the carrier, which reduces the size of the semiconductor packaging component compared to wire bonding.

[0003] However, as the chip thickness becomes thinner, such as Figure 7 As shown in FIG. 1 , after the chip 40 is re-welded with the carrier 60 by the bump structure 50 thereon, it can be seen that the chip 40 is bent. The reason for this is that because the outermost layer of the bump structure 50 is the solder layer 51, in order to be successfully soldered on the carrier 60, the bump structure needs to be heated to 220° C. to 240° C. to melt the solder layer 51. During the heating and cooling process, the thermal expansion coefficients of the multiple layers of materials in the bump structure 50 are often different, such as Fig. 8A As shown, different thermal stresses will appear at the joint 52 between the bump structure 50 and the chip 40, resulting in thermal stress problems such as torsion and bending between the bump structure 50 and the chip 40; Figure 8B As shown, different stresses may cause stretching or compression at different joints between the bump structure 50 and the chip 40, and finally cracks may be generated at the joint 52 between the bump structure 50 and the chip 40, as shown in FIG. Fig. 9 As shown, the most serious crack 42 even extends inward to the circuit layer 41 of the chip 40 , damaging the circuit of the chip 40 .

[0004] Therefore, it is necessary to further improve the bump structure 50 in the prior art. Summary of the invention

[0005] In view of the above-mentioned defects of the bump structure in the prior art, the main purpose of the present invention is to provide a new bump structure for a semiconductor package element to solve the crack problem caused by thermal stress generated by different thermal expansion coefficients of the bump structure.

[0006] The main technical means used to achieve the purpose of the above invention is to form a bump structure of the semiconductor package component on a first dielectric layer of the semiconductor package component, wherein the first dielectric layer is formed on a metal layer, and an opening is formed corresponding to the metal layer portion, and the dielectric layer has a first length; wherein the bump structure includes:

[0007] An under bump metallization layer is formed on the metal layer portion exposed in the opening, the inner wall of the opening and the top surface of the first dielectric layer; wherein the portion of the under bump metallization layer formed on the top surface of the first dielectric layer has a second length;

[0008] a first buffer layer formed between the UBM portion and the top surface of the first dielectric layer, wherein the first buffer layer has a third length that is greater than the second length and less than the first length; and

[0009] A metal bump is formed on the under-bump metal layer.

[0010] The advantage of the present invention is that the bump structure of the present invention further forms the buffer layer between the portion of the metal layer under the bump located on the top surface of the dielectric layer and the top surface of the dielectric layer. The buffer layer effectively absorbs the thermal stress generated in the bonding step due to the different thermal expansion coefficients of the multiple layers of materials in the bump structure, thereby solving the cracks generated in the bump structure of the prior art after the bonding step.

[0011] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A : is a cross-sectional view of a first embodiment of a bump structure of a semiconductor package element of the present invention;

[0013] Figure 1B : is a cross-sectional view of a second embodiment of a bump structure of a semiconductor package element of the present invention;

[0014] Figure 2 : is a cross-sectional view of a third embodiment of a bump structure of a semiconductor package element of the present invention;

[0015] Figure 3 : is a cross-sectional view of a fourth embodiment of a bump structure of a semiconductor package element of the present invention;

[0016] Figure 4A : is a cross-sectional view of a fifth embodiment of a bump structure of a semiconductor package element of the present invention;

[0017] Figure 4B : is a cross-sectional view of a sixth embodiment of a bump structure of a semiconductor package component of the present invention;

[0018] Figure 5 : is a cross-sectional view of a seventh embodiment of a bump structure of a semiconductor package element of the present invention;

[0019] Figure 6 : is a cross-sectional view of an eighth embodiment of a bump structure of a semiconductor package element of the present invention;

[0020] Figure 7 : is a cross-sectional view of a semiconductor packaging component of the prior art;

[0021] Fig. 8A : A thermal stress distribution diagram of a bump structure and a chip joint of a semiconductor packaging element in the prior art;

[0022] Figure 8B : A side thermal stress distribution diagram of a bump structure of a semiconductor packaging component in the prior art;

[0023] Fig. 9 : A cross-sectional view of a local semiconductor packaging component of the prior art.

[0024] Among them, the reference numerals

[0025] 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g: bump structure

[0026] 11, 33: Metal layer

[0027] 12: Insulation layer

[0028] 13: First dielectric layer

[0029] 131: Opening

[0030] 1311: Opened metal layer portion

[0031] 1312: Opening inner wall

[0032] 132: top surface of first dielectric layer

[0033] 14: First buffer layer

[0034] 141: first buffer layer protrusion

[0035] 15: Under Bump Metal Layer

[0036] 151: Under-bump metal layer

[0037] 16, 16a: Metal bump

[0038] 161: Copper pillar layer

[0039] 162: Barrier layer

[0040] 163:Solder layer

[0041] 19: Second buffer layer

[0042] 20: Chip

[0043] 30: Rewiring layer

[0044] 31: Passivation layer

[0045] 32: Second dielectric layer

[0046] 40: Chip

[0047] 41: Circuit layer

[0048] 42: Crack

[0049] 50: Bump structure

[0050] 51:Solder layer

[0051] 52:Joint

[0052] 60: Carrier board DETAILED DESCRIPTION

[0053] The present invention aims to improve the bump structure of a semiconductor package component. The detailed technology of the present invention is described in detail below with reference to a plurality of embodiments and accompanying drawings.

[0054] First see Figure 1A 1 is a first embodiment of a bump structure 10 of a semiconductor package component of the present invention; in this embodiment, a bump structure 10 is formed on a corresponding metal layer 11 of a chip 20; wherein the chip 20 and the surrounding portion of the metal layer 11 are covered with an insulating layer 12, and a first dielectric layer 13 is formed on the insulating layer 12 and the metal layer 11 not covered by the insulating layer 12, and the first dielectric layer 13 is formed with an opening 131 corresponding to the metal layer 11 not covered by the insulating layer 12; preferably, the material of the insulating layer 12 is PSV, and the material of the first dielectric layer 13 can be polyimide (PI) or extreme low-K dielectric (ELK), and has a first length L1. In this embodiment, the bump structure 10 includes a first buffer layer 14, an under-bump metal layer 15, and a metal bump 16.

[0055] The first buffer layer 14 is formed on the top surface 132 of the first dielectric layer, and one end of the first buffer layer 14 is flush with the inner wall 1312 of the opening of the first dielectric layer 13. The first buffer layer 14 has a third length L3 that is smaller than the first length L1 of the first dielectric layer 13. In this embodiment, the Young's modulus of the first buffer layer 14 is lower than that of the first dielectric layer 13.

[0056] The above-mentioned UBM layer 15 is formed on the metal layer portion 1311 corresponding to the opening 131, the inner wall 1312 of the opening and the top surface of the first buffer layer 14, and the UBM layer 15 has a second length L2 that is smaller than the third length L3 of the first buffer layer 14. Therefore, the above-mentioned first buffer layer 14 is formed between the portion 151 of the UBM layer 15 on the top surface 132 of the first dielectric layer and the top surface 132 of the first dielectric layer.

[0057] The metal bump 16 is formed on the under-bump metal layer 15. In this embodiment, the metal bump 16 is formed with a copper pillar layer 161, a barrier layer 162 and a solder layer 163 (solder paste) in sequence from bottom to top. Preferably, the barrier layer 162 can be nickel.

[0058] From the description of the first embodiment of the present invention, it can be seen that the bump structure 10 of this embodiment mainly forms a first buffer layer 14 between the bump under metal layer portion 151 located on the top surface 132 of the first dielectric layer and the top surface 132 of the first dielectric layer to absorb the thermal stress generated in the bonding step, and further, by selecting a material with a Young's modulus lower than the Young's modulus of the first dielectric layer 13 to form the first buffer layer 14, the thermal stress absorption effect is improved, and the bump structure 10 is effectively prevented from generating cracks after the bonding step; the bump structure 10 can be applied to the flip-chip structure of semiconductor packaging components.

[0059] See also Figure 1B As shown, a second embodiment of the bump structure 10a of the semiconductor package element of the present invention; in this embodiment, the bump structure 10a is formed on a redistribution layer 30 (RDL) of a chip 20, and the redistribution layer 30 is formed on the surface of the chip 20 from bottom to top with a passivation layer 31, a second dielectric layer 32, a metal layer 33 and a first dielectric layer 13; wherein the first dielectric layer 13 is formed with an opening 131 at a portion corresponding to the metal layer 33; and the bump structure 10a is formed on a portion of the metal layer 33 corresponding to the opening 131, and includes a first buffer layer 14, a bump under metal layer 15 and a metal bump 16a.

[0060] The first dielectric layer 13, the first buffer layer 14, the under bump metallization layer 15 and the Figure 1A The first dielectric layer 13 , the first buffer layer 14 , and the UBM layer 15 in the bump structure 10 are the same, but the metal bump 16 a is formed on the UBM layer 15 , and the metal bump 16 a is a solder ball.

[0061] From the description of the second embodiment of the present invention, it can be seen that the bump structure 10a of this embodiment mainly forms a first buffer layer 14 between the bump under metal layer portion 151 located on the top surface 132 of the first dielectric layer and the top surface 132 of the first dielectric layer to absorb the thermal stress generated in the bonding step, and further improves the thermal stress absorption effect by selecting the first buffer layer 14 with a Young's modulus lower than the Young's modulus of the material of the first dielectric layer 13, thereby effectively avoiding the bump structure 10a from generating cracks after the bonding step.

[0062] See also Figure 2 FIG. 1 is a third embodiment of a bump structure 10b of a semiconductor package component of the present invention; the bump structure 10b of this embodiment is Figure 1A The bump structure 10 shown is substantially the same, except that the material of the first buffer layer 14 of the bump structure 10b is the same as the material of the first dielectric layer 13; that is, the first buffer layer 14 formed between the bump under-metal layer portion 151 and the top surface 132 of the first dielectric layer of the bump structure 10b of this embodiment increases the thickness of the first dielectric layer 132, and absorbs the thermal stress generated in the bonding step by thickening, which can also prevent the bump structure 10b from generating cracks after the bonding step; the bump structure 10b can also be applied to the flip-chip structure of semiconductor packaging components.

[0063] See also Figure 3 FIG. 1 is a fourth embodiment of a bump structure 10c of a semiconductor package component of the present invention; the bump structure 10c of this embodiment is Figure 1A The bump structure 10 shown is substantially the same, except that the surface of the first buffer layer 14 of the bump structure 10c corresponding to the under-bump metal layer 15 forms a protrusion 141 toward the under-bump metal layer 15; preferably, the protrusion 141 is cut flush with the side wall corresponding to the metal bump 16, or as shown in FIG. Figure 4A As shown, in the fifth embodiment of the bump structure 10d of the present invention, the first buffer layer protrusion 141 of the bump structure 10d further protrudes from the sidewall corresponding to the metal bump 16. In another embodiment of the present invention (not shown), the material of the first buffer layer 14 of the bump structure 10c or the bump structure 10d is the same as the material of the first dielectric layer 13.

[0064] From the description of the fourth and fifth embodiments of the present invention, it can be seen that the bump structures 10c and 10d of the two embodiments effectively increase the contact area between the first buffer layer 14 and the under-bump metal layer 15 by the protrusion 141 on the first buffer layer 14, so that the bonding between the first buffer layer 14 and the under-bump metal layer 15 is better, wherein the first buffer layer protrusion 141 of the bump structure 10d further protrudes from the side wall corresponding to the metal bump 16, thereby increasing the thickness of the first buffer layer 14; therefore, the bump structures 10c and 10d absorb the thermal stress generated in the bonding step by increasing the contact area to improve the bonding between the first buffer layer 14 and the under-bump metal layer 15 and thickening it, thereby avoiding the bump structures 10c and 10d from generating cracks after the bonding step; the bump structures 10c and 10d can also be applied to the flip chip structure of semiconductor packaging components.

[0065] See also Figure 4B FIG. 1 is a sixth embodiment of the bump structure 10e of the semiconductor package component of the present invention; the bump structure 10e of this embodiment is Figure 1B The bump structure 10a shown is substantially the same, except that the first buffer layer 14 of the bump structure 10e has a protrusion 141 as in the fourth embodiment of the present invention or a protrusion 141 as in the fifth embodiment of the present invention (not shown). In another embodiment of the present invention (not shown), the first buffer layer 14 of the bump structure 10e is made of the same material as the first dielectric layer 13.

[0066] From the description of the sixth embodiment of the present invention, it can be seen that the bump structure 10e of this embodiment effectively increases the contact area between the first buffer layer 14 and the under-bump metal layer 15 by means of the protruding portion 141 of the first buffer layer 14, so that the bonding between the first buffer layer 14 and the under-bump metal layer 15 is better, or the protruding portion 141 is further protruded from the side wall corresponding to the metal bump 16 to increase the thickness of the first buffer layer 14; therefore, the bump structure 10e absorbs the thermal stress generated in the bonding step by increasing the contact area to improve the bonding between the first buffer layer 14 and the under-bump metal layer 15 and thickening the layer, so as to avoid the bump structure 10e from generating cracks after the bonding step; the bump structure 10e can also be applied to the rewiring structure of semiconductor packaging components.

[0067] See also Figure 5 FIG. 1 is a seventh embodiment of a bump structure 10f of a semiconductor package component of the present invention; the bump structure 10f of this embodiment is Figure 1A The bump structure 10 shown is substantially the same, except that a second buffer layer 19 is further formed between the first buffer layer 14 and the under-bump metal layer 15 of the bump structure 10f, and the second buffer layer 19 has a fourth length L4; preferably, the fourth length L4 of the second buffer layer 19 is the same as the third length L3 of the first buffer layer 14, or as Figure 6As shown, in the eighth embodiment of the present invention, the fourth length L4 of the second buffer layer 19 of the bump structure 10g is less than the third length L3 of the first buffer layer 14 and greater than the second length L2 of the UBM layer 15 .

[0068] From the description of the seventh and eighth embodiments of the present invention, it can be seen that the bump structures 10f and 10g of the two embodiments further form a second buffer layer 19 between the first buffer layer 14 and the under-bump metal layer 15 to increase the thickness of the first buffer layer 14. The thermal stress generated in the bonding step is absorbed by thickening, which can also prevent the bump structures 10f and 10g from generating cracks after the bonding step. The bump structures 10f and 10g can also be applied to the flip-chip structure of semiconductor packaging components.

[0069] From the description of the above embodiments, it can be known that the bump structure of the present invention mainly forms a first buffer layer between the portion of the under-bump metal layer on the top surface of the dielectric layer and the top surface of the first dielectric layer, so as to thicken the first dielectric layer to absorb the thermal stress that is easily concentrated between the bump structure and the dielectric layer, and reduce the cracks generated by the concentration of thermal stress in the bump structure after the bonding step; in addition, the present invention can further enhance the absorption effect of thermal stress by selecting a first buffer layer with a Young's modulus lower than that of the material of the first dielectric layer, so that the elasticity of the first buffer layer is higher than that of the first dielectric layer; in addition, a second buffer layer can be further added to the first buffer layer, and the absorption effect of thermal stress can be further enhanced by utilizing the thickness or the characteristics of the thickness and the material, so as to more effectively reduce the cracks generated in the bump structure of the prior art after the bonding step. Furthermore, the protrusion formed upward by the first buffer layer also strengthens the bonding between the first buffer layer and the under-bump metal layer.

[0070] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A bump structure of a semiconductor package component, wherein the semiconductor package component comprises a metal layer and a first dielectric layer, the first dielectric layer is formed on the metal layer, and an opening is formed corresponding to a portion of the metal layer so that the metal layer portion is exposed in the opening, and the dielectric layer has a first length; characterized in that, The bump structure of the semiconductor package component comprises: An under bump metallization layer is formed on the portion of the metal layer exposed in the opening, the inner wall of the opening and the top surface of the first dielectric layer; wherein the portion of the under bump metallization layer on the top surface of the first dielectric layer has a second length; a first buffer layer formed between a portion of the under bump metallurgy layer located on the top surface of the first dielectric layer and the top surface of the first dielectric layer, wherein the first buffer layer has a third length that is greater than the second length and less than the first length, and a Young's modulus of a material of the first buffer layer is lower than that of a material of the first dielectric layer; and A metal bump is formed on the under-bump metal layer.

2. The bump structure of the semiconductor package component according to claim 1, characterized in that: The surface of the first buffer layer corresponding to the UBM layer forms a protrusion toward the UBM layer.

3. The bump structure of the semiconductor package component according to claim 1, characterized in that: A second buffer layer is further formed between the first buffer layer and the under bump metal layer.

4. The bump structure of the semiconductor package element according to claim 3, characterized in that: The length of the second buffer layer is less than the third length of the first buffer layer and greater than the second length of the under bump metallurgy layer.

5. The bump structure of the semiconductor package element according to claim 3, characterized in that: The material of the second buffer layer is different from that of the first buffer layer.

6. The bump structure of the semiconductor package component according to claim 1, characterized in that: The first dielectric layer is made of polyimide or ultra-low dielectric material.

7. The bump structure of the semiconductor package component according to claim 1, characterized in that: The metal bump is a solder ball or a metal column.

8. The bump structure of the semiconductor package element according to claim 7, characterized in that: The metal column is a copper column solder bump, wherein the copper column solder bump is sequentially stacked with a copper column layer, a barrier layer and a solder layer.

Images