A pipeline processing method, device, computer storage medium and terminal

Abstract

The present invention discloses a pipeline processing method, device, computer storage medium and terminal. In an embodiment of the present invention, a first first-in-first-out buffer (FIFO) is set for a pipeline module, and second data output when the pipeline module processes first data is stored in the first FIFO. When an error occurs in data processing according to processing status information of the first data, the error type is determined according to the second data, and corresponding interrupt processing is performed according to the determined error type, thereby improving the data processing efficiency of the pipeline processing and enhancing the processing quality and stability of the pipeline processing.

Description

Technical Field

[0001] The present invention relates to but is not limited to data processing technology, and in particular to a pipeline processing method, device, computer storage medium and terminal. Background Art

[0002] Most of the data in high-performance embedded data processing systems pass through the pipeline structure to improve the clock frequency and processing efficiency. At present, embedded data processing systems are generally implemented in a combination of software and hardware. The system contains multi-stage pipeline modules. Before the system starts, the initialization parameters are sent to the running hardware (pipeline module) through software to input the data to be processed into the first-stage pipeline module. The subsequent pipeline modules at each level process the data output by the previous-stage pipeline module step by step. After the last-stage pipeline module outputs the processing result, it is determined whether the pipeline processing has an error through the data processing result of the last-stage pipeline module; when it is determined that an error has occurred in the pipeline processing, the data processing is corrected in the first module of the pipeline processing according to the pre-set interrupt exception handling strategy. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present invention provide a pipeline processing method, device, computer storage medium and terminal, which can improve the data processing efficiency and quality of pipeline processing.

[0005] The embodiment of the present invention provides a pipeline processing method, comprising: respectively setting a first first-in-first-out buffer FIFO for each level of pipeline modules used for data pipeline processing, and further comprising:

[0006] When the pipeline module processes the first data, the second data output by the pipeline module is stored in the first FIFO corresponding to the pipeline module;

[0007] Reading processing status information of the pipeline module processing the first data, and determining whether a data processing error occurs in the pipeline module according to the processing status information;

[0008] When it is determined that a data processing error occurs in the pipeline module, the second data in the first FIFO is analyzed according to a preset error type judgment rule to determine the error type of the data processing;

[0009] According to the preset interrupt processing mode of each error type, the corresponding interrupt processing is performed on the determined error type.

[0010] On the other hand, an embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by a processor, the pipeline processing method of the above data is implemented.

[0011] In another aspect, an embodiment of the present invention further provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein:

[0012] The processor is configured to execute the computer program in the memory;

[0013] When the computer program is executed by the processor, the pipeline processing method of the data as described above is implemented.

[0014] In another aspect, an embodiment of the present invention further provides a data pipeline processing device, comprising: a setting unit, a storage unit, a first judgment unit, a second judgment unit and a processing unit; wherein,

[0015] The setting unit is configured to: respectively set a first first-in-first-out buffer FIFO for each level of pipeline module used for data pipeline processing;

[0016] The storage unit is configured to: when the pipeline module processes the first data, store the second data output by the pipeline module in the first FIFO corresponding to the pipeline module;

[0017] The first judgment unit is configured to: read the processing status information of the pipeline module processing the first data, and determine whether a data processing error occurs in the pipeline module according to the processing status information;

[0018] The second judgment unit is configured to: when determining that a data processing error occurs in the pipeline module, analyze the second data in the first FIFO according to a preset error type judgment rule to determine the error type of the data processing;

[0019] The processing unit is configured to: perform corresponding interrupt processing on the determined error type according to the preset interrupt processing mode of each error type.

[0020] The technical scheme of the present application includes: setting a first first-in-first-out buffer (FIFO) for each level of pipeline module for data pipeline processing, and also includes: when the pipeline module processes the first data, storing the second data output by the pipeline module in the first FIFO corresponding to the pipeline module; reading the processing status information of the pipeline module processing the first data, and determining whether the pipeline module has a data processing error according to the processing status information; when it is determined that the pipeline module has a data processing error, analyzing the second data in the first FIFO according to a preset error type judgment rule to determine the error type of the data processing; according to the interrupt processing mode of each error type set in advance, executing corresponding interrupt processing for the determined error type. The embodiment of the present invention sets a first FIFO for the pipeline module, stores the second data output by the pipeline module when processing the first data in the first FIFO, determines that an error occurs in the data processing according to the processing status information of the first data, determines the error type according to the second data, and executes corresponding interrupt processing according to the determined error type, thereby improving the data processing efficiency of the pipeline processing, and improving the processing quality and stability of the pipeline processing.

[0021] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0023] Figure 1 A flowchart of a pipeline processing method for data according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the module composition of the pipeline processing according to an embodiment of the present invention;

[0025] Figure 3 It is a schematic diagram of the operation of a single module in an embodiment of the present invention;

[0026] Figure 4 It is a structural block diagram of a pipeline processing device for data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0028] The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in a sequence different from that shown here.

[0029] The inventor of the present application analyzed and found that: in the related technology, after all pipeline modules have completed pipeline processing, whether an error has occurred in the pipeline processing is determined by the data processing results of the last-level pipeline module. When it is determined that an error has occurred in the pipeline processing, the data processing is corrected in the first-level pipeline module of the pipeline processing according to a pre-set interrupt exception handling strategy; the correction of the above-mentioned pipeline processing has low processing efficiency, and there may be a problem of being unable to achieve error correction, and the system stability is poor.

[0030] Figure 1 Flow chart of the pipeline processing method of data in the embodiment of the present invention, such as Figure 1 As shown, including:

[0031] Step 100, respectively setting a first first-in-first-out buffer (FIFO) for each level of pipeline module used for data pipeline processing; further comprising:

[0032] Step 101: When the pipeline module processes the first data, the second data output by the pipeline module is stored in the first FIFO corresponding to the pipeline module;

[0033] Step 102: reading processing status information of the pipeline module processing the first data, and determining whether a data processing error occurs in the pipeline module according to the processing status information;

[0034] The processing status information in the embodiment of the present invention includes: information generated by the pipeline module after executing data processing with reference to related technologies.

[0035] Step 103: When it is determined that a data processing error occurs in the pipeline module, the second data in the first FIFO is analyzed according to a preset error type judgment rule to determine the error type of the data processing;

[0036] Step 104 : According to the preset interrupt processing mode for each error type, corresponding interrupt processing is performed on the determined error type.

[0037] The pipeline processing in the embodiment of the present invention includes pipeline processing, which refers to data processing that needs to be processed step by step through multiple modules; for example, after receiving the encoded data, the data needs to be decoded and then converted according to the pre-set rules. The data that needs to be processed by the pipeline is the front-end data relative to the module.

[0038] In an exemplary embodiment, the embodiment of the present invention can execute the above-mentioned processing by a main running program in a CPU or a CPU RAM.

[0039] The embodiment of the present invention sets a first FIFO for the pipeline module, stores second data output by the pipeline module when processing the first data in the first FIFO, determines when an error occurs in data processing based on the processing status information of the first data, determines the error type based on the second data, and performs corresponding interrupt processing based on the determined error type, thereby improving the data processing efficiency of the pipeline processing and enhancing the processing quality and stability of the pipeline processing.

[0040] In an exemplary embodiment, the error type in the embodiment of the present invention includes one or any combination of the following:

[0041] A repairable error that can be corrected by modifying the second data;

[0042] An error in which the second data does not need to be modified, but the first data of the same data type as the second data needs to be modified before pipeline processing;

[0043] An error requiring re-execution of pipeline processing on the first data;

[0044] Unrecoverable error.

[0045] In an exemplary embodiment, the embodiment of the present invention can be implemented by technicians compiling a judgment code for error type judgment according to the data content specifically processed by the pipeline processing, and implementing the error type judgment by running the judgment code in the CPU.

[0046] In an exemplary embodiment, the embodiment of the present invention performs corresponding interrupt processing on the determined error type, including:

[0047] When the error type is a repairable error, before sending the second data to the next-stage pipeline module for pipeline processing, the second data is repaired according to a preset repair strategy;

[0048] When the error type is an error that is modified before pipeline processing, obtain data type information of the second data; generate a corresponding modification instruction according to the obtained data type information; and modify the first data of the same data type as the data type information according to the generated modification instruction;

[0049] When the error type is an error of re-execution of pipeline processing, the first data is restored according to the second data, and the restored first data is re-input into the pipeline module outputting the second data for pipeline processing through a preset insert command;

[0050] When the error type is an unrecoverable error, the pipeline processing of all pipeline modules is interrupted.

[0051] The interrupt processing of the pipeline in the embodiment of the present invention can be implemented by loading it into the CPU RAM in the form of a main running program.

[0052] In an exemplary embodiment, the data type information in the embodiment of the present invention includes a data tag (target) in the related art, and the first data modified by the modification instruction is determined by the data tag.

[0053] In an exemplary instance, an embodiment of the present invention can set a corresponding interrupt processing vector number for each error type of pipeline interrupt processing, and the interrupt processing for different error types can be encapsulated through an interrupt processing function; after determining the error type, an embodiment of the present invention can determine the interrupt processing vector number according to the error type, and then call the corresponding interrupt processing function according to the interrupt processing vector number.

[0054] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0055] A command queue (CQ) is set for each level of pipeline module, and the set command queue records one or any combination of the following commands:

[0056] A command to perform pipeline processing on the first data;

[0057] Modify the command;

[0058] Insert command.

[0059] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0060] A second FIFO is respectively provided for each stage of the pipeline module;

[0061] The data input to the pipeline module for processing by one or any combination of the following is written into the second FIFO in a preset priority order:

[0062] The first data corresponding to the command, the system input data and the first data corresponding to the command for pipeline processing are inserted.

[0063] In an exemplary embodiment, the embodiment of the present invention can set corresponding distinguishing information for different types of data in a data frame according to the relevant technology; distinguish the above data according to the distinguishing information, and prioritize the data based on the distinguishing results.

[0064] In an exemplary embodiment, the data written into the second FIFO by the embodiment of the present invention is sorted according to the priority level as follows: first data corresponding to the command to be processed by pipeline, first data corresponding to the insert command, and system input data.

[0065] In the embodiment of the present invention, the data is received according to a clock cycle specified by the system, and the process of writing the received data into the second FIFO includes:

[0066] When the received data includes the first data corresponding to the command for pipeline processing, the channel for transmitting the first data corresponding to the insertion command and the system input data is closed, and the first data corresponding to the command for pipeline processing is written into the second FIFO;

[0067] When the received data does not contain the first data corresponding to the command to be processed by the pipeline, determine whether the received data contains the first data corresponding to the insert command, and if the received data contains the first data corresponding to the insert command, write the first data corresponding to the insert command into the second FIFO;

[0068] When the received data does not include the first data corresponding to the command for pipeline processing and the first data corresponding to the insert command, the system input data is written into the second FIFO.

[0069] It should be noted that, after the embodiment of the present invention writes the data into the second FIFO, the data is input into the pipeline module for processing according to the first-in-first-out principle.

[0070] In an exemplary embodiment, the pipeline processing method of the embodiment of the present invention further includes:

[0071] A finish queue (FQ) is set for each stage of the pipeline module, and the read data processing status is recorded through the set finish queue.

[0072] The embodiment of the present invention records the command issued by the software to process the data through CQ, and records the data processing status after the hardware module processes the data through FQ.

[0073] In an exemplary embodiment, the pipeline processing method of the embodiment of the present invention further includes:

[0074] When it is determined according to the processing status information that no error occurs when the pipeline module processes the first data, the second data is read out from the first FIFO and output to the next pipeline processing module.

[0075] In an exemplary embodiment, the embodiment of the present invention may map the corresponding first FIFO, second FIFO, CQ and FQ for each module in the memory of the CPU.

[0076] In the embodiment of the present invention, the CPU can access the resources in the module through the bus; the CPU can realize the reading and writing of the information stored in the first FIFO, the second FIFO, the CQ and the FQ.

[0077] It should be noted that, in the embodiment of the present invention, if the module is the last-stage pipeline module of the pipeline processing, the output second data is the output of the pipeline processing. Figure 2 FIG. 1 is a schematic diagram of the pipeline module composition of the pipeline processing according to an embodiment of the present invention, such as Figure 2 As shown, the pipeline module for pipeline processing includes: a first module, a second module and a third module; the central processing unit (CPU) of the system establishes a communication connection with the first module, the second module and the third module through the system bus (BUS); wherein the first module, the second module and the third module are respectively provided with corresponding first FIFO, second FIFO, CQ and FQ; the data to be processed by pipeline is first input into the second FIFO of the first module, and the processing result is output to the first FIFO; it is determined whether the processing of the first module has an error through the data processing state; when it is determined that an error has occurred, the error type is judged by running the judgment code in the CPU, and then the pipeline interrupt processing is performed according to the determined error type; after the interrupt processing, the second data after the interrupt processing is sent to the second module. When it is determined that no error has occurred, the second data in the first FIFO is sent to the second module; the second module continues the pipeline processing with reference to the processing performed by the first module; the third module continues the pipeline processing with reference to the processing performed by the first module, until the third module outputs the second data, and the pipeline processing is completed.

[0078] Figure 3 FIG. 1 is a schematic diagram of the operation of a single pipeline module according to an embodiment of the present invention. Figure 3As shown, within the system clock cycle, the first data corresponding to the insert command, the system input data and the first data corresponding to the command for pipeline processing are connected to the second FIFO through the data selector, and the data selector writes the first data corresponding to the insert command, the system input data and the first data corresponding to the command for pipeline processing into the second FIFO in order of priority; after the data in the second FIFO is processed by the pipeline module, the second data is obtained, and the embodiment of the present invention writes the second data into the first FIFO, and determines whether an error occurs in the pipeline processing through the second data; when an error occurs in the pipeline processing, the error type is determined according to the second data, and corresponding interrupt processing is performed according to the determined error type; when no error occurs in the pipeline processing, the second data is sent to the pipeline module of the next level; in the above processing of the embodiment of the present invention, when an error occurs in the pipeline processing that is modified before the pipeline processing, the data type information of the second data is obtained; the pre-generated modification instruction is called according to the obtained data type information; the first data matching the data type information in the first FIFO is modified according to the generated modification instruction, and the modified first data is input into the pipeline module for pipeline processing. In an exemplary instance, when the error type of an embodiment of the present invention is a repairable error, the embodiment of the present invention can allow the CPU to access and repair the second data through a preset channel according to a preset repair strategy; in an exemplary instance, the embodiment of the present invention generates a repair command based on the repairable strategy, and the CPU executes the access and repair of the second data by calling the repair command.

[0079] An embodiment of the present invention further provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the pipeline processing method of the above data is implemented.

[0080] The embodiment of the present invention further provides a terminal, comprising: a memory and a processor, wherein a computer program is stored in the memory; wherein:

[0081] The processor is configured to execute the computer program in the memory;

[0082] When the computer program is executed by a processor, the pipeline processing method of the data as described above is implemented.

[0083] Figure 4 FIG. 1 is a structural block diagram of a pipeline processing device for data according to an embodiment of the present invention, such as Figure 4 As shown, it includes: a setting unit, a storage unit, a first judgment unit, a second judgment unit and a processing unit; wherein,

[0084] The setting unit is configured to: respectively set a first first-in-first-out buffer FIFO for each level of pipeline module used for data pipeline processing;

[0085] The storage unit is configured to: when the pipeline module processes the first data, store the second data output by the pipeline module in the first FIFO corresponding to the pipeline module;

[0086] The first judgment unit is configured to: read the processing status information of the pipeline module processing the first data, and determine whether a data processing error occurs in the pipeline module according to the processing status information;

[0087] The second judgment unit is configured to: when determining that a data processing error occurs in the pipeline module, analyze the second data in the first FIFO according to a preset error type judgment rule to determine the error type of the data processing;

[0088] The processing unit is configured to: perform corresponding interrupt processing on the determined error type according to the preset interrupt processing mode of each error type.

[0089] The embodiment of the present invention sets a first FIFO for the pipeline module, stores second data output by the pipeline module when processing the first data in the first FIFO, determines when an error occurs in data processing based on the processing status information of the first data, determines the error type based on the second data, and performs corresponding interrupt processing based on the determined error type, thereby improving the data processing efficiency of the pipeline processing and enhancing the processing quality and stability of the pipeline processing.

[0090] In an exemplary embodiment, the error type in the embodiment of the present invention includes one or any combination of the following:

[0091] A repairable error that can be corrected by modifying the second data;

[0092] An error in which the second data does not need to be modified, but the first data of the same data type as the second data needs to be modified before pipeline processing;

[0093] An error requiring re-execution of pipeline processing on the first data;

[0094] Unrecoverable error.

[0095] In an exemplary embodiment, the processing unit of the embodiment of the present invention is configured as follows:

[0096] When the error type is a repairable error, before sending the second data to the next-stage pipeline module for pipeline processing, the second data is repaired according to a preset repair strategy;

[0097] When the error type is an error that is modified before pipeline processing, obtain data type information of the second data; generate a corresponding modification instruction according to the obtained data type information; and modify the first data of the same data type as the data type information according to the generated modification instruction;

[0098] When the error type is an error of re-execution of pipeline processing, the first data is restored according to the second data, and the restored first data is re-input into the pipeline module outputting the second data for pipeline processing through a preset insert command;

[0099] When the error type is an unrecoverable error, the pipeline processing of all pipeline modules is interrupted.

[0100] In an exemplary embodiment, the setting unit of the embodiment of the present invention is further configured to:

[0101] A command queue is set for each level of pipeline module;

[0102] In an exemplary embodiment, the storage unit of the embodiment of the present invention is further configured to: record one or any combination of the following commands through a command queue:

[0103] A command to perform pipeline processing on the first data;

[0104] Modify the command;

[0105] Insert command.

[0106] In an exemplary embodiment, the setting unit of the embodiment of the present invention is further configured to:

[0107] A second FIFO is respectively provided for each stage of the pipeline module;

[0108] In an exemplary embodiment, the storage unit of the embodiment of the present invention is further configured to: write the following data input to the pipeline module for processing in one or any combination thereof into the second FIFO according to a preset priority order:

[0109] The first data corresponding to the command, the system input data and the first data corresponding to the command for pipeline processing are inserted.

[0110] In an exemplary embodiment, the setting unit of the embodiment of the present invention is further configured to:

[0111] Set up a completion queue for each level of pipeline module;

[0112] In an exemplary embodiment, the storage unit of the embodiment of the present invention is further configured to: record the data processing status read through the completion queue.

[0113] In an exemplary embodiment, the processing unit of the embodiment of the present invention is further configured to:

[0114] When it is determined according to the processing status information that no error occurs when the pipeline module processes the first data, the second data is read out from the first FIFO and output to the next pipeline processing module.

[0115] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A pipeline processing method for data, comprising: A first first-in-first-out buffer FIFO is respectively set for each level of pipeline module used for data pipeline processing, and also includes: When the pipeline module processes the first data, the second data output by the pipeline module is stored in the first FIFO corresponding to the pipeline module; Reading processing status information of the pipeline module processing the first data, and determining whether a data processing error occurs in the pipeline module according to the processing status information; When it is determined that a data processing error occurs in the pipeline module, the second data in the first FIFO is analyzed according to a preset error type judgment rule to determine the error type of the data processing; According to the preset interrupt processing mode of each error type, the corresponding interrupt processing is performed on the determined error type; Among them, the corresponding interrupt processing is performed on the determined error type, including: when the error type is a repairable error, before sending the second data to the next-level pipeline module for pipeline processing, the second data is repaired according to a preset repair strategy; when the error type is an error that is modified before pipeline processing, the data type information of the second data is obtained; a corresponding modification instruction is generated according to the obtained data type information; according to the generated modification instruction, the first data of the same data type as the data type information is modified; when the error type is an error for re-executing pipeline processing, the first data is restored according to the second data, and the restored first data is re-input into the pipeline module that outputs the second data for the pipeline processing through a preset insert command; when the error type is an unrepairable error, the pipeline processing of all pipeline modules is interrupted.

2. The pipeline processing method according to claim 1, characterized in that: The method further comprises: A command queue is set for each level of the pipeline module, and the command queue is used to record one or any combination of the following commands: A command to perform pipeline processing on the first data; Modify the command; The insert command.

3. The pipeline processing method according to claim 2, characterized in that: The method further comprises: A second FIFO is provided for each level of the pipeline module; The data input to the pipeline module for processing by one or any combination of the following is written into the second FIFO in a preset priority order: The first data corresponding to the insert command, the system input data and the first data corresponding to the command for pipeline processing.

4. The pipeline processing method according to any one of claims 1 to 3, characterized in that: The pipeline processing method also includes: A completion queue is set for each level of the pipeline module, and the data processing status read is recorded through the set completion queue.

5. The pipeline processing method according to any one of claims 1 to 3, characterized in that: The pipeline processing method also includes: When it is determined according to the processing status information that no error occurs when the pipeline module processes the first data, the second data is read out from the first FIFO and output to the next pipeline processing module.

6. A computer storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the data pipeline processing method according to any one of claims 1 to 5 is implemented.

7. A terminal, comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the data pipeline processing method according to any one of claims 1 to 5 is implemented.

8. A pipeline processing device, comprising: A setting unit, a storage unit, a first judgment unit, a second judgment unit and a processing unit; wherein, The setting unit is configured to: respectively set a first first-in-first-out buffer FIFO for each level of pipeline module used for data pipeline processing; The storage unit is configured to: when the pipeline module processes the first data, store the second data output by the pipeline module in the first FIFO corresponding to the pipeline module; The first judgment unit is configured to: read the processing status information of the pipeline module processing the first data, and determine whether a data processing error occurs in the pipeline module according to the processing status information; The second judgment unit is configured to: when determining that a data processing error occurs in the pipeline module, analyze the second data in the first FIFO according to a preset error type judgment rule to determine the error type of the data processing; The processing unit is configured to: perform corresponding interrupt processing for the determined error type according to the preset interrupt processing mode for each error type; Among them, the corresponding interrupt processing is performed on the determined error type, including: when the error type is a repairable error, before sending the second data to the next-level pipeline module for pipeline processing, the second data is repaired according to a preset repair strategy; when the error type is an error that is modified before pipeline processing, the data type information of the second data is obtained; a corresponding modification instruction is generated according to the obtained data type information; according to the generated modification instruction, the first data of the same data type as the data type information is modified; when the error type is an error for re-executing pipeline processing, the first data is restored according to the second data, and the restored first data is re-input into the pipeline module that outputs the second data for the pipeline processing through a preset insert command; when the error type is an unrepairable error, the pipeline processing of all pipeline modules is interrupted.

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