Multi-level trench Schottky diode and manufacturing method thereof

Abstract

The present application discloses a multi-level trench Schottky diode and a manufacturing method thereof. The Schottky diode comprises: an epitaxial wafer, comprising a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate; a deep trench arranged on the side of the epitaxial layer away from the semiconductor substrate, comprising a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench; the sidewall and the bottom of the deep trench have a doping layer; the surface of the epitaxial layer away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening and in contact with the doping layer; a cathode located on the side of the semiconductor substrate away from the epitaxial layer; a filling structure and an anode located in the deep trench, the filling structure being located between the anode and the bottom of the deep trench; the doping layer and the electric field buffer zone are both anti-doped with the epitaxial layer.

Description

Technical Field

[0001] The present application relates to the technical field of Schottky diodes, and more specifically, to a multi-level trench Schottky diode and a method for manufacturing the same. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The main structure of electronic devices to achieve various functions is the integrated circuit, and Schottky diodes are important electronic components of integrated circuits. SiC is a wide bandgap semiconductor material that has developed rapidly in the past decade. Compared with other semiconductor materials, such as Si, GaN and GaAs, SiC materials have the advantages of wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. SiC can be thermally oxidized to form silicon dioxide, making it possible to realize power devices and circuits such as SiC MOSFET and SBD (Schottky barrier diodes). Since the 1990s, power devices such as SiC MOSFET and SBD have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0004] Due to the characteristics of silicon carbide materials, if doping with a greater implantation depth is to be achieved, high-energy ion implantation will cause damage to its lattice. In order to perform doping regions with a greater depth in silicon carbide materials, it is necessary to form deep trenches in the silicon carbide material and form doping layers on the surface of the deep trenches as doping regions. However, due to the greater depth of the deep trenches, the thickness of the doping layer in the deep trenches is uneven, which affects the performance of the device. Summary of the invention

[0005] In view of this, the present application provides a multi-level trench Schottky diode and a method for manufacturing the same, the scheme is as follows:

[0006] A multi-stage trench Schottky diode, comprising:

[0007] An epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate;

[0008] A deep trench is provided on the side of the epitaxial layer away from the semiconductor substrate; the deep trench comprises a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench;

[0009] The sidewalls and bottom of the deep trench have a doping layer;

[0010] The surface of the epitaxial layer on the side facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, and the electric field buffer zone is in contact with the doped layer;

[0011] a cathode located on a side of the semiconductor substrate away from the epitaxial layer;

[0012] A filling structure and an anode located in the deep trench, wherein the filling structure is located between the anode and the bottom of the deep trench;

[0013] Wherein, the doped layer and the electric field buffer zone are both anti-doped with respect to the epitaxial layer.

[0014] Preferably, in the above-mentioned multi-stage trench Schottky diode, in the first direction, the deep trench comprises: a first partial deep trench and a second partial deep trench;

[0015] The anode fills the first portion of the deep trench and is in ohmic contact with the sidewall of the first portion of the deep trench;

[0016] The filling structure fills the second portion of the deep trench.

[0017] Preferably, in the above-mentioned multi-stage trench Schottky diode, the deep trench has n sub-trench, and n is a positive integer greater than 1;

[0018] In the first direction, the first portion of the deep trench includes at least the first n-1 sub-trench.

[0019] Preferably, in the above-mentioned multi-stage trench Schottky diode, the first portion of the deep trench also includes a portion of the nth sub-trench.

[0020] Preferably, in the above-mentioned multi-stage trench Schottky diode, the filling structure is an insulating dielectric filling structure.

[0021] Preferably, in the above-mentioned multi-stage trench Schottky diode, the filling structure comprises:

[0022] an insulating dielectric layer, wherein the insulating dielectric layer covers the sidewalls and the bottom of the second portion of the deep trench;

[0023] A polysilicon filling structure is provided, wherein the polysilicon filling structure fills the gaps between the insulating dielectric layers.

[0024] Preferably, in the above-mentioned multi-level trench Schottky diode, the thickness of the portion of the doping layer located at the bottom of the deep trench is the largest.

[0025] Preferably, in the above-mentioned multi-level trench Schottky diode, the doping layer is an ion implantation layer located in the side wall surface and the bottom surface of the deep trench.

[0026] The present application also provides a method for manufacturing a multi-level trench Schottky diode, comprising:

[0027] Provided is an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate;

[0028] A deep trench is formed on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench;

[0029] A trench structure is formed in the deep trench, wherein the trench structure comprises: a doping layer located at the sidewall and the bottom of the deep trench; a filling structure and an anode located in the deep trench, wherein the filling structure is located between the anode and the bottom of the deep trench;

[0030] forming a cathode on a side of the semiconductor substrate away from the epitaxial layer;

[0031] The surface of the epitaxial layer facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, the electric field buffer zone is in contact with the doped layer, and both the doped layer and the electric field buffer zone are anti-doped with the epitaxial layer.

[0032] Preferably, in the above manufacturing method, in the first direction, the deep trench comprises: a first portion of the deep trench and a second portion of the deep trench;

[0033] The method of forming a trench structure in the deep trench comprises:

[0034] A first insulating dielectric layer, polysilicon and a second insulating dielectric layer are sequentially formed, wherein the first insulating dielectric layer covers the surface of the epitaxial layer away from the semiconductor substrate and the surface of the deep trench; the polysilicon fills the deep trench and covers the first insulating dielectric layer; the second insulating dielectric layer covers the polysilicon and is located outside the deep trench;

[0035] Exposing the corresponding position of the electric field buffer zone and the first portion of the deep trench through an etching process;

[0036] Based on the first insulating dielectric layer, the polysilicon layer, and the second insulating dielectric layer retained on the epitaxial layer after the etching process, and the first insulating dielectric layer and the polysilicon retained in the second partial deep trench, ion implantation is performed to simultaneously form the doping layer and the electric field buffer zone.

[0037] Preferably, in the above manufacturing method, in the first direction, the deep trench comprises: a first portion of the deep trench and a second portion of the deep trench;

[0038] The method of forming a trench structure in the deep trench comprises:

[0039] Forming an insulating dielectric layer on a surface of the epitaxial layer facing away from the semiconductor substrate, wherein the insulating dielectric layer fills the deep trench;

[0040] Exposing the corresponding position of the electric field buffer zone and the first portion of the deep trench through an etching process;

[0041] Based on the insulating dielectric layer retained on the epitaxial layer after the etching process and the insulating dielectric layer retained in the second portion of the deep trench, ion implantation is performed to simultaneously form the doping layer and the electric field buffer zone.

[0042] It can be seen from the above description that in the multi-level trench Schottky diode and its manufacturing method provided by the technical solution of the present application, the multi-level trench Schottky diode includes: an epitaxial wafer, the epitaxial wafer includes a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate; a deep trench arranged on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-grooves arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in two adjacent sub-grooves, the width of the sub-groove close to the bottom of the deep trench is smaller than the width of the sub-groove away from the bottom of the deep trench; the sidewall and bottom of the deep trench have a doping layer; the surface of the epitaxial layer away from the semiconductor substrate has an electric field buffer surrounding the deep trench opening, and the electric field buffer is in contact with the doping layer; a cathode located on the side of the semiconductor substrate away from the epitaxial layer; a filling structure and an anode located in the deep trench, and the filling structure is located between the anode and the bottom of the deep trench; wherein the doping layer and the electric field buffer are both anti-doped with the epitaxial layer.

[0043] Since the depth of the deep groove is large, the thickness of the doped layer in the deep groove will gradually decrease in the first direction, especially near the opening position. Since the thickness of the doped layer is thin, leakage at this position is avoided, as well as leakage or breakdown caused by electric field concentration, which can enhance the manufacturability and reliability of the device. The technical solution of the present application realizes the voltage buffering function through an electric field buffer zone. Through a multi-level groove structure, it can avoid the contradiction between the forward conduction impedance of the device caused by a single-width groove and the withstand voltage of the Schottky region and the reliability of the surface electric field, further enhancing the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance. The electric field buffer zone can enhance the process tolerance of the device, avoid leakage near the opening caused by the Schottky contact process, as well as leakage or breakdown problems caused by electric field concentration, and enhance the manufacturability and reliability of the device.

[0044] Furthermore, by providing a filling structure in the deep trench, the reverse recovery loss can be reduced and the electric field at the bottom of the deep trench can be made uniform. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments or descriptions of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0046] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0047] Figure 1 A schematic diagram of the structure of a multi-stage trench Schottky diode provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of the structure of another multi-stage trench Schottky diode provided in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of the structure of another multi-stage trench Schottky diode provided in an embodiment of the present application;

[0050] Figure 4-Figure 17 A process flow chart of a method for manufacturing a multi-level trench Schottky diode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0052] Due to the characteristics of silicon carbide materials, the ion implantation depth can only be within 1μm, and the typical depth is 600nm. If higher energy ion implantation is used, although the implantation depth can be increased, higher energy ion implantation, especially Al ion implantation, will cause lattice damage and affect the reliability of the device.

[0053] A deep trench can be formed first, and the required doping layer can be formed in the deep trench to achieve doping at a greater depth. If the depth of the deep trench exceeds 1 μm, the ion implantation distribution will be discontinuous on the sidewall of the deep trench and the thickness will be thinner near the opening of the deep trench, resulting in device breakdown and leakage. Although the deep trench with inclined sidewalls can solve the problems of discontinuous sidewall ion implantation and thin thickness near the opening of the deep trench to a certain extent by setting the width to gradually increase from top to bottom, if the sidewall is tilted to a large extent, the cell area will be increased, affecting the integration. If the sidewall is tilted to a small extent, the improvement effect on the problem is limited, and it is difficult to mass produce.

[0054] The use of a deep trench with a multi-level trench structure can solve the problem of uneven distribution of ion implantation on the sidewall, but it cannot effectively solve the problem of thin ion implantation depth at the opening position.

[0055] In order to solve the above problems, in the technical solution of the embodiment of the present application, a multi-level groove structure is adopted to solve the problem of discontinuity of the sidewall doping layer, and through the electric field buffer zone, the reliability problem caused by the thin thickness of the doping layer at the opening position can be solved.

[0056] At present, the optimization design of breakdown voltage and on-resistance of silicon carbide SBD, especially high-voltage SBD devices, is mutually influential and contradictory. It is generally difficult to obtain low on-resistance when obtaining high breakdown voltage, especially for planar JBS (silicon carbide junction barrier Schottky diode) devices. When designing high withstand voltage, it is difficult to achieve P+ injection with a junction depth of more than 1um due to the limitation of process equipment due to the injection depth of the P+ region. In response to this problem, the industry has proposed a trench SBD structure that can achieve a deeper P+ structure. However, the SBD structure of a single-width trench needs to compromise between the trench depth and the forward conduction impedance of the device, and also needs to compromise between the trench spacing and the withstand voltage of the Schottky region between the trenches and the surface electric field strength, which brings contradictions to the design of high withstand voltage SBD devices. The technical solution of the present application provides a novel multi-level trench structure Schottky diode, constructing a novel trench SBD device, which can avoid the contradiction between the forward conduction impedance of the device and the withstand voltage of the Schottky region and the reliability of the surface electric field caused by the single-width trench structure during device design, further enhancing the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance.

[0057] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0058] like Figure 1 As shown, Figure 1 A schematic diagram of the structure of a multi-stage trench Schottky diode provided in an embodiment of the present application includes:

[0059] An epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate 11 and an epitaxial layer 12 located on a surface of the semiconductor substrate 11;

[0060] A deep trench 13 is provided on the side of the epitaxial layer away from the semiconductor substrate; the deep trench 13 includes a plurality of sub-trench 131 arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench 13 points to the bottom (i.e. Figure 1 In the direction from top to bottom in the deep groove), of two adjacent sub-grooves 131, the width of the sub-groove 131 close to the bottom of the deep groove is smaller than the width of the sub-groove 131 away from the bottom of the deep groove, that is, in the first direction, the width of the previous sub-groove 131 is larger than the width of the next sub-groove 131;

[0061] The sidewall and bottom of the deep trench 13 have a doping layer 14;

[0062] The surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 has an electric field buffer zone 15 surrounding the deep trench opening, and the electric field buffer zone 15 is in contact with the doping layer 14;

[0063] The doped layer 14 and the electric field buffer zone 15 are both counter-doped with the epitaxial layer 12 .

[0064] The depth of the sub-groove 131 directly contacting the electric field buffer zone 15 is set to t1. In the first direction, the depths of the sub-grooves of each level are sequentially t1 to tn, where n is a positive integer. The sizes and relative size relationships of t1 to tn can be set based on process requirements, and the present application embodiment does not specifically limit this.

[0065] The deep trench in the multi-level trench Schottky diode described in the embodiment of the present application is a multi-level trench structure, so the distances between the two adjacent deep trenches 13 and the sub-trench opposite to each other are S1, S2, ... Sn, respectively, and the distance between the electric field buffer regions 15 is S0, then:

[0066] S0<S1<S2<…<Sn

[0067] In the multi-level trench Schottky diode described in the embodiment of the present application, the multi-level trench structure can solve the discontinuity problem of the doping layer 14 in the deep trench. The electric field buffer zone 15 can solve the leakage and breakdown problems caused by the thin thickness of the doping layer 14 at the opening position, thereby enhancing the manufacturability and reliability of the device.

[0068] In a first embodiment, the doping layer 14 may be formed by an ion implantation process. In this case, the doping layer 14 is an ion implantation layer located in the sidewall surface and the bottom surface of the deep trench 13 .

[0069] When the doping layer 14 is formed by an ion implantation process, the doping layer 14 and the electric field buffer zone 15 can be formed simultaneously by the same ion implantation. In this case, the electric field buffer zone 15 and the doping layer 14 are located in the same ion implantation layer. In other embodiments, the doping layer 14 and the electric field buffer zone 15 can be prepared separately by two ion implantation processes. In this case, the electric field buffer zone 15 and the doping layer 14 are different ion implantation layers.

[0070] In the second implementation manner, the doping layer 14 may also be formed by an epitaxial process. In this case, the doping layer 14 is an epitaxial covering layer covering the sidewall surface and the bottom surface of the deep trench 13 .

[0071] When the doping layer 14 is formed by an epitaxial process, the doping layer 14 and the electric field buffer zone 15 may be formed simultaneously by the same epitaxial process. At this time, the electric field buffer zone 15 and the doping layer 14 are the same epitaxial covering layer.

[0072] In the embodiment of the present application, the epitaxial layer 12 is a silicon carbide epitaxial layer, and the depth of the deep trench 13 is not less than 1 μm. Due to the properties of silicon carbide materials, it is impossible to directly form an ion implantation region with a depth of not less than 1 μm by ion implantation. The technical solution of the present application can form a doped layer 14 in a greater depth of the silicon carbide material through a multi-level trench structure.

[0073] Optionally, in a direction parallel to the epitaxial wafer (i.e. Figure 1 In the horizontal direction), the width L of the electric field buffer zone 15 is 200nm-500nm to achieve better anti-leakage and anti-breakdown effects.

[0074] In the embodiment of the present application, the semiconductor substrate 11 and the epitaxial layer 12 are of the same type doped, and the doping concentration of the semiconductor substrate 11 is relatively large. For example, the semiconductor substrate 11 can be set to be N+ type doped (N type heavily doped), and the epitaxial layer 12 can be N- type doped (N type lightly doped). The doped layer 14 and the electric field buffer zone 15 are of the same type doped, and both are anti-doped with the epitaxial layer 12. For example, the doped layer 14 and the electric field buffer zone 15 can be set to be P+ type doped (P type heavily doped).

[0075] like Figure 2 As shown, Figure 2 A schematic diagram of the structure of another multi-stage trench Schottky diode provided in an embodiment of the present application, based on Figure 1 As shown, Figure 2 The structure shown also includes: a cathode 172 located on a side of the semiconductor substrate 11 away from the epitaxial layer 12;

[0076] A filling structure 16 and an anode 171 are located in the deep trench 13 , wherein the filling structure 16 is located between the anode 171 and the bottom of the deep trench 13 ; the anode 171 extends to the outside of the deep trench 13 , and covers a portion of the surface of the epitaxial layer 12 away from the semiconductor substrate 11 .

[0077] A patterned anode 171 is provided on the surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 , and the anode 171 has Schottky contact with the electric field buffer 15 and the doped layer 14 and the filling structure 16 in the deep trench 13 ;

[0078] In the first direction, the deep trench 13 includes: a first partial deep trench and a second partial deep trench; the anode 171 fills the first partial deep trench and is in ohmic contact with the sidewall of the first partial deep trench; and the filling structure 16 fills the second partial deep trench.

[0079] The P-type doped layer 14 on the sidewall of the deep trench serves as a reverse voltage-resistant shielding structure, and the P-type doped layer 14 on the sidewall of the first portion of the deep trench forms an ohmic contact with the anode metal, which can improve the surge current resistance of the device.

[0080] The anode 171 is in ohmic contact with the sidewall of the first portion of the deep trench.

[0081] The deep trench 13 has n sub-trenchs 131 , where n is a positive integer greater than 1; in the first direction, the first portion of the deep trench includes at least the first n-1 sub-trenches 131 .

[0082] The larger the area of ​​ohmic contact between the P-type doped layer 14 and the anode metal, the better the surge resistance. Therefore, in the first direction, the first part of the deep groove is set to include part of the nth sub-groove 131. This can protect the bottom of the groove, make the electric field at the bottom of the groove uniform, reduce leakage, and switch capacitance and loss. At the same time, the area of ​​the ohmic contact area between the P-doped layer 14 on the side wall of the groove and the anode metal in the groove will not be sacrificed too much, ensuring the surge current resistance of the device.

[0083] In other embodiments, the depth of the second portion of the deep trench may also be set to be greater than the depth of the nth sub-trench 131 .

[0084] Among them, the epitaxial layer 12 has a cell region and a terminal region 19. The terminal region 19 includes a junction termination extension (JTE) or a field limiting ring (FLR). The deep trench 13 is located in the cell region, and the surface of the epitaxial layer 12 on one side away from the semiconductor substrate 11 is covered with an insulating dielectric layer 18 in the area outside the anode 171, and the insulating dielectric layer 18 includes silicon nitride and silicon dioxide. The epitaxial layer 12 has a cutting area 20 for cutting and separating different devices. The anode 171 is a composite metal layer structure formed by two or more metals such as Ti / TiW / Mo / Pt / Al. The anode 171 forms a Schottky contact in the part that contacts the surface of the epitaxial layer 12. Figure 2 In the illustrated method, the filling structure 16 is an insulating dielectric filling structure, such as silicon oxide. At this time, the insulating dielectric layer and the P-type doping layer 14 at the bottom of the trench act as a mitigation shielding layer for the electric field, compared to the method in which the bottom of the trench is in direct contact with the anode metal. Figure 2 The approach shown can make the reverse capacitance lower.

[0085] like Figure 3 As shown, Figure 3 A schematic diagram of the structure of another multi-stage trench Schottky diode provided in an embodiment of the present application, based on Figure 2 As shown, Figure 3In the illustrated embodiment, the filling structure 16 includes: an insulating dielectric layer 161, the insulating dielectric layer 161 covers the sidewalls and the bottom of the second portion of the deep trench; and a polysilicon filling structure 162, the polysilicon filling structure 162 fills the gap between the insulating dielectric layers 161. The anode 171 contacts the trench sidewalls and the polysilicon filling structure 162 in the filling structure 16 in the deep trench 13, and can form a non-ohmic contact or an ohmic contact. Figure 3 In the method shown, Figure 2 Based on the polysilicon filling structure 162, a trench MOS diode (TBMS) structure can be constructed at the bottom of the trench. Figure 2 The structure shown, Figure 3 The electric field distribution at the bottom of the trench in the structure shown is more uniform, and the reverse capacitance can also be reduced compared to the method in which the bottom of the trench is in direct contact with the anode metal.

[0086] The SBD structure is prone to generate a high electric field area at the bottom of the deep trench. Especially if the bottom of the deep trench is in direct contact with the metal, a high electric field is likely to be generated, causing the device to break down prematurely or leak electricity at the corner of the trench. The anode metal is also prone to form metal spikes directly at the bottom of the deep trench. Even if various efforts are made to make the deep trench smoother, there will still be a high electric field problem at the bottom, making it difficult to stably mass-produce reliable devices.

[0087] The multi-level trench junction barrier Schottky diode with bottom filling structure provided in the embodiment of the present application is based on the filling structure 16 at the bottom of the deep trench to construct a novel trench Schottky device, which can avoid the reliability problems such as leakage and breakdown caused by the high electric field at the groove angle of the trench JBS device due to the direct contact between the anode metal layer and the bottom of the deep trench at the bottom of the deep trench. By composite filling the bottom of the multi-level trench JBS, direct contact between the anode metal and the bottom is avoided.

[0088] Figure 3 In the illustrated embodiment, the polysilicon filling structure 162 at the bottom of the deep trench 13 forms a MOS capacitor structure with the SiC P-type doped region 14 at the bottom and sidewalls through a surrounding insulating dielectric layer 161, which does not affect the shielding of the Schottky region electric field by the P-type region, and at the same time can alleviate the high electric field at the bottom, avoid premature breakdown and leakage at the bottom, and enhance the manufacturability and reliability of the device.

[0089] The filling structure 16 can be equivalent to a series capacitor to reduce reverse recovery loss and can also make the electric field at the bottom of the trench uniform.

[0090] Optionally, the thickness of the doped layer 14 is the largest at the bottom of the deep trench 13. The bottom of the trench is an electric field concentration area. Setting the thickness of the doped layer 14 at the bottom of the deep trench 13 to be the largest can improve the withstand voltage capability of the device and enhance the device performance.

[0091] The embodiment of the present application provides a novel multi-level trench Schottky diode, which realizes the voltage buffering function through the electric field buffer 15. The multi-level trench structure can avoid the contradiction between the forward conduction impedance of the device caused by the single-width trench and the withstand voltage of the Schottky region and the reliability of the surface electric field, further enhancing the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance. The electric field buffer 15 can enhance the process tolerance of the device, avoid leakage near the opening of the Schottky contact process, and leakage or breakdown caused by electric field concentration, and enhance the manufacturability and reliability of the device.

[0092] Based on the above embodiments, another embodiment of the present application further provides a method for manufacturing a multi-level trench Schottky diode, such as Figure 4-Figure 6 As shown, the production method includes:

[0093] Step S11: Figure 4 As shown, an epitaxial wafer is provided. The epitaxial wafer includes a semiconductor substrate 11 and an epitaxial layer 12 located on the surface of the semiconductor substrate 11 .

[0094] Step S12: Figure 5 As shown, a deep trench 13 is formed on the side of the epitaxial layer 12 away from the semiconductor substrate 11; the deep trench 13 includes a plurality of sub-trench 131 arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench 13 points to the bottom; of two adjacent sub-trench 131, the width of the sub-trench 131 close to the bottom of the deep trench 13 is smaller than the width of the sub-trench 131 away from the bottom of the deep trench 13;

[0095] The deep groove 13 is made by ICP, RIE or laser hole burning. Two or more levels of sub-grooves are made by two or more photolithography and etching. The bottom sub-groove can be completed by etching the photolithography alignment mark layer of the wafer in the first step.

[0096] Step S13: Figure 6 As shown, a trench structure is formed in the deep trench 13, and the trench structure includes: a doping layer 14 located on the sidewall and bottom of the deep trench 13; a filling structure 16 and an anode 171 located in the deep trench 13, and the filling structure 16 is located between the anode 171 and the bottom of the deep trench 13

[0097] Step S14: forming a cathode 172 on the side of the semiconductor substrate away from the epitaxial layer, forming Figure 3 The multi-stage trench Schottky diode shown.

[0098] The surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 has an electric field buffer zone 15 surrounding the opening of the deep trench 13, and the electric field buffer zone 15 is in contact with the doped layer 14. Both the doped layer 14 and the electric field buffer zone 15 are anti-doped with the epitaxial layer 12.

[0099] exist Figure 6 In the illustrated embodiment, the filling structure 16 includes an insulating layer 161 and a polysilicon filling structure 162. Obviously, the filling structure 16 may also include an insulating dielectric filling structure to form a structure as shown in FIG. Figure 2 The multi-stage trench Schottky diode shown.

[0100] In the manufacturing method described in the embodiment of the present application, the deep trench 13 may be provided with M sub-trench 131. In the first direction, the M sub-trench 131 are sequentially from the first-order sub-trench to the M-order sub-trench, where M is a positive integer greater than 1, and M=n. Figure 5 After forming the deep trench 13, a doping layer 14 is formed which is doped inversely to the epitaxial layer 12, including: Figure 7 As shown, the same ion implantation can be performed in the surface of the surrounding area of ​​the deep trench 13 opening, the sidewall surface of each sub-groove 131, and the step ( Figure 7 Ions are implanted synchronously in the surface of the M-th level sub-groove (in the area indicated by the dotted circle) and in the bottom surface of the M-th level sub-groove to form the electric field buffer zone 15 and the doping layer 14 synchronously; wherein the electric field buffer zone 15 and the doping layer 14 are located in the same ion implantation layer. In this method, the first mask 01 is required to be used for ion implantation, and the first mask 01 has ion implantation windows 011 corresponding to the deep grooves 13 one by one, and the ion implantation windows 011 expose the corresponding deep grooves 13 and the area around their openings corresponding to the electric field buffer zone 15.

[0101] When ion implantation is performed in the deep trench 13, by controlling the ion implantation direction, P+ ion implantation is performed at a certain angle in the side wall, so as to form a doping layer 14 in the side wall surface.

[0102] In another embodiment, before forming the deep trench 13, Figure 8As shown, the electric field buffer region 15 is formed by one ion implantation. The second mask 02 may be used for ion implantation. The second mask 02 has ion implantation windows 011 corresponding to the deep trenches 13. The ion implantation windows 011 expose the corresponding deep trenches 13 and the area around their openings corresponding to the electric field buffer region 15. The first mask 01 and the second mask 02 are the same mask.

[0103] Then as Fig. 9 As shown, a deep trench 13 is formed. After the deep trench 13 is formed, the deep trench 13 penetrates the electric field buffer region 15, and the electric field buffer region 15 contacts the sidewall of the first-level sub-trench.

[0104] based on Figure 8 and Fig. 9 , forming a doping layer 14 that is anti-doped with the epitaxial layer 12, comprising:

[0105] like Fig.10 As shown, by another ion implantation, simultaneous ion implantation is performed in the sidewall surfaces of each sub-groove 131, in the step surface between two adjacent sub-grooves 131, and in the bottom surface of the M-th sub-groove to form the doping layer 14;

[0106] The electric field buffer region 15 and the doping layer 14 are different ion implantation layers. At this time, the doping concentrations of the electric field buffer region 15 and the doping layer 14 may be the same or different.

[0107] exist Fig.10 In the illustrated manner, a third mask 03 is used for ion implantation. The third mask 03 has ion implantation windows 011 corresponding to the deep trenches 13 one by one. The ion implantation windows 011 expose the corresponding deep trenches 13 and shield other areas.

[0108] exist Figure 7-Figure 10 In the illustrated method, the doping layer 14 is formed first, and then the filling structure 16 and the anode 171 are formed.

[0109] In other embodiments, after forming the deep trench 13 , the filling structure 16 and the anode 171 may be formed first, and then the doping layer 14 may be formed.

[0110] In one way, if you make Figure 3 In the device structure shown, when the filling structure 16 and the anode 171 are formed first, and then the doping layer 14 is formed, the method for forming the trench structure in the deep trench includes:

[0111] Step S21, as Fig.11As shown, a first insulating dielectric layer 161, polysilicon 162 and a second insulating dielectric layer 163 are formed in sequence, wherein the first insulating dielectric layer 161 covers the surface of the epitaxial layer 12 away from the semiconductor substrate 11 and the surface of the deep trench 13; the polysilicon 162 fills the deep trench 13 and covers the first insulating dielectric layer 161; the second insulating dielectric layer 163 covers the polysilicon 162 and is located outside the deep trench 13; in this step, the first insulating dielectric layer 161, polysilicon 162 and the second insulating dielectric layer 163 can be formed in sequence by LPCVD or PECVD process. The first insulating dielectric layer 161 has a thickness of 10nm-200nm, and serves as an adhesion layer between the polysilicon 162 and the epitaxial layer 11, and a stop layer for subsequent etching of the polysilicon 162. The thickness of polysilicon 162 is 10nm-2000nm, and it is used as the main ion implantation masking material for subsequent P-type ion implantation in the trench; the thickness of second insulating dielectric layer 163 is 10nm-2000nm, and it is used as the contact layer of photoresist during photolithography. In other methods, the second insulating dielectric layer 163 may not be formed.

[0112] Step S22, as Figure 12-14 As shown, the corresponding position of the electric field buffer zone 25 and the first portion of the deep trench are exposed through an etching process.

[0113] First Fig.12 As shown, based on the mask, the second insulating dielectric layer 163 is etched to form an opening at the position corresponding to the deep trench 13. First, an etching gas having a high selectivity ratio for etching the second insulating dielectric layer 163: polysilicon 162, such as one or more of CF4, CHF3, CH2F2, C4F8, and a mixed gas of oxygen, nitrogen, and argon is used to etch the second insulating dielectric layer 163 on the surface, and the etching stops at the surface of the polysilicon 162.

[0114] For example Fig.13 As shown, based on the mask, the polysilicon 162 in the first part of the deep trench and the corresponding position of the electric field buffer 15 is removed. The polysilicon 162 is etched by using an etching gas with a high selectivity ratio for the polysilicon 162: the first insulating dielectric layer 161, such as HBr gas; during the etching process, a part of the polysilicon 162 filled in the trench will also be etched away.

[0115] In such Fig.14 As shown, based on the mask, the first insulating dielectric layer 161 in the first part of the deep trench and the corresponding position of the electric field buffer 15 is removed. Next, a gas having good etching properties for the first insulating dielectric layer 161, such as one or more of CF4, CHF3, CH2F2, C4F8, and a mixed gas of oxygen, nitrogen, and argon are used to etch the first insulating dielectric layer 161; the final etching result is as shown in FIG. Fig.14 As shown, a portion of the first insulating dielectric layer 161 and the polysilicon 162 will remain at the bottom of the groove, wherein the polysilicon 162 will protrude slightly more than the first insulating dielectric layer 161, that is, the filling structure 16 is away from the side of the semiconductor substrate 11, and the height of the first insulating dielectric layer 161 is less than the height of the polysilicon 162, so that the anode metal and the polysilicon filling structure can form a stable and reliable contact. At the same time, at the bottom of the groove, the first insulating dielectric layer 161 surrounds and surrounds the polysilicon 162, so that a stable and reliable MOS capacitor structure is formed through the filling structure, which does not affect the shielding of the Schottky region electric field by the P-type doping layer 14, and can also alleviate the high electric field at the bottom, avoid premature breakdown and leakage at the bottom, and enhance the manufacturability and reliability of the device.

[0116] Step S23, as Fig.15 As shown, based on the first insulating dielectric layer 161, the polysilicon layer 162, and the second insulating dielectric layer 163 retained on the epitaxial layer 11 after the etching process, the first insulating dielectric layer 161 and the polysilicon 162 retained in the second portion of the deep trench are ion implanted to simultaneously form the doping layer 14 and the electric field buffer 15. P-type doping of SiC generally uses high-energy Al ion implantation, and the polysilicon layer 162 can form a good ion implantation mask.

[0117] Step S24, as Fig.16 As shown, the film structure on the surface of the epitaxial layer 11 is removed to facilitate the formation of the anode 171 in the subsequent process steps. The three-layer structure on the surface of the epitaxial layer 12 is removed by dry etching or wet etching process; and the first insulating dielectric layer 161 and polysilicon 162 at the bottom of the trench are thick and confined to the bottom of the trench, and the etching speed is slow, so some of them will be left. Finally, the structure is formed as shown in FIG. Figure 3 The bottom composite filling of the multi-level trench JBS shown in the figure avoids direct contact between the anode metal and the bottom of the trench. The polysilicon 162 at the bottom of the trench forms a MOS capacitor structure through a layer of SiC P-type doped layer 14 surrounding the first insulating dielectric layer 161 and the bottom and sidewall of the trench. It does not affect the shielding of the Schottky region electric field by the P-type doped layer 14, and at the same time can alleviate the high electric field at the bottom, avoid premature breakdown and leakage at the bottom, and enhance the manufacturability and reliability of the device.

[0118] Alternatively, if you make Figure 2 In the device structure shown, when the filling structure 16 and the anode 171 are formed first, and then the doping layer 14 is formed, the method for forming the trench structure in the deep trench includes:

[0119] Step S31, as Fig.17As shown, an insulating dielectric layer 164 is formed on the surface of the epitaxial layer away from the semiconductor substrate, and the insulating dielectric layer 164 fills the deep trench 13.

[0120] Step S32: exposing the corresponding position of the electric field buffer zone and the first portion of the deep trench through an etching process.

[0121] Step S33, performing ion implantation based on the insulating dielectric layer remaining on the epitaxial layer and the insulating dielectric layer remaining in the second portion of the deep trench after the etching process, to simultaneously form the doping layer and the electric field buffer zone.

[0122] Step S34, removing the insulating dielectric layer on the surface of the epitaxial layer to facilitate the formation of an anode in subsequent process steps.

[0123] Steps 32 to 34 are similar to the above process flow and will not be described in detail here. Figure 2 In the device structure shown, the bottom of the trench is filled with only an insulating dielectric layer, which is equivalent to a thickened dielectric buffer layer at the bottom of the trench, and can also play a role in alleviating the bottom electric field and breakdown.

[0124] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0125] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0126] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0127] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-stage trench Schottky diode, characterized in that: include: An epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate; A deep trench is provided on the side of the epitaxial layer away from the semiconductor substrate; the deep trench comprises a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench; The sidewalls and bottom of the deep trench have a doping layer; The surface of the epitaxial layer facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, and the electric field buffer zone is in contact with the doped layer; a cathode located on a side of the semiconductor substrate away from the epitaxial layer; A filling structure and an anode located in the deep trench, wherein the filling structure is located between the anode and the bottom of the deep trench; Wherein, the doped layer and the electric field buffer zone are both anti-doped with the epitaxial layer; In the first direction, the deep trench includes: a first portion of the deep trench and a second portion of the deep trench; the anode fills the first portion of the deep trench and is in ohmic contact with the sidewall of the first portion of the deep trench, and the anode also extends to the outside of the deep trench to cover a portion of the surface of the epitaxial layer away from the semiconductor substrate; the filling structure fills the second portion of the deep trench; The deep trench has n sub-grooves, where n is a positive integer greater than 1; in the first direction, the first portion of the deep trench includes at least the first n-1 sub-grooves; in the first direction, the first portion of the deep trench also includes part of the nth sub-groove.

2. The multi-stage trench Schottky diode according to claim 1, characterized in that: The filling structure is an insulating medium filling structure.

3. The multi-stage trench Schottky diode according to claim 1, characterized in that: The filling structure comprises: An insulating dielectric layer, wherein the insulating dielectric layer covers the sidewalls and the bottom of the second portion of the deep trench; A polysilicon filling structure is provided, wherein the polysilicon filling structure fills the gaps between the insulating dielectric layers.

4. The multi-stage trench Schottky diode according to claim 1, characterized in that: The portion of the doping layer located at the bottom of the deep trench has the largest thickness.

5. The multi-stage trench Schottky diode according to claim 1, characterized in that: The doping layer is an ion implantation layer located in the sidewall surface and the bottom surface of the deep trench.

6. A method for manufacturing a multi-stage trench Schottky diode according to any one of claims 1 to 5, characterized in that: include: Provided is an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate; A deep trench is formed on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench; A trench structure is formed in the deep trench, wherein the trench structure comprises: a doping layer located at the sidewall and the bottom of the deep trench; a filling structure and an anode located in the deep trench, wherein the filling structure is located between the anode and the bottom of the deep trench; forming a cathode on a side of the semiconductor substrate away from the epitaxial layer; The surface of the epitaxial layer facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, the electric field buffer zone is in contact with the doped layer, and both the doped layer and the electric field buffer zone are anti-doped with the epitaxial layer.

7. The manufacturing method according to claim 6, characterized in that: In the first direction, the deep trench comprises: a first portion of the deep trench and a second portion of the deep trench; The method of forming a trench structure in the deep trench comprises: A first insulating dielectric layer, polysilicon and a second insulating dielectric layer are sequentially formed, wherein the first insulating dielectric layer covers the surface of the epitaxial layer away from the semiconductor substrate and the surface of the deep trench; the polysilicon fills the deep trench and covers the first insulating dielectric layer; the second insulating dielectric layer covers the polysilicon and is located outside the deep trench; Exposing the corresponding position of the electric field buffer zone and the first portion of the deep trench through an etching process; Based on the first insulating dielectric layer, the polysilicon layer, and the second insulating dielectric layer retained on the epitaxial layer after the etching process, and the first insulating dielectric layer and the polysilicon retained in the second partial deep trench, ion implantation is performed to simultaneously form the doping layer and the electric field buffer zone.

8. The manufacturing method according to claim 6, characterized in that: In the first direction, the deep trench comprises: a first portion of the deep trench and a second portion of the deep trench; The method of forming a trench structure in the deep trench comprises: Forming an insulating dielectric layer on a surface of the epitaxial layer facing away from the semiconductor substrate, wherein the insulating dielectric layer fills the deep trench; Exposing the corresponding position of the electric field buffer zone and the first portion of the deep trench through an etching process; Based on the insulating dielectric layer retained on the epitaxial layer after the etching process and the insulating dielectric layer retained in the second portion of the deep trench, ion implantation is performed to simultaneously form the doping layer and the electric field buffer zone.

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