A semiconductor device wafer dynamic parameter testing and sorting system and method

Abstract

The present invention provides a semiconductor device wafer dynamic parameter test sorting system and method, which obtains test mode, test parameters and sorting conditions, generates corresponding control instructions according to the above information; controls the positioning needle unit to move to the top of the chip to be tested and needles; performs double pulse test and / or gate charge test according to the control instruction; obtains test data of the parameter test unit, extracts the dynamic parameters of the current chip under test, and classifies the chip under test according to the pre-set sorting and filing conditions. The present invention can perform dynamic characteristic test and chip sorting on the wafer of semiconductor devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of power device packaging and testing, and in particular relates to a semiconductor device wafer dynamic parameter testing and sorting system and method. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] The third generation of semiconductor devices represented by SiCMOSFET has excellent performance and has great application potential in high voltage, high temperature, high frequency, high power and radiation resistance. The use of SiC materials to replace traditional Si materials is one of the main technical trends in the power device industry. In typical applications such as DC / DC converters, photovoltaic inverters, and active bridge inverters, SiCMOSFET, as a switch tube, can well meet the high-frequency working requirements, thereby greatly improving energy conversion efficiency, while reducing the size of passive devices such as inductors, which helps to develop lighter and more efficient systems.

[0004] In order to verify the working characteristics of SiC MOSFET at high frequency, whether in the device design and development stage or the system application design stage, SiC MOSFET must be dynamically tested to examine its switching performance under specific working conditions.

[0005] However, the current testing and sorting of SiCMOSFET in the industry is still based on static characteristics sorting tests, and no dynamic performance tests are performed on it at the wafer level. The current chip testing and sorting of power devices and modules such as MOSFET and IGBT before packaging only includes static parameter tests such as threshold voltage, on-resistance, and parasitic capacitance, which cannot directly reflect the switching performance of the chip. There are still certain differences in the dynamic performance of chips sorted by conventional methods. This difference has little effect on SiIGBTs with relatively long switching time and relatively low operating frequency, but it has a great impact on SiCMOSFETs with extremely short switching time and higher operating frequency. In multi-chip parallel applications and high-power SiC modules, the difference in dynamic characteristics between chips has a significant impact. Power modules usually adopt a multi-core parallel layout mode, so conventional sorting tests are not conducive to the dynamic current sharing design of power modules, which will at least have the following effects: First, it will cause the power module to be used at a lower frequency, and it will not be able to give full play to the advantages of SiCMOSFET in working at high frequencies; second, dynamic current imbalance will cause chips that turn on quickly and turn off slowly to bear overcurrent during the switching process. Since SiCMOSFET often works at a higher switching frequency, the switching loss accounts for a larger proportion of the total power loss within a certain working time, and the heat difference between different chips is greater, which will increase the risk of burning out the power module. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a semiconductor device wafer dynamic parameter testing and sorting system and method. The present invention can perform dynamic characteristic testing and chip sorting on wafers of semiconductor devices such as SiCMOSFET.

[0007] According to some embodiments, the present invention adopts the following technical solutions:

[0008] A semiconductor device wafer dynamic parameter testing and sorting system, comprising:

[0009] A positioning needle-piercing unit includes a wafer stage, a probe located above the wafer stage, and an image acquisition module located above the probe, wherein the wafer stage and the probe can move relative to each other, and the image acquisition module is used to identify and locate the chip on the wafer stage;

[0010] The control unit is configured to obtain the test mode, test parameters and sorting conditions, and generate corresponding control instructions according to the above information to control the movement of the positioning needle unit and the test of the parameter test unit;

[0011] The parameter test unit includes a double pulse test or / and a gate charge test module, each of which is configured to perform a double pulse test or / and a gate charge test according to a control instruction of the control unit;

[0012] The data processing unit is configured to obtain the test data of the parameter testing unit, extract the dynamic parameters of the chip under test, and then classify the chip under test according to pre-set sorting and filing conditions, and feed back the classification information to the control unit.

[0013] As an optional implementation, a vacuum suction hole is provided on the upper portion of the wafer stage, and the top of the wafer stage is a high-conductivity material layer for direct contact with the chip drain.

[0014] As an optional embodiment, a movable mechanism is disposed at the lower portion of the wafer stage, and the movable mechanism is used to drive the wafer stage to perform three-dimensional movement or / and rotational movement relative to the probe.

[0015] As an optional embodiment, the probe comprises a pin card for fixing and a probe group detachably connected to the pin card. The probe group can be replaced according to the chip size and pad arrangement.

[0016] The working method based on the above system includes the following steps:

[0017] (1) Obtaining the test mode, test parameters and sorting conditions, and generating corresponding control instructions based on the above information;

[0018] (2) Control the movement of the positioning needle insertion unit, move the probe to the top of the chip to be tested and insert the needle;

[0019] (3) According to the control instruction, the parameter test unit performs a double pulse test and / or a gate charge test;

[0020] (4) The data processing unit obtains the test data of the parameter test unit, extracts the dynamic parameters of the chip under test, and classifies the chip under test according to pre-set sorting and filing conditions.

[0021] As an optional embodiment, the specific process of controlling the movement of the positioning needle puncture unit in step (2) includes:

[0022] (2-1) Place the wafer on a chip stage and move the stage to the test area;

[0023] (2-2) Determine the needle insertion height, by moving and rotating the wafer stage so that the probe is facing a chip to be tested, and determine the needle insertion height by observation and control instructions to ensure that the probe can effectively contact the chip without inserting the needle too deep and damaging the chip;

[0024] (2-3) By moving and rotating the wafer stage and using the image acquisition module to identify and locate the chip, the absolute position of the wafer stage when the probe is facing each chip to be tested is recorded, and a MAP diagram for continuous testing is generated. After the probe is inserted, a positioning completion signal is fed back.

[0025] As an optional implementation, in the step (3), the specific process of performing a double pulse test and / or a gate charge test includes: adjusting the test conditions according to the instructions, and performing a double pulse test or a gate charge test, collecting the chip drain current, the voltage across the drain and source, and the voltage across the gate and source, and transmitting the collected signal to the data processing unit.

[0026] As an optional implementation, in step (4), the specific process of classifying the chip under test according to the pre-set sorting and filing conditions includes: extracting data according to international industry standards and user-set measurement parameters, referring to the sorting interval set by the user, analyzing and matching the measurement data and waveform, and determining the grade of the current chip.

[0027] As an optional implementation, when performing wafer testing, steps (2)-(4) are executed in a loop until all chips have completed the test.

[0028] As a further limitation, the archived results are obtained and stored, and the control unit determines whether the current chip is the last one based on the MAP diagram. If not, a control instruction is issued to the positioning needle unit again. The positioning needle unit jumps to the next chip to be tested according to the MAP diagram and inserts the needle, and feeds back a secondary positioning completion signal to the control unit; if it is determined that the current chip is the last one, the test is completed and the chip to be tested is exited.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention proposes a semiconductor chip sorting method. Compared with the conventional chip sorting method in the industry, the present invention innovatively proposes a wafer-level dynamic test of semiconductor chips, thereby adding reference indicators of dynamic parameters when sorting chips, and classifying semiconductor chips according to their actual dynamic performance. Therefore, the dynamic current sharing design of multi-core parallel silicon carbide power modules can be optimized from the perspective of chip sorting, thereby improving the high-frequency performance and reliability of the silicon carbide power modules.

[0031] The present invention proposes a semiconductor chip testing and sorting system, which combines a wafer testing probe station and a power device dual pulse / gate charge testing platform. On the one hand, the testing system is directly integrated on the probe station, and on the other hand, the power semiconductor device-level testing method is introduced into the wafer-level testing, providing a new testing idea and method for the testing of power chips in the industry.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0034] Figure 1 It is a structural schematic diagram of the positioning needle unit;

[0035] Figure 2 Test schematics for dynamic parameter testing units;

[0036] Figure 3 Test flow chart for SiCMOSFET wafer test and sorting system;

[0037] Figure 4 Dynamic parameter test option for SiCMOSFET wafers. DETAILED DESCRIPTION

[0038] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0039] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0040] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0041] This embodiment partially exemplarily proposes a SiCMOSFET chip testing and sorting system, which includes the following parts:

[0042] (1) The control unit is the control center of the entire wafer testing and sorting system. The control unit has a user interface that allows users to flexibly select test modes, input test parameters and sorting conditions; it can coordinate and control each unit of the system, send instructions to each unit and receive feedback through serial port communication, thereby controlling each process of wafer testing;

[0043] (2) Positioning needle unit is the motion unit of the wafer testing and sorting system, such as Figure 1 As shown, it is divided into three parts. The first is a probe card with a test busbar. The probe card itself is a fixed component, but the probe group can be replaced according to the chip size and pad arrangement. It is used to install probes and act as a test busbar; the second is a six-inch horizontal wafer stage with a vacuum suction hole on the top. It can move three-dimensionally relative to the probe card or rotate around the central axis under the control of the control unit. It is used to carry the wafer and perform relative positioning of the probe. At the same time, the top of the wafer stage is made of high-conductivity material, which is in direct contact with the chip drain. The test line directly connects it to the needle card; the third is a positioning and identification device, the main component of which is a CCD camera installed just above the probe, which is used to identify and locate the chip;

[0044] It should be noted that although in fact only the wafer stage can move and rotate freely, what the CCD camera observes is only the movement of the probe on the wafer. To conform to people's common language habits, the probe movement, positioning, needle insertion and other actions described in the following text are all relative movements, while they are actually absolute movements of the wafer stage.

[0045] (3) Dynamic parameter test unit is the test center of the wafer test sorting system. It includes two test platforms: double pulse test and gate charge test. It has the equipment and components required for testing and can be divided into power end, control end and acquisition end. The power end includes high and low voltage DC power supply, adjustable inductor, high power capacitor, current limiting resistor; the control end includes the drivers and signal generators corresponding to the two test platforms; the acquisition end includes oscilloscope and current sensor, voltage sensor, communication unit, etc. Figure 2As shown, the test principle is designed with reference to IEC 60747-8-4, and the test system can select two test modes according to the settings.

[0046] Of course, the two test platforms of the double pulse test and the gate charge test can use platforms of other structures, which will not be described in detail here.

[0047] As an exemplary explanation, when the double pulse test is selected, the test uses an inductor as the load, and the load is anti-parallel connected with a freewheeling diode to simulate the actual operating conditions of the chip.

[0048] The test steps are as follows: first, use a high-voltage power supply to charge the capacitor until the voltage VDD specified by the test conditions, and then the control end sends two consecutive pulse signals to the gate of the chip under test (DUT), with one signal time long and one short. The SiCMOSFET chip under test is turned on and off twice, and the collected data of the first shutdown and the second startup are taken as the test data.

[0049] When the first pulse lasts, due to the presence of the load inductance at the power end, the drain current ID increases linearly, and the growth rate is proportional to the busbar voltage and inversely proportional to the load inductance. When the current reaches the ID specified in the experimental conditions, the first pulse ends, the DUT is turned off, and the power end current continues to flow between the diode and the load inductance and the magnitude remains unchanged. When the second pulse arrives, the DUT turns on again, the drain-source voltage drops from VDD to the conduction voltage drop, and the drain current increases from 0 to the ID at the end of the first pulse.

[0050] The second pulse ends after a certain period of time, and the DUT is turned off again. At this point, a double pulse test is completed. The gate voltage VGS, drain-source current ID, and drain-source voltage VDS that are continuously monitored during the opening and closing process are transmitted as test data to the data processing and sorting and archiving unit to extract and analyze the switching time, switching energy, and switching waveform.

[0051] When the gate charge test is selected, the test uses a resistor as the load. The test steps are as follows: first, use a high-voltage power supply to charge the capacitor until the voltage VDD specified by the test condition is reached, ensuring that the gate voltage VGS of the DUT is at the turn-off voltage corresponding to the set test condition, and then the control end provides a constant positive gate current to the gate of the chip under test (DUT) until the gate voltage VGS reaches the corresponding value of the set test condition and then stops. During this period, the gate voltage VGS increases linearly with time until the DUT is fully turned on and stops outputting the gate current; after a period of time, the control end provides a reverse constant gate current to the gate, during which the gate voltage VGS decreases linearly with time until it is completely turned off. At this point, a gate charge test is completed, and the gate voltage VGS, drain-source current ID, and drain-source voltage VDS continuously monitored during the opening and closing process are recorded as test data and transmitted to the data processing and sorting and archiving unit for gate charge extraction and analysis.

[0052] (4) The data processing and sorting and archiving unit is the data post-processing unit of the wafer test sorting system. It can receive the original test data output by the test unit acquisition end, extract the dynamic parameters of the current chip under test according to the preset industry standard, and then classify the chip under test according to the user-defined sorting and archiving conditions, and feed back the classification information to the control unit.

[0053] like Figure 3 As shown, the specific test and sorting steps of the above SiCMOSFET wafer test and sorting system are as follows:

[0054] Step 1: The control unit selects the test mode and test parameters, and sets the test conditions and sorting conditions; see Figure 4 ,The specific test modes are divided into double pulse test and gate charge test, both of which have corresponding test parameters and test conditions, which need to be defined by yourself;

[0055] Step 2: The positioning needle unit identifies and locates the chip.

[0056] (2-1) Loading. Place the wafer on the chip stage and move the stage to the test area;

[0057] (2-2) Determine the needle insertion height. Move and rotate the wafer stage so that the probe is facing a certain chip, and determine the needle insertion height through observation and test procedures. After that, the position of the wafer stage will not be higher than this height, and the wafer stage can only be moved when it is lower than this height;

[0058] (2-3) MAP generation. The positioning needle unit moves and rotates the wafer stage and uses a CCD camera to identify and locate the chip. It then records the absolute position of the wafer stage when the probe is facing each chip to be tested, and generates a MAP for continuous testing and feeds it back to the control unit. Finally, the probe automatically moves to the top of the first chip to be tested and inserts the needle, and feeds back a positioning completion signal to the control unit.

[0059] Step 3: Execute the automatic test procedure.

[0060] (3-1) The control unit sends a start test signal and test conditions to the dynamic parameter test unit. The test unit adjusts the test conditions according to the instructions and performs a double pulse test or a gate charge test. The acquisition end uses a coaxial shunt to collect the chip drain current, collects the voltage across the drain source through a high-voltage differential probe, and measures the voltage across the gate source through a low-voltage differential probe. The oscilloscope collects the signals and transmits the switching waveform data to the data processing and sorting and archiving unit through the serial port program.

[0061] (3-2) The data processing and sorting archiving unit extracts data according to international industry standards and the measurement parameters set by the user, and then analyzes and matches the measurement data and waveform with reference to the sorting interval set by the user and the algorithm embedded in the system to determine the grade of the current chip, and the obtained sorting data is fed back to the control unit;

[0062] (3-3) The control unit obtains and stores the results of the data processing and sorting and archiving units, and determines whether the current chip is the last one according to the MAP. If not, it sends a control instruction to the positioning and puncturing unit again, and the probe jumps to the next chip to be tested according to the MAP and punctures, and feeds back a secondary positioning completion signal to the control unit; if it is determined that the current chip is the last one, it jumps to step 4;

[0063] (3-4) The control unit sends a start test signal and test conditions to the dynamic parameter test unit again, starts testing the second chip, and jumps to step (3-1);

[0064] Step 4: After the test is completed, the wafer is ejected. The control unit generates the test and sorting results of the wafer, and controls the wafer stage to fall and exit the test area.

[0065] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0066] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0067] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0070] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A semiconductor device wafer dynamic parameter test sorting system, characterized by: include: The positioning needle-piercing unit includes a wafer stage, a probe located above the wafer stage, and an image acquisition module located above the probe, wherein the wafer stage and the probe move relative to each other, and the image acquisition module is used to identify and locate the chip on the wafer stage; A control unit is configured to obtain a test mode, test parameters and sorting conditions, and generate corresponding control instructions according to the test mode, test parameters and sorting conditions to control the movement of the positioning needle unit and the test of the parameter test unit; The parameter test unit includes a double pulse test or / and a gate charge test module, each of which is configured to perform a double pulse test or / and a gate charge test according to a control instruction of the control unit; The data processing unit is configured to obtain the test data of the parameter test unit, extract the dynamic parameters of the chip under test, and then classify the chip under test according to the pre-set sorting and filing conditions, and feed back the classification information to the control unit; The control unit is provided with a user interface for flexibly selecting test modes, inputting test parameters and sorting conditions; The specific process of the double pulse test or / and the gate charge test includes: adjusting the test conditions according to the instructions, performing a double pulse test or a gate charge test, collecting the chip drain current, the voltage across the drain source and the voltage across the gate source, and transmitting the collected signals to the data processing unit; The specific process of classifying the chips under test according to the preset sorting and filing conditions includes: extracting data according to international industry standards and user-set measurement parameters, referring to the sorting interval set by the user, analyzing and matching the measurement data and waveform, and determining the grade of the current chip.

2. A semiconductor device wafer dynamic parameter test sorting system as claimed in claim 1, characterized in that: The upper part of the wafer stage is provided with a vacuum suction hole, and the top of the wafer stage is a high-conductivity material layer for direct contact with the chip drain.

3. A semiconductor device wafer dynamic parameter testing and sorting system as claimed in claim 1, characterized in that: A movable mechanism is disposed at the lower portion of the wafer stage, and the movable mechanism is used to drive the wafer stage to perform three-dimensional movement or / and rotational movement relative to the probe.

4. A semiconductor device wafer dynamic parameter testing and sorting system as claimed in claim 1, characterized in that: The probe comprises a needle card for fixing and a probe group detachably connected to the needle card.

5. A working method based on the system according to any one of claims 1 to 4, characterized in that: The following steps are involved: (1) Obtaining test mode, test parameters and sorting conditions, and generating corresponding control instructions according to the test mode, test parameters and sorting conditions; (2) Control the movement of the positioning needle insertion unit, move the probe to the top of the chip to be tested and insert the needle; (3) According to the control instruction, the parameter test unit performs a double pulse test and / or a gate charge test; (4) The data processing unit obtains the test data of the parameter test unit, extracts the dynamic parameters of the chip under test, and classifies the chip under test according to the pre-set sorting and filing conditions; In the step (3), the specific process of performing the double pulse test or / and the gate charge test includes: adjusting the test conditions according to the instructions, performing a double pulse test or a gate charge test, collecting the chip drain current, the voltage across the drain source and the voltage across the gate source, and transmitting the collected signals to the data processing unit; In step (4), the specific process of classifying the chip under test according to the pre-set sorting and filing conditions includes: extracting data according to international industry standards and user-set measurement parameters, referring to the sorting interval set by the user, analyzing and matching the measurement data and waveform, and determining the grade of the current chip.

6. The working method according to claim 5, characterized in that: The specific process of controlling the movement of the positioning needle-piercing unit in step (2) includes: (2-1) Place the wafer on the chip stage and move the stage to the test area; (2-2) Determine the needle insertion height by moving and rotating the wafer stage so that the probe is facing a chip to be tested, and determine the maximum limit of the needle insertion height by observation and control instructions; (2-3) By moving and rotating the wafer stage and using the image acquisition module to identify and locate the chip, the absolute position of the wafer stage when the probe is facing each chip to be tested is recorded, and a continuous test is generated. MAP Figure 1. The probe sends a positioning completion signal after insertion.

7. The working method according to claim 5, characterized in that: When performing wafer testing, steps (2)-(4) are executed repeatedly until all chips have completed testing.

8. The working method according to claim 7, characterized in that: Obtain and store the archived results, the control unit MAP Figure determines whether the current one is the last one. If not, it sends a control command to the positioning needle unit again. The positioning needle unit MAP The figure jumps to the next chip to be tested and inserts the needle, and feeds back a secondary positioning completion signal to the control unit; if it is determined that the current one is the last one, the test is completed and the chip to be tested is exited.

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