3D NAND memory formation method

Abstract

A method for forming a 3D NAND memory, forming a storage structure and a polysilicon layer located on the storage structure in a channel through hole, after the surface of the polysilicon layer is lower than the top surface of the dielectric layer, forming a first metal silicide layer and a through hole contact metal layer located on the first metal silicide layer on the surface of the polysilicon layer; replacing the sacrificial layer with a control gate structure; forming a first through hole in the dielectric layer to expose a part of the surface of the well region on one side of the stacked structure and a plurality of second through holes to expose the surface of the corresponding step structure; forming a second metal silicide layer on the surface of the well region at the bottom of the first through hole; forming a first contact plug in the first through hole, and forming a second contact plug in the second through hole. The present invention can adjust the thickness of the formed first metal silicide layer separately, so that the thickness of the formed first metal silicide layer meets the performance requirements.

Description

[0001] This application is a divisional application of a Chinese patent application filed on October 19, 2020, with application number 202011117206.4 and invention name “Method for forming a 3D NAND memory”. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing, and in particular to a 3D NAND memory and a method for forming the same. Background Art

[0003] NAND flash memory is a better storage device than hard disk drives. As people pursue non-volatile storage products with low power consumption, light weight and good performance, it has been widely used in electronic products. At present, the planar structure of NAND flash memory has reached the practical expansion limit. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D structure NAND memory is proposed.

[0004] Existing 3D The NAND memory generally comprises: a semiconductor substrate having a well region; a stack structure having control gates and isolation layers alternately stacked on the semiconductor substrate, and one end of the stack structure having a step structure; a dielectric layer covering the stack structure and the semiconductor substrate on one side of the stack structure; a channel through hole penetrating the dielectric layer and the stack structure, a storage structure located in the channel through hole, and the surface of the storage structure is lower than the surface of the dielectric layer; a polysilicon layer located in the remaining channel through hole on the storage structure and a first metal silicide layer located on the surface of the polysilicon layer, and the surface of the first metal silicide layer is flush with the surface of the dielectric layer; a first through hole located in the dielectric layer exposing a part of the well region surface on one side of the stack structure and a second through hole exposing the corresponding step structure surface; a second metal silicide layer located on the well region surface at the bottom of the first through hole; a first contact plug located in the first through hole connected to the second metal silicide layer; a second contact plug located in the second through hole connected to the step structure; a bit line located on the stack structure and connected to the first metal silicide layer, and the size of the bit line is smaller than the size of the channel through hole or the first metal silicide layer.

[0005] The thickness of the first metal silicide layer formed by the existing process is difficult to meet the performance requirements. Summary of the invention

[0006] The technical problem to be solved by the present invention is how to form a first metal silicide layer with a thickness that meets performance requirements.

[0007] The present invention provides a method for forming a 3D NAND memory, comprising:

[0008] A semiconductor substrate is provided, wherein the semiconductor substrate has a well region, a stacking structure in which sacrificial layers and isolation layers are alternately stacked is formed on the well region of the semiconductor substrate, and an end of the stacking structure has a step structure;

[0009] forming a dielectric layer covering the semiconductor substrate and the stacked structure;

[0010] Forming a plurality of channel through holes penetrating the thickness of the stack structure in the dielectric layer and the stack structure;

[0011] forming a storage structure and a polysilicon layer on the storage structure in the channel through hole, wherein a surface of the polysilicon layer is lower than a top surface of the dielectric layer;

[0012] forming a first metal silicide layer and a through-hole contact metal layer located on the first metal silicide layer on the surface of the polysilicon layer;

[0013] replacing the sacrificial layer with a control gate structure;

[0014] Forming a first through hole exposing a portion of the surface of the well region on one side of the stacked structure and a plurality of second through holes exposing the surfaces of the corresponding step structures in the dielectric layer;

[0015] forming a second metal silicide layer on the surface of the well region at the bottom of the first through hole;

[0016] A first contact plug connected to the second metal silicide layer is formed in the first through hole, and a second contact plug connected to the corresponding stepped structure surface is formed in the second through hole.

[0017] Optionally, the formation process of the first metal silicide layer and the through-hole contact metal layer is as follows: forming a first metal layer in the channel through-hole on the surface of the dielectric layer and the polysilicon layer; annealing the first metal layer to allow the first metal layer to react with a portion of the polysilicon layer on the storage structure to form a first metal silicide layer on the surface of the polysilicon layer, wherein the surface of the first metal silicide layer is lower than the top surface of the dielectric layer; removing the unreacted first metal layer, and forming a through-hole contact metal layer on the surface of the first metal silicide layer, wherein the surface of the through-hole contact metal layer is flush with the top surface of the dielectric layer.

[0018] Optionally, the material of the first metal silicide layer is nickel silicide, cobalt silicide, tantalum silicide, titanium silicide, or a combination thereof.

[0019] Optionally, the formation process of the control gate structure is: forming a hard mask layer on the stacked structure; forming a gate groove in the hard mask layer and the stacked structure; removing the sacrificial layer along the gate groove; forming a control gate structure at the position where the sacrificial layer is removed; and forming an array common source in the gate groove.

[0020] Optionally, the method further includes: forming a bit line connected to the through-hole contact metal layer in the hard mask layer, wherein a size of the bit line is smaller than a size of the through-hole contact metal layer.

[0021] Optionally, the formation process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line includes: etching the hard mask layer and the dielectric layer, forming a first through hole exposing a portion of the surface of the well region on one side of the stacked structure and a plurality of second through holes exposing the corresponding step structure surface in the hard mask layer and the dielectric layer, and forming a third through hole exposing a portion of the surface of the through hole contacting the metal layer in the hard mask layer, wherein the size of the third through hole is smaller than the size of the through hole contacting the metal layer; forming a second metal layer in the first through hole and on the surface of the hard mask layer; performing annealing to react the second metal layer with silicon in the well region to form a second metal silicide layer on the surface of the well region; removing the unreacted second metal layer; filling the first through hole, the second through hole and the third through hole with a metal layer, forming a first contact plug connected to the second metal silicide layer in the first through hole, forming a second contact plug connected to the corresponding step structure surface in the second through hole, and forming a bit line connected to the through hole contacting the metal layer in the third through hole.

[0022] Optionally, the second metal silicide layer material is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide.

[0023] Optionally, the storage structure includes a charge storage layer located on the sidewall surface of the channel through hole and a channel layer located on the sidewall surface of the charge storage layer.

[0024] Optionally, the charge storage layer includes a blocking layer located on the side wall surface of the channel through hole, a charge trapping layer located on the side wall surface of the blocking layer, and a tunneling layer located on the side wall surface of the charge trapping layer.

[0025] Optionally, the control gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] The method for forming a 3D NAND memory of the present invention comprises forming a storage structure and a polysilicon layer located on the storage structure in a channel through hole, after the surface of the polysilicon layer is lower than the top surface of the dielectric layer, forming a first metal silicide layer and a through hole contact metal layer located on the first metal silicide layer on the surface of the polysilicon layer; replacing the sacrificial layer with a control gate structure; forming a first through hole in the dielectric layer to expose a part of the surface of the well region on one side of the stacked structure and a plurality of second through holes to expose the surface of the corresponding step structure; forming a second metal silicide layer on the surface of the well region at the bottom of the first through hole; forming a first contact plug connected to the second metal silicide layer in the first through hole, and forming a second contact plug connected to the surface of the corresponding step structure in the second through hole. The step of forming the first metal silicide layer and the subsequent step of forming the second metal silicide are not performed in the same step, so when forming the first metal silicide, the thickness of the formed first metal silicide layer can be adjusted separately, so that the thickness of the first metal silicide layer is not limited by the process of forming the second metal silicide layer, so that the thickness of the formed first metal silicide layer meets the performance requirements.

[0028] Furthermore, the formation process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line includes: etching the hard mask layer and the dielectric layer, forming a first through hole exposing a partial surface of the well region on one side of the stacked structure and a plurality of second through holes exposing the corresponding step structure surface in the hard mask layer and the dielectric layer, and forming a third through hole exposing a partial surface of the through hole contacting the metal layer in the hard mask layer, wherein the size of the third through hole is smaller than the size of the through hole contacting the metal layer; forming a second metal layer in the first through hole and on the surface of the hard mask layer; performing annealing to react the second metal layer with the silicon in the well region to form a second metal silicide layer on the surface of the well region; removing the unreacted second metal layer; filling the first through hole, the second through hole and the third through hole with a metal layer, forming a first contact plug connected to the second metal silicide layer in the first through hole, forming a second contact plug connected to the corresponding step structure surface in the second through hole, and forming a bit line connected to the through hole contacting the metal layer in the third through hole. Since the first metal silicide layer is formed first and then the second metal silicide layer is formed, not only can the thickness of the first metal silicide layer be controlled independently to meet the performance requirements, but also there is no need to form a mask layer when forming the first metal silicide layer (the position of the first metal silicide layer is directly defined by the channel through hole), and only one mask process (hard mask layer) is required to form the second metal silicide layer and the first contact plug, the second contact plug and the bit line, and a smaller bit line can be formed through one mask process, saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1-Figure 9FIG. 4 is a schematic cross-sectional structural diagram of a formation process of a 3D NAND memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As mentioned in the background art, the thickness of the first metal silicide layer formed by the existing process is difficult to meet the performance requirements.

[0031] Research has found that the thickness of the existing first metal silicide layer is too thick and does not meet performance requirements. Further research has found that the existing first metal silicide layer and the second metal silicide layer are formed in the same process step. Since a lower contact resistance is required when the first contact plug is connected to the well region, more metal needs to be deposited when forming the second metal silicide layer. The hole depth in the storage structure is shallow. If the same amount of metal is deposited, the thickness of the formed first metal silicide layer will be thicker when the metal is annealed.

[0032] In addition, since the size of the bit line is smaller than the size of the channel through hole or the first metal silicide layer, an additional mask process is required (a mask process is required when forming the first metal silicide layer and the second metal silicide layer, and another mask process is required when forming the bit line). That is, the mask process for forming the bit line is not compatible with the mask process for forming the first metal silicide layer and the second metal silicide layer, which increases the cost.

[0033] To this end, the present invention provides a method for forming a 3D NAND memory, wherein a storage structure and a polysilicon layer located on the storage structure are formed in a channel through hole, and after the surface of the polysilicon layer is lower than the top surface of the dielectric layer, a first metal silicide layer and a through hole contact metal layer located on the first metal silicide layer are formed on the surface of the polysilicon layer; the sacrificial layer is replaced with a control gate structure; a first through hole exposing a partial surface of a well region on one side of a stacked structure and a plurality of second through holes exposing a corresponding step structure surface are formed in the dielectric layer; a second metal silicide layer is formed on the surface of the well region at the bottom of the first through hole; a first contact plug connected to the second metal silicide layer is formed in the first through hole, and a second contact plug connected to the corresponding step structure surface is formed in the second through hole. The step of forming the first metal silicide layer and the subsequent step of forming the second metal silicide are not performed in the same step. Therefore, when forming the first metal silicide, the thickness of the formed first metal silicide layer can be adjusted separately, so that the thickness of the first metal silicide layer will not be limited by the process of forming the second metal silicide layer, so that the thickness of the formed first metal silicide layer meets the performance requirements.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0035] Figure 1-9 FIG. 4 is a schematic cross-sectional structural diagram of a formation process of a 3D NAND memory according to an embodiment of the present invention.

[0036] refer to Figure 1 , providing a semiconductor substrate 100, wherein the semiconductor substrate 100 has a well region 110, and a stacking structure 111 in which sacrificial layers 103 and isolation layers 104 are alternately stacked is formed on the well region 110 of the semiconductor substrate, and the end of the stacking structure 111 has a step structure 11; forming a dielectric layer 105 covering the semiconductor substrate 100 and the stacking structure 111; forming a plurality of channel through holes penetrating the thickness of the stacking structure in the dielectric layer 105 and the stacking structure 111; forming a storage structure 108 and a polysilicon layer 109 located on the storage structure 108 in the channel through holes.

[0037] The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

[0038] The semiconductor substrate 100 has a well region 110. The well region 110 may be a P-type well region.

[0039] The stacked structure 111 includes a plurality of alternately stacked sacrificial layers 103 and isolation layers 104, wherein the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate structure is formed at the location where the sacrificial layers 103 are removed. The isolation layers 104 serve as electrical isolation between control gates of different layers and between the control gate and other devices (conductive contact portions, channel holes, etc.).

[0040] The sacrificial layer 103 and the isolation layer 104 are alternately stacked, which means that after forming a sacrificial layer 103, an isolation layer 104 is formed on the surface of the sacrificial layer 103, and then the steps of forming the sacrificial layer 103 and the isolation layer 104 on the sacrificial layer 103 are sequentially repeated. In this embodiment, the bottom layer of the stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.

[0041] In one embodiment, a buffer oxide layer 101 is further formed between the stack structure 111 and the semiconductor substrate 100 .

[0042] The number of layers of the stacked structure 111 (the number of layers of the double-layer stacked structure of the sacrificial layer 103 and the isolation layer 104 in the stacked structure 111) is determined according to the number of storage units to be formed in the vertical direction. The number of layers of the stacked structure 111 can be 8 layers, 32 layers, 64 layers, etc. The more layers of the stacked structure 111, the higher the integration. In this embodiment, only 6 layers of the stacked structure 111 are used as an example for description.

[0043] The sacrificial layer 103 and the isolation layer 104 are made of different materials. When the sacrificial layer 103 is subsequently removed, the sacrificial layer 103 has a high etching selectivity relative to the isolation layer 104. Therefore, when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, thereby ensuring the flatness of the isolation layer 104.

[0044] The material of the isolation layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of the sacrificial layer 103 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. In this embodiment, the material of the isolation layer 104 is silicon oxide, the material of the sacrificial layer 103 is silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by chemical vapor deposition process.

[0045] In one embodiment, the bottommost sacrificial layer 103 in the stacked structure 111 can be used as a bottom select gate sacrificial layer, and a bottom select gate (Bottom Selective Gate, BSG) can be formed correspondingly at the position where the bottom select gate sacrificial layer is removed. The topmost sacrificial layer 103 in the first stacked structure 111 is used as a top select gate sacrificial layer, and a top select gate (Top Selective Gate, TSG) is formed correspondingly at the position where the top select gate sacrificial layer is removed.

[0046] One end of the stacking structure 111 has a step structure 11 , and the step structure 11 includes a plurality of steps that are gradually raised in a step-like manner.

[0047] The top surface of the dielectric layer 105 is higher than the top surface of the stacked structure 111. The material of the dielectric layer 105 is silicon oxide. The formation process of the dielectric layer 105 can be a plasma enhanced chemical vapor deposition process, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a high density plasma chemical vapor deposition process or an atomic layer chemical vapor deposition process.

[0048] In one embodiment, after a number of channel through holes are formed in the dielectric layer 105 and the stacked structure 111, the semiconductor substrate 100 exposed at the bottom of the channel through hole is continuously etched to form a groove in the semiconductor substrate 100; a semiconductor epitaxial layer is formed in the groove by a selective epitaxial process, the surface of the semiconductor epitaxial layer is lower than the surface of the bottom isolation layer 104 and higher than the surface of the semiconductor substrate 100, and the material of the semiconductor epitaxial layer is silicon, germanium or silicon germanium; a storage structure 108 is formed on the semiconductor epitaxial layer, the surface of the storage structure 108 is lower than the surface of the dielectric layer 105; a polysilicon layer 109 is formed on the storage structure 108 to fill the remaining channel through holes, and the surface of the polysilicon 109 is flush with the surface of the dielectric layer 105. Here, the storage structure 108 is a channel structure.

[0049] The storage structure 108 includes a charge storage layer 107 located on the sidewall surface of the channel through hole and a channel layer 106 located on the surface of the charge storage layer 107 .

[0050] In one embodiment, the charge storage layer 107 includes a blocking layer located on the sidewall surface of the channel through hole, a charge capture layer located on the sidewall surface of the blocking layer, and a tunneling layer located on the sidewall surface of the charge capture layer. The materials of the blocking layer and the tunneling layer are silicon oxide, the material of the charge capture layer is silicon nitride, and the material of the channel layer 106 is polysilicon.

[0051] refer to Figure 2 , the polysilicon layer 109 is etched back so that the surface of the remaining polysilicon layer 109 is lower than the surface of the dielectric layer 105 .

[0052] The polysilicon layer may be etched back using a wet etching process or an isotropic plasma etching process.

[0053] The purpose of etching back the polysilicon layer 109 is to define the position of subsequently forming the first metal silicide layer and the through-hole contact metal layer located on the first metal silicide layer.

[0054] refer to Figure 3 and Figure 4 A first metal silicide layer 112 is formed on the surface of the polysilicon layer 109 (reference Figure 3 ) and the through hole contact metal layer 113 located on the first metal silicide layer 112 (reference Figure 4 ).

[0055] In one embodiment, the formation process of the first metal silicide layer 112 and the through-hole contact metal layer 113 is as follows: forming a first metal layer (not shown in the figure) on the surface of the dielectric layer 105 and in the channel through-hole on the polysilicon layer 109; annealing the first metal layer so that the first metal layer reacts with a portion of the polysilicon layer 109 on the storage structure to form a first metal silicide layer 112 on the surface of the polysilicon layer 109, wherein the surface of the first metal silicide layer 112 is lower than the top surface of the dielectric layer 105; removing the unreacted first metal layer, forming a through-hole contact metal layer 113 on the surface of the first metal silicide layer 112, wherein the surface of the through-hole contact metal layer 113 is flush with the top surface of the dielectric layer 105.

[0056] The material of the first metal layer is one or more of nickel, cobalt, tantalum and titanium. The first metal layer is formed by sputtering, and the thickness of the first metal layer is smaller than the radius of the channel through hole.

[0057] The annealing includes a first annealing and a second annealing performed at the same time, and the temperature of the second annealing is higher than the temperature of the first annealing. In one embodiment, the first annealing is an immersion annealing, the annealing temperature is 220-320 degrees Celsius, and the annealing time is 30-90 seconds, and the second annealing is a millisecond annealing, the annealing temperature is 700-950 degrees Celsius, and the annealing time is 0.25-20 milliseconds.

[0058] The unreacted first metal layer may be removed by a wet etching process.

[0059] The material of the first metal silicide layer 112 is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide. In the present application, the step of forming the first metal silicide layer 112 and the subsequent step of forming the second metal silicide are not performed in the same step, so that by adjusting the thickness of the first metal layer alone, the thickness of the formed first metal silicide layer 112 can be adjusted alone, so that the thickness of the first metal silicide layer will not be limited by the process of forming the second metal silicide layer, so that the thickness of the formed first metal silicide layer 112 meets the performance requirements. In one embodiment, the thickness of the first metal layer is 7nm-50nm, and the thickness of the first metal silicide layer 112 is 7nm-50nm.

[0060] The formation process of the through hole contact metal layer 113 is as follows: forming a metal layer on the dielectric layer 105 and the first metal silicide 112; planarizing and removing the metal layer above the surface of the dielectric layer 105, and forming the through hole contact metal layer 113 on the first metal silicide layer 112. The through hole contact metal layer 113 is subsequently used to connect with the bit line, and when the second metal silicide layer is subsequently formed, the second metal layer can be isolated from the first metal silicide layer 112 to prevent the thickness of the formed first metal silicide layer 112 from changing. The through hole contact metal layer 113 can also be used as an etching stop layer when a third through hole is subsequently formed in the hard mask layer.

[0061] The material of the through hole contact metal layer 113 may be tungsten.

[0062] refer to Figure 5 , the sacrificial layer is replaced by a control gate structure 123 .

[0063] In one embodiment, the control gate structure 123 is formed by: forming a hard mask layer 114 on the stacked structure 111; forming a gate groove 115 in the hard mask layer 114 and the stacked structure 111; removing the sacrificial layer along the gate groove 115; and forming the control gate structure 123 at the position where the sacrificial layer is removed.

[0064] The hard mask layer 114 may be a single layer or a multi-layer stacked structure. The material of the hard mask layer 114 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0065] The sacrificial layer is removed by wet etching. In one embodiment, after the bottommost sacrificial layer (bottom select gate sacrificial layer) in the stacked structure is removed, the corresponding position can form a bottom select gate (BSG) 122, and after the topmost sacrificial layer (top select gate sacrificial layer) in the stacked structure is removed, the corresponding position can form a top select gate (TSG) 124. The bottom select gate sacrificial layer and the top select gate sacrificial layer are removed simultaneously with other sacrificial layers, and the bottom select gate 122 and the top select gate 124 are formed simultaneously with the control gate structure 123.

[0066] For example, the control gate structure 123 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. In one embodiment, the gate dielectric layer may be a high-K dielectric layer and a metal gate located on the surface of the high-K dielectric layer, and the material of the metal gate may be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The material of the high-K dielectric layer may be HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO. In other embodiments, the control gate structure 123 may include a silicon oxide dielectric layer and a polysilicon gate located on the dielectric layer.

[0067] refer to Figure 6 In the gate isolation groove 115 (reference Figure 5 ) to form an array common source 116.

[0068] Before forming the array common source 116 , an isolation spacer is formed on the sidewall of the gate spacer 115 .

[0069] In this embodiment, the surface forming the array common source 116 is lower than the surface of the hard mask layer 114 , and the material of the array common source 116 is a polysilicon layer.

[0070] refer to Figure 7 , forming a patterned photoresist layer 130 on the hard mask layer 114; using the patterned photoresist layer 130 as a mask, etching the hard mask layer 114 and the dielectric layer 105, forming a first through hole 117 exposing a portion of the surface of the well region 110 on one side of the stacked structure 111 and a plurality of second through holes 118 exposing the surface of the corresponding step structure 11 in the hard mask layer 114 and the dielectric layer 105, and forming a third through hole 119 exposing a portion of the surface of the through hole contacting the metal layer 113 in the hard mask layer 114, wherein the size of the third through hole 119 is smaller than the size of the through hole contacting the metal layer 113.

[0071] A first contact plug connected to the well region 110 is subsequently formed in the first through hole 117 , a second contact plug connected to the step structure 11 is subsequently formed in the second through hole 118 , and a bit line connected to the through hole contact metal layer 113 is subsequently formed in the third through hole 119 .

[0072] The size of the third through hole 119 is smaller than the size of the through hole contacting the metal layer 113 (or the channel through hole), and the size of the bit line formed subsequently is smaller than the size of the through hole contacting the metal layer 113 (or the channel through hole), so that the size of the formed bit line can be smaller. In one embodiment, the size of the third through hole 119 can be 1 / 4-2 / 3 of the size of the through hole contacting the metal layer 113 (or the channel through hole).

[0073] The hard mask layer 114 and the dielectric layer 105 may be etched using an anisotropic dry etching process, such as an anisotropic plasma etching process.

[0074] In the present application, since the first metal silicide layer 112 is formed first and then the second metal silicide layer is formed, not only the thickness of the first metal silicide layer 112 can be controlled independently to meet the performance requirements, but also no mask layer needs to be formed when forming the first metal silicide layer 112 (the position of the first metal silicide layer 112 is directly defined by the channel through hole), and only one mask process (hard mask layer) is required to form the second metal silicide layer and the first contact plug, the second contact plug and the bit line, and a smaller bit line can be formed through one mask process, thereby saving costs.

[0075] refer to Figure 8 , a second metal silicide layer 120 is formed on the surface of the well region at the bottom of the first through hole 117 .

[0076] In one embodiment, the formation process of the second metal silicide layer 120 includes: forming a second metal layer in the first through hole 117 and on the surface of the hard mask layer 105; performing annealing to allow the second metal layer to react with silicon in the well region to form a second metal silicide layer 120 on the surface of the well region; and removing the unreacted second metal layer.

[0077] The material of the second metal layer is one or more of nickel, cobalt, tantalum and titanium. The second metal layer is formed by sputtering.

[0078] The annealing includes a first annealing and a second annealing performed at the same time, and the temperature of the second annealing is higher than the temperature of the first annealing. In one embodiment, the first annealing is an immersion annealing, the annealing temperature is 220-320 degrees Celsius, and the annealing time is 30-90 seconds, and the second annealing is a millisecond annealing, the annealing temperature is 700-950 degrees Celsius, and the annealing time is 0.25-20 milliseconds.

[0079] The unreacted second metal layer may be removed by a wet etching process.

[0080] The material of the second metal silicide layer 112 is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide, or a combination thereof.

[0081] refer to Fig. 9 A first contact plug 125 connected to the second metal silicide layer 120 is formed in the first through hole, a second contact plug 126 connected to the surface of the corresponding step structure 11 is formed in the second through hole, and a bit line 127 connected to the through hole contact metal layer 113 is formed in the third through hole.

[0082] The first contact plug 125, the second contact plug 126 and the bit line 127 are formed in the same step. Before forming the first contact plug 125, the second contact plug 126 and the bit line 127, the patterned photoresist layer 130 is removed to expose the remaining gate partition grooves on the array common source 116. While forming the first contact plug 125, the second contact plug 126 and the bit line 127, the fourth contact plug 128 is formed in the remaining gate partition grooves on the array common source 116.

[0083] In one embodiment, the formation process of the first contact plug 125, the second contact plug 126, the bit line 127 and the fourth contact plug 128 is as follows: forming a metal layer that fills the first through hole, the second through hole, the third through hole and the remaining gate partition groove on the array common source 116 and covers the surface of the hard mask layer 114, and the material of the metal layer can be tungsten; a planarization process (such as a chemical mechanical polishing process) is used to remove the metal layer above the surface of the hard mask layer 114, and the first contact plug 125 is formed in the first through hole, the second contact plug 126 is formed in the second through hole, the bit line 127 is formed in the third through hole, and the fourth contact plug 128 is formed in the remaining gate partition groove on the array common source 116.

[0084] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a 3D NAND memory, characterized in that: include: Providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate, a stacked structure located on the semiconductor substrate, and a dielectric layer covering the semiconductor substrate and the stacked structure; forming a plurality of channel through holes penetrating the stack structure in the dielectric layer and the stack structure; forming a channel structure in the channel through hole; forming a polysilicon layer and a first metal silicide layer on the channel structure; forming a first through hole in the dielectric layer to expose the semiconductor substrate; A second metal silicide layer is formed at the bottom of the first through hole, and the step of forming the first metal silicide layer and the step of forming the second metal silicide layer are different steps.

2. The method for forming a 3D NAND memory according to claim 1, wherein: The step of forming the first metal silicide layer is performed before the step of forming the second metal silicide layer.

3. The method for forming a 3D NAND memory according to claim 1, wherein: The formation process of the first metal silicide layer is as follows: forming a first metal layer in the channel through hole on the polysilicon layer; annealing the first metal layer so that the first metal layer reacts with a portion of the polysilicon layer on the channel structure to form a first metal silicide layer on the surface of the polysilicon layer.

4. The method for forming a 3D NAND memory according to claim 3, wherein: Also includes: removing an unreacted portion of the first metal layer to expose the first metal silicide layer; forming a through-hole contact metal layer on the surface of the first metal silicide layer; The surface of the first metal silicide layer is lower than the top surface of the dielectric layer; The surface of the through hole contacting the metal layer is flush with the top surface of the dielectric layer.

5. The method for forming a 3D NAND memory according to claim 1, wherein: The material of the first metal silicide layer is one or a combination of nickel silicide, cobalt silicide, tantalum silicide and titanium silicide; The material of the second metal silicide layer is one of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide, or a combination thereof.

6. The method for forming a 3D NAND memory according to claim 1 or 2, wherein: The stacked structure includes sacrificial layers and isolation layers that are alternately stacked; The method also includes: forming a gate groove; removing the sacrificial layer along the gate groove; and forming a control gate structure at the position where the sacrificial layer is removed.

7. The method for forming a 3D NAND memory according to claim 6, wherein: The method further comprises: after forming the control gate structure, forming an array common source in the gate partition groove.

8. The method for forming a 3D NAND memory according to claim 4, wherein: Also includes: A bit line connected to the through-hole contact metal layer is formed, wherein the size of the bit line is smaller than the size of the through-hole contact metal layer.

9. The method for forming a 3D NAND memory according to claim 1, wherein: The end of the stack structure has a step structure; while forming the first through hole in the dielectric layer, it also includes: forming a plurality of second through holes in the dielectric layer to expose the corresponding step structure surfaces.

10. The method for forming a 3D NAND memory according to claim 9, wherein: Also includes: A first contact plug connected to the second metal silicide layer is formed in the first through hole, and a second contact plug connected to the corresponding stepped structure surface is formed in the second through hole.

11. The method for forming a 3D NAND memory according to claim 10, wherein: Also includes: forming a silicon oxide layer on the stacked structure; The formation process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line includes: etching the silicon oxide layer and the dielectric layer, forming a first through hole exposing the semiconductor substrate on one side of the stacking structure and a plurality of second through holes exposing the corresponding step structure surface in the silicon oxide layer and the dielectric layer, and forming a third through hole exposing a portion of the surface of the through hole contacting the metal layer in the silicon oxide layer, wherein the size of the third through hole is smaller than the size of the channel through hole; forming a second metal layer in the first through hole; performing annealing to react the second metal layer with silicon in the semiconductor substrate to form a second metal silicide layer on the surface of the semiconductor substrate; removing the unreacted second metal layer; filling the first through hole, the second through hole and the third through hole with a metal layer, forming a first contact plug connected to the second metal silicide layer in the first through hole, forming a second contact plug connected to the corresponding step structure surface in the second through hole, and forming a bit line connected to the through hole contacting the metal layer in the third through hole.

12. The method for forming a 3D NAND memory according to claim 7, wherein: The channel structure includes a charge storage functional layer located on the side wall surface of the channel through hole and a channel layer located on the side wall surface of the charge storage layer; the charge storage functional layer includes a blocking layer located on the side wall surface of the channel through hole, a charge capture layer located on the side wall surface of the blocking layer, and a tunneling layer located on the side wall surface of the charge capture layer.

13. The method for forming a 3D NAND memory according to claim 12, wherein: The forming of a polysilicon layer on the channel structure comprises: Before forming the first metal silicide layer, forming an initial polysilicon layer on the channel layer; Etching back the initial polysilicon layer so that the surface of the polysilicon layer obtained by etching back is lower than the top surface of the dielectric layer; In the step of etching back the initial polysilicon layer, an etching rate of the initial polysilicon layer by the etchant is different from an etching rate of the tunnel layer.

14. The method for forming a 3D NAND memory according to claim 13, wherein: In the step of etching back the initial polysilicon layer, the etching rate of the etchant on the initial polysilicon is greater than the etching rate on the dielectric layer.

15. The method for forming a 3D NAND memory according to claim 13, wherein: In the step of etching back the polysilicon layer, the etching rate of the etchant on the initial polysilicon is greater than the etching rate on the tunneling layer.

16. The method for forming a 3D NAND memory according to claim 13, wherein: The step of etching back the initial polysilicon layer is performed before forming the gate spacer.

17. A 3D NAND memory, characterized in that: include: A semiconductor substrate, a stacked structure located on the semiconductor substrate, and a dielectric layer covering the semiconductor substrate and the stacked structure; A channel hole structure penetrating the dielectric layer and the stacked structure, the channel hole structure comprising a channel structure, a polysilicon layer, a first metal silicide layer and a through-hole contact metal layer located on the first metal silicide layer; A second metal silicide layer and a first contact plug formed in the dielectric layer, wherein the second metal silicide layer is located on the semiconductor substrate, and the first contact plug is located on the second metal silicide layer; a silicon oxide layer located on the dielectric layer; a bit line formed in the silicon oxide layer, the bit line being connected to the through-hole contact metal layer; Wherein, the diameter of the through hole contact metal layer is greater than the diameter of the bit line.

18. The 3D NAND memory according to claim 17, wherein: The end of the stack structure has a step structure; and further comprises: a second contact plug formed in the dielectric layer, the second contact plug being connected to a corresponding step structure surface; An array common source and a fourth contact plug are formed in a gate isolation groove formed in the stacked structure.

19. The 3D NAND memory according to claim 18, wherein: The diameter of the through-hole contact metal layer is equal to the diameter of the polysilicon layer; the diameter of the second contact plug is larger than the diameter of the bit line; and the diameter of the first contact plug is larger than the diameter of the bit line.

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