Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, wherein the substrate has an initial first conductive layer; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer, wherein the first opening exposes a portion of the surface of the initial first conductive layer; forming an initial second opening in the initial first conductive layer at the bottom of the first opening; performing an amorphization treatment on the initial first conductive layer at the bottom surface and the sidewall surface of the initial second opening to form a first conductive layer and a modified region located in the first conductive layer, wherein the material of the modified region is the material of the amorphous initial first conductive layer; performing a first annealing treatment on the modified region to crystallize the modified region into a second conductive layer, and forming a second opening in the second conductive layer at the bottom of the first opening, wherein the projected area of ​​the first opening on the substrate is smaller than the projected area of ​​the second opening on the substrate. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active areas, between transistors, or between metal lines of different layers, and complete the transmission and control of signals. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of semiconductor devices and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of each semiconductor device, a multi-layer interconnection structure is usually required.

[0003] Generally, in the back-end interconnection process of the semiconductor device manufacturing process, the first metal layer (M1) needs to form an electrical connection with the active device structure (including the source and drain regions and the gate structure region) of the lower layer. Therefore, before forming the first metal layer, it is usually necessary to pre-form a local interconnection structure (Local Interconnect) of the semiconductor device. The local interconnection structure includes: a zeroth metal layer (M0) electrically connected to the source and drain regions of the lower layer, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the semiconductor structure with the local interconnection structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has an initial first conductive layer; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer, wherein the first opening exposes a portion of the surface of the initial first conductive layer; forming an initial second opening in the initial first conductive layer at the bottom of the first opening; performing an amorphization treatment on the initial first conductive layer at the bottom surface and the side wall surface of the initial second opening to form a first conductive layer and a modified region located in the first conductive layer, wherein the material of the modified region is the material of the amorphous initial first conductive layer; performing a first annealing treatment on the modified region to crystallize the modified region into a second conductive layer, and forming a second opening in the second conductive layer at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is within the projection range of the second opening on the substrate.

[0007] Optionally, the method of amorphizing the bottom surface and the sidewall surface of the initial second opening includes: oxidizing a portion of the initial first conductive layer to form an oxide layer; and reducing the oxide layer to form a modified region.

[0008] Optionally, the oxidation treatment process includes a gas oxidation process, and the gas of the gas oxidation process includes a gas containing oxygen or ozone; the parameter range of the oxidation process is: gas flow rate is 30sccm~500sccm, temperature is 100 degrees Celsius~500 degrees Celsius, time is 10 seconds~500 seconds, and power is 0 watts~500 watts.

[0009] Optionally, the reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a hydrogen-containing gas; the parameter range of the reduction process is: gas flow rate is 10sccm~5000sccm, temperature is 100 degrees Celsius~500 degrees Celsius, and time is 10 seconds~500 seconds.

[0010] Optionally, the method of performing amorphization treatment on the bottom surface and the sidewall surface of the initial second opening includes: performing nitridation treatment on a portion of the initial first conductive layer to form a nitride layer; and performing reduction treatment on the nitride layer to form a modified area.

[0011] Optionally, the method of performing amorphization treatment on the bottom surface and the side wall surface of the initial second opening includes: performing plasma gas bombardment treatment on the bottom surface and the side wall surface of the initial second opening to form the modified area.

[0012] Optionally, the second opening is larger than the first opening in a size range of 2 nanometers to 5 nanometers.

[0013] Optionally, the thickness of the modified zone ranges from 30 angstroms to 50 angstroms.

[0014] Optionally, process parameters of the first annealing treatment include: a temperature of 200 degrees Celsius to 500 degrees Celsius, and a time of 50 seconds to 500 seconds.

[0015] Optionally, the method for forming the first opening and the initial second opening includes: forming a first mask layer on the first dielectric layer, the first mask layer exposing a portion of the surface of the first dielectric layer on the initial first conductive layer; etching the first dielectric layer using the first mask layer as a mask until the surface of the initial first conductive layer is exposed to form the first opening; etching the initial first conductive layer exposed by the first opening to form a transitional second opening; and laterally etching the initial first conductive layer exposed by the transitional second opening to form the initial second opening.

[0016] Optionally, the process of etching the first dielectric layer to form the first opening includes an anisotropic dry etching process; and the process of etching the initial first conductive layer to form the transitional second opening includes an anisotropic dry etching process.

[0017] Optionally, the process of laterally etching the initial first conductive layer exposed by the transitional second opening includes an isotropic wet etching process.

[0018] Optionally, the substrate also includes: a base; a gate structure located on the base; source and drain doped regions located in the base on both sides of the gate structure; a second dielectric layer located on the base, the second dielectric layer being located on the sidewalls of the gate structure; the initial first conductive layer being located in the second dielectric layer, and the initial first conductive layer being located on the source and drain doped regions.

[0019] Optionally, the substrate further includes: a fin structure located on the base; the gate structure spans the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

[0020] Optionally, the method for forming the initial first conductive layer includes: forming a second mask layer on the second dielectric layer, the second mask layer exposing a portion of the surface of the second dielectric layer on the source and drain doping regions; etching the second dielectric layer using the second mask layer as a mask until the surface of the source and drain doping regions is exposed, thereby forming a groove in the second dielectric layer; forming a transitional first conductive layer in the groove; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer.

[0021] Optionally, after forming the second opening, the method further includes: forming a third conductive layer in the first opening and in the second opening.

[0022] Optionally, the method for forming the third conductive layer includes: forming an initial third conductive layer in the first opening and the second opening; forming a stop layer on the initial third conductive layer; forming a buffer layer on the stop layer; and planarizing the buffer layer, the stop layer and the initial third conductive layer to form a third conductive layer.

[0023] Optionally, the buffer layer and the initial third conductive layer are made of the same material.

[0024] Optionally, the material of the buffer layer and the initial third conductive layer includes metal, and the metal includes tungsten.

[0025] Optionally, the material of the stop layer includes titanium nitride.

[0026] Optionally, the process of forming the initial third conductive layer in the first opening and in the second opening includes a selective deposition process.

[0027] Optionally, process parameters for forming the initial third conductive layer include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0028] Optionally, the process of planarizing the buffer layer, the stop layer and the initial third conductive layer includes a chemical mechanical polishing process, and a polishing liquid of the chemical mechanical polishing process is an acidic solution.

[0029] Optionally, the material of the first conductive layer includes metal, and the metal includes crystalline cobalt.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] The method for forming a semiconductor structure in the technical solution of the present invention forms a first conductive layer and a modified area located in the first conductive layer by amorphizing the initial first conductive layer on the bottom surface and side wall surface of the initial second opening, wherein the material of the modified area is the material of the amorphous initial first conductive layer, and then the modified area is subjected to a first annealing treatment to crystallize the modified area into a second conductive layer, wherein the material of the second conductive layer is crystalline. The amorphous material is transformed into a crystalline state after annealing treatment, and the structure of the crystalline material becomes dense and the volume becomes smaller. The first annealing treatment causes the modified area to transform from an amorphous state to a crystalline state. When the amorphous material is transformed into a crystalline state, the molecules of the amorphous material move toward the direction of the crystalline material and are arranged in an orderly manner. Therefore, the thickness of the modified area is reduced. Therefore, the projection area of ​​the second opening formed on the substrate is larger than the projection area of ​​the first opening on the substrate. When the third conductive layer is subsequently formed in the first opening and the second opening, the third conductive layer located in the second opening can protect the second conductive layer and the first conductive layer, and prevent the second conductive layer and the first conductive layer from being damaged during the formation of the third conductive layer, thereby improving the performance of the semiconductor structure.

[0032] Furthermore, when the bottom surface and side wall surface of the initial second opening are subjected to amorphization treatment, a portion of the initial first conductive layer is first subjected to oxidation treatment to form an oxide layer, and then the oxide layer is subjected to reduction treatment to form a modified area. Therefore, after oxidation and reduction, a portion of the material of the initial first conductive layer becomes an amorphous modified area, and then after annealing treatment, the projected area of ​​the formed second opening on the substrate is larger than the projected area of ​​the first opening on the substrate.

[0033] Furthermore, the modified area can be transformed into a second conductive layer through the first annealing treatment, so that the resistance of the second conductive layer is reduced and the conductive effect of the second conductive layer can be improved.

[0034] Furthermore, the process of forming an initial third conductive layer in the first opening and the second opening includes a selective deposition process, which can form a densely structured initial third conductive layer in the first opening and the second opening with a larger aspect ratio, so that the subsequently formed third conductive layer has a smaller resistance and a better conductive effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0036] Figures 4 to 10 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the manufacturing process of the semiconductor structure with the local interconnection structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0038] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0039] Please refer to Figure 1 , providing a substrate 100; forming a gate structure 101 on the substrate 100; forming source-drain doped regions 102 in the substrate on both sides of the gate structure 101; forming a first dielectric layer 103 on the substrate; forming a conductive layer 104 in the dielectric layer 103, wherein the conductive layer 104 is electrically connected to the source-drain doped regions 102; forming a second dielectric layer 105 on the first dielectric layer 103 and the conductive layer 104; forming a first opening 106 in the second dielectric layer 105, wherein the first opening 106 exposes the surface of the conductive layer 104; and forming a second opening 110 in the first conductive layer at the bottom of the first opening 106.

[0040] Please refer to Figure 2 , forming an initial connection layer 107 in the first opening 106 and the second opening 110 ; forming a seed layer (not shown) on the surface of the initial connection layer 107 and the surface of the second dielectric layer 105 ; and forming a connection material layer 108 on the seed layer.

[0041] Please refer to Figure 3 , planarizing the connection material layer 108 , the seed layer, the initial connection layer 107 and a portion of the second dielectric layer 105 to form the connection layer 109 .

[0042] During the formation of the semiconductor structure, the material of the initial connection layer 107 includes metal tungsten, the material of the conductive layer 104 includes metal cobalt, and the process of forming the initial connection layer 107 in the opening 106 includes a selective deposition process. The material growth of the initial connection layer 107 formed by the selective deposition process has a certain directionality, so the initial connection layer 107 is not completely tightly combined with the second dielectric layer 105, and there is a gap between the initial connection layer 107 and the second dielectric layer 105. In addition, since the material growth of the initial connection layer 107 formed by the selective deposition process has a certain directionality, the top surface of the initial connection layer 107 formed is often higher than the surface of the second dielectric layer 105, and the initial connection layer 107 needs to be planarized to form a connection layer 109. Before planarizing the initial connection layer 107, a seed layer and a connection material layer 108 located on the seed layer are formed on the surface of the initial connection layer 107 and the surface of the second dielectric layer 105, so that the starting plane of the planarization process is relatively flat, so as to control the stop position of the planarization later.

[0043] The planarization process generally adopts a chemical mechanical polishing process, and the polishing liquid of the chemical mechanical polishing process is an acidic solution. Since there is a gap between the initial connection layer 107 and the second dielectric layer 105, the polishing liquid of the chemical mechanical polishing process will enter the conductive layer 104 along the gap between the initial connection layer 107 and the second dielectric layer 105, causing damage to the lattice of the conductive layer 104, thereby increasing the resistance of the conductive layer 104, thereby affecting the performance of the semiconductor structure.

[0044] In order to reduce the influence of the polishing liquid on the conductive layer 104, in this embodiment, an initial second opening (not shown) is formed in the first conductive layer 104 at the bottom of the first opening 106, and then the bottom of the initial second opening is laterally etched to form a second opening 110, so that the size of the second opening 110 in the conductive layer 104 is larger than the size of the first opening 106. Therefore, when the polishing liquid flows into the conductive layer 104 along the gap between the initial connection layer 107 and the second dielectric layer 105, the initial connection layer 107 in the second opening 110 will block the polishing liquid, thereby reducing the damage of the polishing liquid to the conductive layer 104.

[0045] However, since the conductive layer 104 is transformed into a crystalline state after annealing, the crystalline conductive layer 104 is denser and has grain boundaries. When the wet etching process is used to laterally etch the bottom of the initial second opening, the etching direction of the etching solution in the wet etching process is easily guided by the grain boundaries and deviates from the preset direction, making the etching process difficult to control, and thus making it difficult to make the side walls of all the second openings 110 formed to be concave into the first dielectric layer 104 relative to the first opening 106 (e.g., Figure 3 Therefore, the subsequent planarization process for forming the connection layer 109 will still damage part of the conductive layer 104, affecting the performance of the formed semiconductor structure.

[0046] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by amorphizing the initial first conductive layer on the bottom surface and the sidewall surface of the initial second opening, forming a first conductive layer and a modified area located in the first conductive layer, the material of the modified area is the material of the amorphous initial first conductive layer, and then performing a first annealing treatment on the modified area to crystallize the modified area into a second conductive layer, the material of the second conductive layer is crystalline. The amorphous material is transformed into a crystalline state after annealing, and the structure of the crystalline material becomes dense and the volume becomes smaller. The first annealing treatment causes the modified area to transform from an amorphous state to a crystalline state. When the amorphous material is transformed into a crystalline state, the molecules of the amorphous material move toward the direction of the crystalline material to form an orderly arrangement state, so the thickness of the modified layer is reduced, so that the projection area of ​​the second opening formed on the substrate is larger than the projection area of ​​the first opening on the substrate, and when the third conductive layer is subsequently formed in the first opening and the second opening, the third conductive layer located in the second opening can protect the first conductive layer from being damaged in the process of forming the second conductive layer, thereby improving the performance of the semiconductor structure.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 4 to 10 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0049] Please refer to Figure 4 , providing a substrate having an initial first conductive layer 204 therein.

[0050] The substrate includes: a base 200; a gate structure 201 located on the base 200; source-drain doped regions 202 located in the base 200 on both sides of the gate structure 201; a second dielectric layer 203 located on the base 200, the second dielectric layer 203 being located on the sidewalls of the gate structure 201; the initial first conductive layer 204 being located in the second dielectric layer 203, and the initial first conductive layer 204 being located on the source-drain doped regions 202.

[0051] In this embodiment, the material of the substrate 200 is silicon.

[0052] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0053] The source-drain doping region 202 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

[0054] The material of the second dielectric layer 203 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second dielectric layer 203 includes silicon oxide.

[0055] The gate structure 201 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0056] In this embodiment, the material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate layer includes polysilicon.

[0057] In other embodiments, the gate structure further includes a work function layer, and the work function layer is located between the gate dielectric layer and the gate layer.

[0058] In other embodiments, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0059] The initial first conductive layer 204 is used for subsequently forming a first conductive layer.

[0060] The material of the initial first conductive layer 204 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, crystalline cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0061] In this embodiment, the material of the initial first conductive layer 204 includes crystalline cobalt. The crystalline cobalt has a relatively low resistivity, which is beneficial to improving the conductive efficiency of the subsequent first conductive layer and improving the performance of the semiconductor structure.

[0062] The method for forming the initial first conductive layer 204 includes: forming a second mask layer (not shown) on the second dielectric layer 203; etching the second dielectric layer 203 using the second mask layer as a mask until the surface of the source-drain doped region 202 is exposed, and forming a groove (not shown) in the second dielectric layer 203; forming a transitional first conductive layer (not shown) in the groove; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer 204.

[0063] The method for forming a transitional first conductive layer in a groove includes: forming an adhesion layer (not shown) on the bottom surface and sidewall surface of the groove and the second dielectric layer 203; forming a conductive material layer (not shown) on the adhesion layer; and planarizing the conductive material layer and the adhesion layer until the surface of the second dielectric layer 203 is exposed to form the transitional first conductive layer.

[0064] The adhesion layer is used to form a conductive material layer in the groove and on the second dielectric layer 203 .

[0065] The material of the adhesion layer includes metal or metal nitride, including metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, crystalline cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0066] In this embodiment, the material of the adhesion layer includes titanium nitride.

[0067] The process of forming the conductive material layer includes an electroplating process, a chemical plating process, a physical vapor deposition process, an atomic layer deposition process or a selective deposition process.

[0068] In this embodiment, the process of forming the conductive material layer includes an electroplating process.

[0069] The second annealing process is used to crystallize the amorphous transitional first conductive layer into a crystalline initial first conductive layer 204 .

[0070] In this embodiment, the substrate is a planar substrate.

[0071] In other embodiments, the substrate further includes: a fin structure located on the base; the gate structure spans across the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

[0072] Please refer to Figure 5 , a first dielectric layer 205 is formed on the substrate.

[0073] The material of the first dielectric layer 205 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first dielectric layer 205 includes silicon oxide.

[0074] Please continue to refer to Figure 5 , a first opening 206 is formed in the first dielectric layer 205 , wherein the first opening 206 exposes a portion of the surface of the initial first conductive layer 204 .

[0075] The method for forming the first opening 206 includes: forming a first mask layer (not shown) on the first dielectric layer 205, the first mask layer exposing a portion of the surface of the first dielectric layer 205 on the initial first conductive layer 204; etching the first dielectric layer 205 using the first mask layer as a mask until the surface of the initial first conductive layer 204 is exposed to form the first opening 206.

[0076] The process of etching the first dielectric layer 205 to form the first opening 206 includes an anisotropic dry etching process or a wet etching process.

[0077] In this embodiment, the process of etching the first dielectric layer 205 to form the first opening 206 includes an anisotropic dry etching process. The anisotropic dry etching process has high directional selectivity and can form the first opening 206 with smooth sidewalls and good morphology.

[0078] Please refer to Figure 6 An initial second opening 207 is formed in the initial first conductive layer 204 at the bottom of the first opening 206 .

[0079] The method for forming the initial second opening 207 includes: etching the initial first conductive layer 204 exposed by the first opening 206 to form a transitional second opening (not shown); and laterally etching the initial first conductive layer 204 exposed by the transitional second opening to form the initial second opening 207 .

[0080] By performing lateral etching on the initial first conductive layer 204 exposed by the transitional second opening, the side walls of the initial second opening 207 can be recessed into the second dielectric layer 203 relative to the side walls of the first opening 206. Thus, when a portion of the initial first conductive layer 204 is subsequently amorphized to form a modified area, the process conditions of the amorphization treatment can be weakened, thereby improving production efficiency.

[0081] The process of etching the initial first conductive layer 204 to form the transitional second opening includes an anisotropic dry etching process, and the anisotropic dry etching process is convenient for controlling the depth of the transitional second opening.

[0082] The etching gas of the anisotropic dry etching process includes a mixed gas of carbon tetrafluoride, monofluoromethane and oxygen.

[0083] The process of laterally etching the initial first conductive layer 204 exposed by the transitional second opening includes an isotropic wet etching process, and the isotropic wet etching process can have a high etching selectivity to the first dielectric layer 205 and the initial first conductive layer 204, so that the side wall of the initial second opening 207 is recessed into the second dielectric layer 203 relative to the side wall of the first opening 206.

[0084] In other embodiments, the initial first conductive layer exposed by the transitional second opening may not be laterally etched, and the transitional second opening is the initial second opening.

[0085] Please refer to Figure 7 The initial first conductive layer 204 on the bottom surface and the side wall surface of the initial second opening 207 is amorphized to form a first conductive layer 208 and a modified area 209 located in the first conductive layer 208, wherein the material of the modified area 209 is the material of the amorphous initial first conductive layer 204.

[0086] In this embodiment, the method of amorphizing the bottom surface and the sidewall surface of the initial second opening 207 includes: oxidizing a portion of the initial first conductive layer 204 to form an oxide layer (not shown); and reducing the oxide layer to form a modified region 209 .

[0087] The oxidation treatment process includes a gas oxidation process, and the gas of the gas oxidation process includes a gas containing oxygen or ozone.

[0088] The parameter ranges of the oxidation process are: gas flow rate of 30 sccm to 500 sccm, temperature of 100 degrees Celsius to 500 degrees Celsius, time of 10 seconds to 500 seconds, and power of 0 watts to 500 watts.

[0089] The reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

[0090] The parameter range of the reduction process is: gas flow rate is 10 sccm to 5000 sccm, temperature is 100 degrees Celsius to 500 degrees Celsius, and time is 10 seconds to 500 seconds.

[0091] The oxidation process and the reduction process under the process conditions make the thickness of the formed modified area thicker, and after the subsequent first annealing treatment, the size of the second opening can be larger.

[0092] In another embodiment, the method of amorphizing the bottom surface and the sidewall surface of the initial second opening includes: nitriding a portion of the initial first conductive layer to form a nitride layer; and reducing the nitride layer to form a modified region.

[0093] In another embodiment, the method of performing amorphization treatment on the bottom surface and the side wall surface of the initial second opening includes: performing plasma gas bombardment treatment on the bottom surface and the side wall surface of the initial second opening to form the modified area.

[0094] First, a part of the initial first conductive layer 204 is oxidized to form an oxide layer, and then the oxide layer is reduced to form a modified area 209. Therefore, after oxidation and reduction, the material of part of the initial first conductive layer 204 becomes an amorphous modified area 209. The material of the modified area 209 is the material of the amorphous initial first conductive layer. Therefore, when the modified area 209 is subsequently subjected to a first annealing treatment, the modified area 209 can be crystallized into a second conductive layer. The material of the second conductive layer is crystalline. The amorphous material is transformed into a crystalline state after annealing. The structure of the crystalline material becomes dense and the volume becomes smaller. The first annealing treatment causes the modified area 209 to transform from an amorphous state to a crystalline state. When the amorphous material transforms into a crystalline state, the molecules of the amorphous material move toward the direction of the crystalline material to form an orderly arrangement state. Therefore, the thickness of the modified area 209 is reduced, so that the projected area of ​​the second opening formed subsequently on the substrate is larger than the projected area of ​​the first opening on the substrate.

[0095] Please refer to Figure 8 , a first annealing treatment is performed on the modified area 209 to crystallize the modified area 209 into a second conductive layer 210, and a second opening 211 is formed in the second conductive layer 210 at the bottom of the first opening 206, the projection area of ​​the first opening 206 on the substrate is smaller than the projection area of ​​the second opening 211 on the substrate, and the projection of the first opening 206 on the substrate is within the projection range of the second opening 211 on the substrate.

[0096] The second opening 211 is larger than the first opening 206 by 2 nanometers to 5 nanometers. Therefore, when the third conductive layer is subsequently formed in the second opening 211, the third conductive layer in the second opening 211 can protect the second conductive layer 210 and the first conductive layer 208, and prevent the second conductive layer 210 and the first conductive layer 208 from being damaged during the process of forming the third conductive layer.

[0097] In this embodiment, the thickness of the modified region 209 is in the range of 30 angstroms to 50 angstroms.

[0098] The process parameters of the first annealing treatment include: a temperature of 200 degrees Celsius to 500 degrees Celsius and a time of 50 seconds to 500 seconds.

[0099] The modified area 209 can be transformed into the second conductive layer 210 through the first annealing process, so that the resistance of the second conductive layer 210 is reduced and the conductive effect of the second conductive layer 210 is improved.

[0100] Since the material of the modified zone 209 is the material of the initial first conductive layer 204 which is in an amorphous state, the amorphous material is transformed into a crystalline state after annealing treatment, and the structure of the crystalline material becomes dense and the volume becomes smaller. The first annealing treatment causes the modified zone 209 to transform from an amorphous state to a crystalline state. When the amorphous material transforms into a crystalline state, the molecules of the amorphous material move toward the crystalline material and are arranged in an orderly manner. Therefore, the thickness of the modified zone 209 is reduced, and the projection area of ​​the second opening 211 formed on the substrate is larger than the projection area of ​​the first opening 206 on the substrate. When the third conductive layer is subsequently formed in the first opening 211 and the second opening 206, the third conductive layer located in the second opening 211 can protect the second conductive layer 210 and the first conductive layer 208, and prevent the second conductive layer 210 and the first conductive layer 208 from being damaged during the formation of the third conductive layer, thereby improving the performance of the semiconductor structure.

[0101] Next, after forming the second opening 211, the method further includes: forming a third conductive layer 215 in the first opening 206 and the second opening 211. The formation process of the third conductive layer 215 can be found in Fig. 9 and Fig.10 .

[0102] Please refer to Fig. 9 , an initial third conductive layer 212 is formed in the first opening 206 and the second opening 211 ; a stop layer 213 is formed on the initial third conductive layer 212 and the first dielectric layer 205 ; and a buffer layer 214 is formed on the stop layer 213 .

[0103] The buffer layer 214 and the initial third conductive layer 212 are made of the same material.

[0104] The buffer layer 214 and the initial third conductive layer 212 are made of metal, and the metal includes tungsten.

[0105] The material of the stop layer 213 includes titanium nitride. The stop layer 213 is used to form a buffer layer 214 on the second dielectric layer 207 and also serves as an etching stop layer for subsequent planarization of the buffer layer 214 , the stop layer 213 and the initial third conductive layer 212 .

[0106] The process of forming the initial third conductive layer 212 in the first opening 206 and the second opening 211 includes a selective deposition process, which can form a densely structured initial third conductive layer 212 in the opening with a large aspect ratio, so that the subsequently formed third conductive layer has a smaller resistance and a better conductive effect.

[0107] The process parameters for forming the initial third conductive layer include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0108] Please refer to Fig.10 , planarizing the buffer layer 214 , the stop layer 213 and the initial third conductive layer 212 to form a third conductive layer 215 .

[0109] The process of planarizing the buffer layer 214 , the stop layer 213 and the initial third conductive layer 212 includes a chemical mechanical polishing process, and the polishing liquid of the chemical mechanical polishing process is an acidic solution.

[0110] Since the projection area of ​​the first opening 206 on the substrate is smaller than the projection area of ​​the second opening 211 on the substrate, during the process of forming the third conductive layer 215 in the first opening 206 and the second opening 211, the third conductive layer 215 located in the second opening 211 can protect the second conductive layer 210 and the first conductive layer 208, thereby preventing the polishing liquid of the chemical mechanical polishing process from flowing into the second conductive layer 210 and the first conductive layer 208 along the gap between the initial third conductive layer 212 and the first dielectric layer 205 during the process of planarizing the buffer layer 214, the stop layer 213 and the initial third conductive layer 212, thereby damaging the second conductive layer 210 and the first conductive layer 208, thereby improving the performance of the semiconductor structure.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having an initial first conductive layer therein; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer, wherein the first opening exposes a portion of the surface of the initial first conductive layer; forming an initial second opening in the initial first conductive layer at a bottom of the first opening; Performing an amorphization treatment on the initial first conductive layer on the bottom surface and the sidewall surface of the initial second opening to form a first conductive layer and a modified region located in the first conductive layer, wherein the material of the modified region is the material of the amorphous initial first conductive layer; The modified area is subjected to a first annealing treatment to crystallize the modified area into a second conductive layer, and a second opening is formed in the second conductive layer at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is within the projection range of the second opening on the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method of amorphizing the bottom surface and the sidewall surface of the initial second opening comprises: oxidizing a portion of the initial first conductive layer to form an oxide layer; and reducing the oxide layer to form a modified region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The oxidation treatment process includes a gas oxidation process, and the gas of the gas oxidation process includes a gas containing oxygen or ozone; the parameter range of the oxidation process is: gas flow rate is 30sccm~500sccm, temperature is 100 degrees Celsius~500 degrees Celsius, time is 10 seconds~500 seconds, and power is 0 watts~500 watts.

4. The method for forming a semiconductor structure according to claim 2, wherein: The reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen; the parameter range of the reduction process is: a gas flow rate of 10sccm to 5000sccm, a temperature of 100 degrees Celsius to 500 degrees Celsius, and a time of 10 seconds to 500 seconds.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of amorphizing the bottom surface and the sidewall surface of the initial second opening comprises: nitriding a portion of the initial first conductive layer to form a nitride layer; and reducing the nitride layer to form a modified region.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method of performing amorphization treatment on the bottom surface and the side wall surface of the initial second opening includes: performing plasma gas bombardment treatment on the bottom surface and the side wall surface of the initial second opening to form the modified area.

7. The method for forming a semiconductor structure according to claim 1, wherein: The second opening is larger than the first opening in a size range of 2 nanometers to 5 nanometers.

8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the modified area ranges from 30 angstroms to 50 angstroms.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the first annealing treatment include: a temperature of 200 degrees Celsius to 500 degrees Celsius and a time of 50 seconds to 500 seconds.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening and the initial second opening includes: forming a first mask layer on the first dielectric layer, the first mask layer exposing a portion of the surface of the first dielectric layer on the initial first conductive layer; etching the first dielectric layer using the first mask layer as a mask until the surface of the initial first conductive layer is exposed to form the first opening; etching the initial first conductive layer exposed by the first opening to form a transitional second opening; and laterally etching the initial first conductive layer exposed by the transitional second opening to form the initial second opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of etching the first dielectric layer to form the first opening includes an anisotropic dry etching process; and the process of etching the initial first conductive layer to form the transitional second opening includes an anisotropic dry etching process.

12. The method for forming a semiconductor structure according to claim 10, wherein: The process of laterally etching the initial first conductive layer exposed by the transitional second opening comprises an isotropic wet etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The substrate also includes: a base; a gate structure located on the base; source-drain doped regions located in the base on both sides of the gate structure; a second dielectric layer located on the base, the second dielectric layer being located on the sidewalls of the gate structure; the initial first conductive layer being located in the second dielectric layer, and the initial first conductive layer being located on the source-drain doped regions.

14. The method for forming a semiconductor structure according to claim 13, wherein: The substrate further includes: a fin structure located on the base; the gate structure spans across the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

15. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the initial first conductive layer includes: forming a second mask layer on the second dielectric layer, the second mask layer exposing a portion of the second dielectric layer surface on the source and drain doped regions; etching the second dielectric layer using the second mask layer as a mask until the source and drain doped regions are exposed to form grooves in the second dielectric layer; forming a transitional first conductive layer in the grooves; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer.

16. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second opening, the method further includes: forming a third conductive layer in the first opening and in the second opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the third conductive layer includes: forming an initial third conductive layer in a first opening and in a second opening; forming a stop layer on the initial third conductive layer; forming a buffer layer on the stop layer; and planarizing the buffer layer, the stop layer and the initial third conductive layer to form a third conductive layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The buffer layer and the initial third conductive layer are made of the same material.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the buffer layer and the initial third conductive layer includes metal, and the metal includes tungsten.

20. The method for forming a semiconductor structure according to claim 17, wherein: The material of the stop layer includes titanium nitride.

21. The method for forming a semiconductor structure according to claim 17, wherein: The process of forming the initial third conductive layer in the first opening and in the second opening includes a selective deposition process.

22. The method for forming a semiconductor structure according to claim 21, wherein: The process parameters for forming the initial third conductive layer include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

23. The method for forming a semiconductor structure according to claim 17, wherein: The process of planarizing the buffer layer, the stop layer and the initial third conductive layer includes a chemical mechanical polishing process, and the polishing liquid of the chemical mechanical polishing process is an acidic solution.

24. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first conductive layer includes metal, and the metal includes crystalline cobalt.

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