Synchronous testing device and synchronous testing method

Abstract

The present application belongs to the field of chip testing technology, and provides a synchronous testing device and a synchronous testing method. A synchronous testing device includes: a digital stimulus response unit, a signal source unit, a signal analysis unit and a power supply unit; the digital stimulus response unit is configured to output a control signal and a first trigger signal to the chip under test and the signal source unit, respectively. Since the control signal and the first trigger signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting a radio frequency input signal to the chip under test by responding to the first trigger signal, triggering the power supply unit to supply power to the chip under test, and without configuring a test case, when testing the chip under test, work coordination and action synchronization are achieved in a more streamlined manner, simplifying the process of testing the chip under test and improving test efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a synchronous testing device and a synchronous testing method. Background Art

[0002] At present, when testing a chip, a corresponding test case is configured, and the automatic test equipment implements the test of the chip by executing the test case. However, the current automatic test equipment is provided with a variety of test components with different test functions. Accordingly, when configuring the test case of the chip, it is necessary to consider the coordination or synchronization between the test components with different test functions, which makes the configuration of the test case too complicated, which is not conducive to improving the testing and production of the chip. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a synchronous testing device and a synchronous testing method to solve the problem of low testing efficiency in chip testing in the prior art.

[0004] A first aspect of an embodiment of the present application provides a synchronous testing device, comprising: a digital stimulus response unit, a signal source unit, a signal analysis unit and a power supply unit;

[0005] A digital stimulus response unit is configured to output a control signal to the chip under test and output a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working state of the chip under test;

[0006] The signal source unit is configured to respond to the first trigger signal to output a radio frequency input signal to the chip under test, and to output a second trigger signal to the signal analysis unit and the power supply unit, wherein the radio frequency input signal is used to be input into the chip under test for processing and output a radio frequency output signal, and the second trigger signal is used to trigger the signal analysis unit to analyze and process the radio frequency output signal, and to trigger the power supply unit to supply power to the chip under test.

[0007] Furthermore, the synchronous testing device also includes: a control backplane and multiple groups of test card positions units arranged on the control backplane, each group of test card positions units includes at least one test connection card position, and the test connection card position is used to connect the digital stimulus response unit, the signal source unit and the power supply unit.

[0008] Furthermore, different test connection card positions on the same test card position unit are connected to each other to trigger synchronization, and different test connection card positions on different test card position units are configured with a trigger bus to trigger synchronization.

[0009] Furthermore, the control backplane and all the test connection card positions are connected by a trigger bus whose initial state is a low level, and all the test connection card positions use the trigger bus being pulled up to a high level as a trigger signal, or, the control backplane and all the test connection card positions are connected by a trigger bus whose initial state is a high level, and all the test connection card positions use the trigger bus being pulled down to a low level as a trigger signal.

[0010] A second aspect of an embodiment of the present application provides a synchronization test method, which is applied to a synchronization test device, including:

[0011] The digital stimulus response unit outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working state of the chip under test;

[0012] The signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip under test, and outputs a second trigger signal to the signal analysis unit and the power supply unit;

[0013] The power supply unit supplies power to the chip under test based on the first trigger signal;

[0014] The chip under test amplifies the radio frequency input signal and outputs a radio frequency output signal;

[0015] The signal analysis unit analyzes and processes the radio frequency output signal based on the second trigger signal.

[0016] Further, the control backplane obtains a preset script file, wherein the preset script file includes a backplane configuration script segment;

[0017] The control backplane sends a trigger instruction to the digital stimulus response unit according to the backplane configuration script segment to trigger the digital stimulus response unit to output a control signal to the chip under test and output a first trigger signal to the signal source unit.

[0018] Furthermore, the preset script also includes a trigger configuration script segment, and the trigger configuration script segment includes a trigger mode, a first group of transmission ports, and a second group of transmission ports;

[0019] The digital stimulus response unit responds to the trigger instruction, outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit, including:

[0020] The digital stimulus response unit responds to the trigger instruction, outputs the control signal to the chip under test through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

[0021] Further, the trigger configuration script segment includes a first marking signal;

[0022] The digital stimulus response unit responds to the trigger instruction, outputs the control signal to the chip under test through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports, including:

[0023] The digital stimulus response unit responds to a trigger instruction, outputs a control signal to the chip under test through the first group of transmission ports based on the first marking signal, and outputs a first trigger signal to the signal source unit through the second group of transmission ports.

[0024] Furthermore, the preset script also includes a signal source configuration script segment, and the signal source configuration script segment includes a second marking signal;

[0025] The signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip under test, and outputs a second trigger signal to the signal analysis unit and the power supply unit, including:

[0026] Based on the second marking signal, the signal source unit outputs a radio frequency input signal to the chip under test and outputs a second trigger signal to the signal analysis unit and the power supply unit when the first trigger signal is detected.

[0027] Furthermore, the first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.

[0028] Implementing a synchronous testing device and a synchronous testing method provided in the embodiments of the present application has the following beneficial effects:

[0029] The synchronous test device provided in the embodiment of the present application includes: a digital stimulus response unit, a signal source unit, a signal analysis unit and a power supply unit; the digital stimulus response unit is configured to output a control signal and a first trigger signal to the chip under test and the signal source unit respectively. Since the control signal and the first trigger signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting a radio frequency input signal to the chip under test by responding to the first trigger signal, triggering the power supply unit to supply power to the chip under test, so that the chip under test processes the radio frequency input signal and outputs a radio frequency output signal under the working state indicated by the control signal, and the trigger signal analysis unit analyzes and processes the radio frequency output signal output by the chip under test. Without configuring a test case, when testing the chip under test, the work coordination and action synchronization between the digital stimulus response unit, the signal source unit, the signal analysis unit and the power supply unit are realized in a more streamlined manner, simplifying the implementation process of testing the chip under test and improving the testing efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 is a structural schematic diagram of a synchronous testing device provided in an embodiment of the present application;

[0032] Figure 2 is a structural schematic diagram of a synchronization test device provided by another embodiment of the present application;

[0033] Figure 3 It is a flow chart of an implementation of a synchronization test method provided in an embodiment of the present application;

[0034] Figure 4 This is a flow chart of an implementation of a synchronization testing method provided in another embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] A synchronous testing device provided by this embodiment is described in detail below through a specific implementation method.

[0037] Figure 1 FIG. 1 is a schematic diagram showing the structure of a synchronous testing device provided in an embodiment of the present application. Figure 1 As shown, a synchronous testing device 100 provided in this embodiment includes: a digital stimulus response unit 10 , a signal source unit 20 , a signal analysis unit 30 and a power supply unit 40 .

[0038] The digital stimulus response unit 10 is configured to output a control signal to the chip under test 110 and output a first trigger signal to the signal source unit 20; the control signal and the first trigger signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test 110. The synchronous association of the control signal and the first trigger signal in the time domain means that the digital stimulus response unit 10 outputs the control signal to the chip under test 110 and outputs the first trigger signal to the signal source unit 20 at the same time point, and makes the working state of the chip under test 110 in the time domain correspond to the working state of the signal source unit 20 in the time domain, that is, the digital stimulus response unit 10, the chip under test 110 and the signal source unit 20 are synchronized in the time domain.

[0039] The signal source unit 20 is configured to respond to a first trigger signal to output a radio frequency input signal to the chip under test, and to output a second trigger signal to the signal analysis unit 30 and the power supply unit 40, wherein the radio frequency input signal is used to be input into the chip under test for processing and output a radio frequency output signal, and the second trigger signal is used to trigger the signal analysis unit 30 to analyze and process the radio frequency output signal, and to trigger the power supply unit 40 to supply power to the chip under test.

[0040] In this embodiment, when the chip under test 110 is tested by the synchronous test device 100, the chip under test 110 is electrically connected to the synchronous test device 100. Here, the chip under test 110 may be a radio frequency signal processing chip, for example, a radio frequency signal amplification chip, etc. When the chip under test 110 is tested, the digital stimulus response unit 10 sends a control signal to the chip under test 110, and sends a first trigger signal to the signal source unit 20. Here, the control signal is used to indicate the working state of the chip under test 110, that is, after receiving the control signal, the chip under test 110 works according to the working state indicated by the control signal. In this embodiment, the control signal indicates the working state of the chip under test 110, including the control signal indicating the working state of the chip under test 110 in the time domain.

[0041] It should be noted that the signal source unit 20 responds to the first trigger signal and outputs the RF input signal and the second trigger signal to the signal analysis unit 30 and the power supply unit 40, respectively. Here, since the control signal and the first trigger signal are synchronously associated in the time domain, the RF input signal and the second trigger signal output by the signal source unit 20 in response to the first trigger signal are also associated with the first trigger signal in the time domain. That is, since the control signal and the first trigger signal are synchronously associated in the time domain, the time point when the signal source unit 20 outputs the RF input signal and the time point when the signal source unit 20 outputs the second trigger signal in response to the first trigger signal are associated with the time domain of the control signal.

[0042] In all embodiments of the present application, since the digital stimulus response unit 10 outputs a control signal and a first trigger signal that are synchronized in the time domain, the signal source unit 20, when responding to the first trigger signal, can output the RF input signal and the second trigger signal according to the trigger timing set by the first trigger signal. Because the second trigger signal is used to trigger the power supply unit 40 to supply power to the chip under test, and the second trigger signal is also used to trigger the signal analysis unit 30 to analyze and process the RF output signal, the power supply unit 40 responds to the second trigger signal and supplies power to the chip under test 110 according to the time domain signal indicated by the second trigger signal. Therefore, after the power supply unit 40 supplies power to the chip under test 110, according to the received RF input signal, the chip under test 110 outputs the RF output signal to the signal analysis unit 30 under the working state indicated by the control signal. After receiving the RF output signal output by the chip under test 110, the signal analysis unit 30 responds to the second trigger signal and analyzes and processes the RF output signal according to the time domain signal indicated by the second trigger signal to obtain an analysis result, that is, the digital stimulus response unit 10, the chip under test 110, the signal source unit 20, the signal analysis unit 30 and the power supply unit 40 are synchronously associated in the time domain.

[0043] It is easy to understand that, while the digital stimulus response unit 10 sends a control signal to the chip under test 110 to instruct the chip under test 110 to enter a corresponding working state, it outputs a first trigger signal to the signal source unit 20 to trigger the signal source unit 20 to output a RF input signal to the chip under test 110, so that the chip under test 110 processes the RF input signal and outputs a RF output signal, and outputs a second trigger signal to the signal analysis unit 30 and the power supply unit 40. The second trigger signal triggers the source unit 40 to power the chip under test 110, and triggers the signal analysis unit 30 to perform data analysis on the RF output signal, so that in the process of testing the chip under test 110, the signal source unit 20, the signal analysis unit 30 and the power supply unit 40 are synchronized with the working state of the chip under test 110 under the control of the digital stimulus response unit 10.

[0044] In a specific implementation, the digital stimulus response unit 10 may select an existing digital stimulus response device, such as an MDSR board. As an example, when testing the chip under test 110, the MDSR board outputs a control signal to the chip under test 110 through a corresponding configuration port, such as a Mobile Industry Processor Interface (MIPI).

[0045] Exemplarily, the chip under test 110 is a radio frequency signal amplifier chip, which is used to amplify the radio frequency input signal and output the amplified radio frequency input signal as a radio frequency output signal. The radio frequency signal amplifier chip works in time division duplex mode, because its work in time division duplex mode is not continuous in timing, but periodic in sections. That is, the radio frequency signal amplifier chip works in a time period and outputs a certain power; the radio frequency signal amplifier chip does not work in a time period and has no power output, so the radio frequency signal amplifier chip works in time division duplex mode with periodicity, so it is necessary to synchronize the working modes of all functional components in the test device 100 to adapt to the working mode of the radio frequency signal amplifier chip. Here, since the radio frequency signal amplifier chip works in time division duplex mode with periodicity, when testing the working performance of the radio frequency signal amplifier chip in time division duplex mode, the MDSR board needs to instruct the working timing of other functional units to synchronize with the working timing of the radio frequency signal amplifier chip, thereby achieving adaptation to the working mode of the radio frequency signal amplifier chip.

[0046] In combination with the previous example, the digital stimulus response unit 10 (for example, MDSR board) outputs the first trigger signal to the signal source unit 20 through the GPIO port, or the digital stimulus response unit 10 (for example, MDSR board) outputs the first trigger signal to the signal source unit 20 through the trigger line of the modular instrument platform. Here, the modular instrument platform can be a PCI Extensions for Instrumentation (PXI) backplane for instrument systems configured based on the Peripheral Component Interconnect (PCI) standard, that is, the digital stimulus response unit 10 outputs the first trigger signal to the signal source unit 20 through the trigger line of the PXI backplane. The signal source unit 20 can use an existing RF transceiver, and output the RF input signal to the RF signal amplification chip by responding to the first trigger signal of the digital stimulus response unit 10 (for example, MDSR board), and also outputs the second trigger signal to the signal analysis unit 30 and the power supply unit 40.

[0047] In a specific embodiment, the first trigger signal and the second trigger signal are preferably pulse signals. When the signal source unit 20 detects that the first trigger signal jumps from a low level to a high level, that is, after detecting the rising edge of the first trigger signal, it immediately outputs the RF input signal and the second trigger signal. The power supply unit 40 can be an AC / DC power supply or a DC voltage regulating power supply. When the power supply unit 40 detects that the second trigger signal jumps from a low level to a high level, that is, after detecting the rising edge of the second trigger signal, it supplies power to the RF signal amplifying chip. The RF signal amplifying chip can amplify the RF input signal and output the RF output signal. At the same time, the signal analysis unit 30 can receive the RF output signal when detecting that the second trigger signal jumps from a low level to a high level, that is, after detecting the rising edge of the second trigger signal, and then analyze and process the RF output signal and output the analysis result.

[0048] Figure 2 FIG. 2 shows a schematic diagram of the structure of a synchronous testing device provided by another embodiment of the present application. Figure 2 As shown, as an embodiment, the synchronous testing device 100 also includes: a control backplane 50 and a plurality of groups of test card positions 51 arranged on the control backplane 50, each group of test card positions 51 includes at least one test connection card position 511, and the test connection card position 511 is used to connect the digital stimulus response unit 10, the signal source unit 20 and the power supply unit 40.

[0049] In this embodiment, since a plurality of test card positions 51 are provided on the control backplane 50, and each test card position unit 51 includes at least one test connection card position 511, the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 can be arranged on the control backplane 50 by using the test connection card position 511. Here, since each test card position unit 51 includes at least one test connection card position 511, a sufficient number of test connection card positions 511 can be arranged on a group of test card position units 51, and the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 can be arranged on the same group of test card position units 51. Alternatively, at least one test connection card position 511 can be arranged on a group of test card position units 51, and then the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 can be arranged on different groups of test card position units 51.

[0050] It can be understood that if the digital stimulus response unit 10, the signal source unit 20 and the power supply unit 40 are arranged on the same group of test card position units 51, the multiple test connection card positions on the same group of test card position units 51 can be connected through internal wiring, that is, the functional units on different test connection cards connected in the same group of test card position units 51 can be directly triggered synchronously, and the synchronous transmission of the trigger signal can be achieved by configuring the port transmission mode between the digital stimulus response unit 10, the signal source unit 20 and the power supply unit 40.

[0051] like Figure 2 As shown, as an embodiment, different test connection positions 511 on the same test position unit 51 are connected to each other to trigger synchronization, and different test connection positions 511 on different test position units 51 are configured with a trigger bus 52 to trigger synchronization.

[0052] In this embodiment, if the digital stimulus response unit 10 and the signal source unit 20 are arranged on two test connection positions 511 on the same group of test position units 51, the two test connection positions 511 are connected by internal wiring, so the digital stimulus response unit 10 can output the first trigger signal to the signal source unit 20 through the internal wiring between the two test connection positions 511, thereby realizing the trigger synchronization of the first trigger signal. Alternatively, if the digital stimulus response unit 10 and the signal source unit 20 are respectively arranged on two test connection positions 511 on two groups of test position units 51, the digital stimulus response unit 10 can output the first trigger signal to the signal source unit 20 through the trigger bus 52 between the two test connection positions 511, thereby realizing the trigger synchronization of the first trigger signal. Similarly, if the signal source unit 20 and the power supply unit 40 are arranged on two test connection positions 511 on the same group of test position units 51, the two test connection positions 511 are connected by internal wiring, so the signal source unit 20 can output the second trigger signal to the power supply unit 40 through the internal wiring between the two test connection positions 511, thereby realizing the trigger synchronization of the second trigger signal. Alternatively, if the signal source unit 20 and the power supply unit 40 are respectively arranged on two test connection positions 511 on two groups of test position units 51, the signal source unit 20 can output the second trigger signal to the power supply unit 40 through the trigger bus 52 between the two test connection positions 511, thereby realizing the trigger synchronization of the second trigger signal.

[0053] In an actual application process, since the signal source unit 20 outputs the second trigger signal to the signal analysis unit 30 and the power supply unit 40 simultaneously by responding to the first trigger signal, when the signal source unit 20 is connected to the signal analysis unit 30, the signal analysis unit 30 can also be configured on the test connection card position 511, or the signal source unit 20 and the signal analysis unit 30 can be connected by an external contact bus. Similarly, if the signal source unit 20 and the signal analysis unit 30 are set on two test connection card positions 511 on the same group of test card positions 51, the two test connection card positions 511 are connected by an internal wiring, so the signal source unit 20 can output the second trigger signal to the signal analysis unit 30 through the internal wiring between the two test connection card positions 511, thereby realizing the trigger synchronization of the second trigger signal. Alternatively, if the signal source unit 20 and the signal analysis unit 30 are respectively set on two test connection positions 511 on two groups of test position units 51, the signal source unit 20 can output a second trigger signal to the signal analysis unit 30 through the trigger bus 52 between the two test connection positions 511, thereby realizing the trigger synchronization of the second trigger signal.

[0054] In some embodiments, the signal source unit 20 and the signal analysis unit 30 may be integrated into the same instrument. For example, a spectrum analyzer VXT with a signal source is provided with a radio frequency signal generating unit (RF Generator) and a radio frequency signal analyzing unit (RF Analyzer). The radio frequency signal generating unit responds to a first trigger signal, outputs a radio frequency input signal to the chip under test 110, and outputs a second trigger signal to the radio frequency signal analyzing unit, triggering the radio frequency signal analyzing unit to analyze and process the radio frequency output signal output by the chip under test 110. At the same time, the radio frequency signal generating unit also outputs a second trigger signal to the power supply unit 40, triggering the power supply unit 40 to supply power to the chip under test 110.

[0055] In all embodiments of the present application, the second trigger signal is used to trigger the signal analysis unit 30 to analyze and process the RF output signal to obtain a corresponding analysis result. Here, the analysis result may include at least one of: gain data, output power data, signal-to-noise ratio, efficiency, and standing wave ratio.

[0056] It is understandable that the signal analysis unit can analyze and process the RF output signal according to the preset parameter configuration, so as to determine the various performance indicators of the chip under test 110. How the signal analysis unit analyzes and obtains the analysis results will not be described in detail here.

[0057] As an embodiment, the control backplane 50 and all the test connection positions 511 are connected with the trigger bus 52 which is initially at a high level, and all the test connection positions 511 use the trigger bus 52 being pulled down to a low level as a trigger signal.

[0058] In this embodiment, the trigger bus 52 is used to connect the control backplane 50 and all the test connection card positions 511. That is, the control backplane 50 and all the test connection card positions 511 can perform signal transmission through the trigger bus 52.

[0059] In a specific embodiment, the control backplane and all the test connection positions are connected with a trigger bus whose initial state is a high level, that is, the initial state of the signal transmitted on the trigger bus 52 is a high level, that is, when a trigger signal is sent to the test connection position 511 through the trigger bus 52, the electric pulse signal corresponding to the trigger signal changes from a high level to a low level, and the unit component connected to the test connection position 511 receives the trigger signal. When the electric pulse signal changes from a low level to a high level, the trigger signal is sent, and the trigger bus 52 returns to the initial state.

[0060] In another specific embodiment, the control backplane and all the test connection positions are connected by a trigger bus whose initial state is a low level, that is, the initial state of the signal transmitted on the trigger bus 52 is a low level, that is, when a trigger signal is sent to the test connection position 511 through the trigger bus 52, the electric pulse signal corresponding to the trigger signal changes from a low level to a high level, and the unit component connected to the test connection position 511 receives the trigger signal. When the electric pulse signal changes from a high level to a low level, the trigger signal is sent, and the trigger bus 52 returns to the initial state.

[0061] In the specific implementation, the control backplane 50 and all the test connection card positions 511 are connected by the trigger bus 52, and all the test connection card positions 511 are pulled high or low by the signal transmitted on the trigger bus 52 as a trigger signal. That is, between the functional units set on the test connection card position 511, the trigger signal transmitted through the trigger bus 52 is preferably a pulse signal. If for each functional unit on all the test connection card positions 511, the initial state of the signal transmitted on the trigger bus 52 is a low level, that is, when the pulse signal is not sent through the trigger bus 52, the initial state of the signal transmitted on the trigger bus 52 is a low level, when the test connection card position 511 or each unit on the test connection card position 511 detects that the pulse signal is converted from a low level to a high level, it starts to perform the corresponding action and function. For example: when the signal source unit detects that the first trigger signal is converted from a low level to a high level, it starts to output the RF input signal to the chip under test, and outputs the second trigger signal to the signal analysis unit and the power supply unit. When the second trigger signal is converted from a low level to a high level, the power supply unit starts to supply power to the chip under test. Similarly, between the units set on the test connection card position 511, the signal transmitted through the trigger bus 52 is a pulse signal. If for all units on the test connection card position 511, the initial state of the signal transmitted on the trigger bus 52 is a high level, that is, when the pulse signal is not sent through the trigger bus 52, the initial state of the signal transmitted on the trigger bus 52 is a high level, when the test connection card position 511 or each unit on the test connection card position 511 detects the low level of the pulse signal, the corresponding action and function are started to be executed. For example: when the signal source unit detects that the first trigger signal is converted from a high level to a low level, it starts to output the RF input signal to the chip under test, and outputs the second trigger signal to the signal analysis unit and the power supply unit. When the second trigger signal is converted from a high level to a low level, the power supply unit starts to supply power to the chip under test.

[0062] As an example, the control backplane 50 and all the test connection positions 511 are connected with the trigger bus 52 which is initially at a low level, and all the test connection positions 511 use the trigger bus 52 being pulled up to a high level as a trigger signal.

[0063] For example, Figure 2 As shown, the digital stimulus response unit 10 and the signal source unit 20 are connected to the same group of test card units 51. Assuming that the initial state of the signal transmitted between different test connection card positions on the same test card unit is a low level, when the signal source unit 20 detects that the pulse signal corresponding to the first trigger signal is converted from a low level to a high level, it responds to the first trigger signal, outputs a radio frequency input signal to the chip under test 110, and also outputs a second trigger signal to the signal analysis unit 30 and the power supply unit 40.

[0064] Combining the previous example, Figure 2 In the embodiment, the signal source unit 20 and the power supply unit 40 are respectively connected to two test connection positions 511 of different test position units. The second trigger signal transmitted between the signal source unit 20 and the power supply unit 40 through the trigger bus 52 between the two test connection positions 511 is a pulse signal. If the initial state of the signal transmitted on the trigger bus 52 is a low level, that is, when the pulse signal is not sent through the trigger bus 52, the signal transmitted on the trigger bus 52 is a low level. When the signal source unit 20 detects that the pulse signal corresponding to the first trigger signal is converted from a low level to a high level, the second trigger signal is output to the power supply unit 40. When the power supply unit 40 detects that the pulse signal is converted from a low level to a high level, the chip under test 110 is powered.

[0065] In the above scheme, the digital stimulus response unit is configured to output a control signal to the chip under test, and to output a first trigger signal to the signal source unit. Since the control signal and the first trigger signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting the RF input signal to the chip under test by responding to the first trigger signal, thereby triggering the power supply unit to supply power to the chip under test, so that the chip under test processes the RF input signal and outputs a RF output signal under the working state indicated by the control signal, and at the same time triggers the signal analysis unit to analyze and process the RF output signal output by the chip under test. Without configuring a test case, when testing the chip under test, the work coordination and action synchronization between the digital stimulus response unit, the signal source unit, the signal analysis unit and the power supply unit are realized in a more streamlined manner, thereby simplifying the implementation process of the chip under test test and improving the chip test efficiency.

[0066] The present application also provides a flow chart of a chip testing method, which is described in detail as follows:

[0067] S11: The digital stimulus response unit outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working status of the chip under test.

[0068] In step S11, the digital stimulus response unit outputs a control signal to the chip under test according to a trigger instruction, wherein the trigger instruction is an instruction for instructing the digital stimulus response unit to output a control signal to the chip under test and simultaneously output a first trigger signal to the signal source unit. In this embodiment, the trigger instruction is sent by the control backplane to the digital stimulus response unit to trigger the digital stimulus response unit to perform a corresponding function. The digital stimulus response unit responds to the trigger instruction to output a control signal to the chip under test through two different paths, and outputs a first trigger signal to the signal source unit.

[0069] In this embodiment, the digital stimulus response unit is pre-configured with a signal transmission strategy, which includes a transmission path for the digital stimulus response unit to output a control signal to the chip under test and to output a first trigger signal to the signal source unit.

[0070] In a specific implementation, the trigger instruction can be generated by the digital stimulus response unit after detecting that the chip under test has been connected to the synchronous test device, or it can be generated periodically, or it can be generated by the control backplane connected to the digital stimulus response unit by executing a preset test script file.

[0071] It can be understood that since the control signal and the first trigger signal are synchronously associated in the time domain, the rising edge / falling edge of the high-low level conversion between the pulse signal corresponding to the control signal and the pulse signal corresponding to the first trigger signal corresponds to each other, that is, the high-low level conversion time points between the pulse signal corresponding to the control signal and the pulse signal corresponding to the first trigger signal are synchronized, thereby enabling the working state of the chip under test in the time domain to be synchronized with the working state of the signal source unit in the time domain.

[0072] In this embodiment, the working state of the chip under test and the specific selection and implementation of the digital stimulus response unit are involved. Figure 1 The corresponding embodiments have been described in detail. Figure 1 as well as Figure 1 The relevant parts in the embodiments will not be repeated here.

[0073] S12: The signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip under test, and outputs a second trigger signal to the signal analysis unit and the power supply unit.

[0074] In step S12, the RF input signal is used as a signal input to the chip under test for processing, and the chip under test processes it according to the working state indicated by the control signal, and then outputs a RF output signal. The second trigger signal is used to trigger the signal analysis unit to analyze the RF output signal output by the chip under test, and is also used to trigger the power supply unit to power the chip under test.

[0075] In this embodiment, since the control signal is synchronously associated with the first trigger signal in the time domain, the RF input signal and the second trigger signal output by the signal source unit in response to the first trigger signal are also associated with the first trigger signal respectively. That is, since the control signal is synchronously associated with the first trigger signal in the time domain, the time point when the signal source unit outputs the RF input signal in response to the first trigger signal and the time point when the signal source unit outputs the second trigger signal are synchronously associated with the time point of the control signal in the time domain. Here, the signal source unit responds to the first trigger signal, and then outputs the RF input signal to the chip under test, and simultaneously outputs the second trigger signal to the signal analysis unit and the power supply unit, so that when the chip under test is tested, the signal source unit can provide the RF input signal to the chip under test, and the power supply unit can provide the working power synchronized with the working state of the chip under test, and the working state of the signal analysis unit when analyzing and processing the RF output signal output by the chip under test is synchronized with the working state of the chip under test in the time domain.

[0076] S13: The power supply unit supplies power to the chip under test based on the second trigger signal.

[0077] In step S13, since the first trigger signal and the control signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test, the signal source unit responds to the first trigger signal to output a second trigger signal to the power supply unit, and the power supply unit supplies power to the chip under test based on the second trigger signal, which is equivalent to the working state of the power supply unit supplying power to the chip under test being synchronized with the working state of the chip under test in the time domain.

[0078] In this embodiment, the working state of the chip under test is used to characterize the working time or non-working time of the chip under test, that is, the control signal indicates when the chip under test is working and when it is not working. Here, the switching between different working states of the chip under test can be set according to different working modes or different working strategies of the chip under test.

[0079] Taking the chip under test as an RF signal amplifier chip as an example, the RF signal amplifier chip is used to amplify the RF input signal and output the amplified RF input signal as an RF output signal.

[0080] As an example, the RF signal amplifying chip works in the time division duplex mode. Since its operation in the time division duplex mode is not continuous in timing, but periodic in sections. That is, the RF signal amplifying chip works in a time period and outputs a certain power; the RF signal amplifying chip does not work in a time period and has no power output. Therefore, the RF signal amplifying chip works in the time division duplex mode with periodicity, so it is necessary to synchronize the working modes of all functional components in the test device 100 to adapt to the working mode of the RF signal amplifying chip. Here, since the RF signal amplifying chip works in the time division duplex mode with periodicity, when testing the working performance of the RF signal amplifying chip in the time division duplex mode, the MDSR board needs to instruct the working timing of other functional units to be synchronized with the working timing of the RF signal amplifying chip, thereby achieving adaptation to the working mode of the RF signal amplifying chip.

[0081] In this embodiment, the specific selection and implementation of the unit unit are as follows: Figure 1 The corresponding embodiments have been described in detail. Figure 1 as well as Figure 1 The relevant parts in the embodiments will not be repeated here.

[0082] As an embodiment, step S13 includes: a power supply unit supplies power to the chip under test according to a second trigger signal.

[0083] In this embodiment, since the second trigger signal is synchronously associated with the control signal in the time domain, and the control signal is used to indicate the working state of the chip under test, the duration of the high level or the duration of the low level of the first trigger signal can not only be used to determine the working time of the chip under test, but also can be used to indicate the working time of the power supply unit supplying power to the chip under test. For example, the second trigger signal can be a rising edge signal converted from a low level to a high level. When the power supply unit receives the rising edge signal converted from a low level to a high level, it can supply power to the chip under test according to the working cycle of the chip under test, and then the working state of the power supply unit supplying power to the chip under test is synchronized with the working state of the chip under test in the time domain. For example, when the power supply unit detects that the first trigger signal is converted from a low level to a high level, it supplies power to the chip under test.

[0084] S14: The chip under test amplifies the RF input signal and outputs a RF output signal.

[0085] In step S14, the amplification process is that the chip under test amplifies the RF input signal according to the configuration instructions carried by the control signal, and then outputs the RF output signal. That is, the RF output signal is the signal output by the chip under test after amplifying the RF input signal. By analyzing and processing the RF output signal, various performance indicators of the chip under test can be determined, such as gain, linearity, maximum output power, etc.

[0086] In this embodiment, when the chip under test receives the control signal, the signal source unit outputs the RF input signal to the chip under test according to the first trigger signal, and the signal source unit also outputs the second trigger signal to the power supply unit, thereby triggering the power supply unit to supply power to the chip under test. It can be understood that the working state of the chip under test processing the received RF input signal and the working state of the power supply unit supplying power to the chip under test are synchronously associated in the time domain.

[0087] It is easy to understand that in other embodiments, the chip under test can also process the RF input signal in other ways, such as filtering, frequency conversion, etc. Correspondingly, the output RF output signal can also be the filtered RF input signal or the frequency converted RF input signal, which is not limited here.

[0088] S15: The signal analysis unit analyzes and processes the RF output signal based on the second trigger signal.

[0089] In step S15, the second trigger signal can trigger the signal analysis unit to perform analysis and processing on the radio frequency signal, and the working state of the chip under test to process the received radio frequency input signal is synchronously associated in the time domain.

[0090] In this embodiment, since the power supply unit supplies power to the chip under test, the chip under test amplifies the RF input signal in the working state indicated by the control signal, and then outputs the RF output signal to the signal analysis unit. Since the signal analysis unit and the power supply unit simultaneously receive and respond to the second trigger signal, the working state of the signal analysis unit analyzing and processing the RF signal and the working state of the chip under test processing the received RF input signal can be synchronously correlated in the time domain.

[0091] It is easy to understand that in all embodiments of the present application, both the first trigger signal and the second trigger signal can be a pulse signal with high and low level switching.

[0092] As an exemplary embodiment, the rising edge of the pulse signal can be used as a response timing, that is, when the signal source unit detects the rising edge of the first trigger signal, it starts to output the RF input signal to the chip under test, and outputs the second trigger signal to the signal analysis unit and the power supply unit. Correspondingly, when the signal analysis unit detects the rising edge of the second trigger signal, it starts to analyze and process the RF output signal. When the power supply unit detects the rising edge of the second trigger signal, it starts to power the chip under test. As another exemplary embodiment, the falling edge of the pulse signal can be used as a response timing, that is, when the signal source unit detects the falling edge of the first trigger signal, it starts to output the RF input signal to the chip under test, and output the second trigger signal to the signal analysis unit and the power supply unit. Correspondingly, when the signal analysis unit detects the falling edge of the second trigger signal, it starts to analyze and process the RF output signal. When the power supply unit detects the falling edge of the second trigger signal, it starts to power the chip under test.

[0093] In this embodiment, the signal analysis unit analyzes and processes the RF output signal based on the second trigger signal to obtain a corresponding analysis result. Here, the analysis result may include at least one of gain data, output power data, signal-to-noise ratio, efficiency, and standing wave ratio.

[0094] It is understandable that, since the RF input signal is a known signal and the working state of the chip under test is also a known parameter, the signal analysis unit can perform band analysis on the RF output signal to obtain the corresponding analysis result. Since the analysis and processing of the RF output signal can be achieved by selecting the existing band analysis technology, how the signal analysis unit analyzes and obtains the analysis result will not be described in detail here.

[0095] Figure 4 FIG. 2 shows a flow chart of a synchronous testing method according to another embodiment of the present invention. Figure 4 As shown, Figure 3 The difference is that, before step S11, this embodiment further includes steps S21 to S22. Specifically:

[0096] S21: Control the backplane to obtain a preset script file, where the preset script file includes a backplane configuration script segment.

[0097] S22: The control backplane sends a trigger instruction to the digital stimulus response unit according to the backplane configuration script segment.

[0098] In this embodiment, the trigger instruction is sent by the control backplane to the digital stimulus response unit. Here, since the control backplane is configured with a preset script file, and the preset script file includes a backplane configuration script segment, the control backplane can execute the preset script file to send a trigger instruction to the digital stimulus response unit to trigger the digital stimulus response unit to output a control signal to the chip under test, and output a first trigger signal to the signal source unit.

[0099] It should be noted that the backplane configuration script segment is used to describe the way the control backplane sends a trigger instruction to the digital stimulus response unit. The backplane configuration script defines the specific port for the control backplane to generate a trigger instruction, the transmission port for the trigger instruction, and the transmission path for the trigger instruction.

[0100] Combination Figure 2 A schematic diagram of a synchronous test device 100 is shown. Exemplarily, a plurality of test card positions 51 are provided on the control backplane 50, and each test card position unit 51 is provided with at least one test connection card position 511. In addition, all the test connection card positions 511 can be configured to trigger synchronization by configuring a trigger bus 52. Based on this, the specific port for the control backplane to generate a trigger instruction, the transmission port of the trigger instruction, and the transmission path of the trigger instruction are defined in the backplane configuration script segment, so that the control backplane can accurately transmit the trigger instruction to the digital stimulus response unit.

[0101] exist Figure 4 Correspondingly, in this embodiment, after steps S21 to S22 are executed, steps S11 to S15 are executed. As a possible implementation of this embodiment, the preset script also includes a trigger configuration script segment, and the trigger configuration script segment includes a trigger mode, a first group of transmission ports, and a second group of transmission ports. Accordingly, step S11 includes:

[0102] The digital stimulus response unit responds to the trigger instruction, executes the trigger configuration script segment, outputs the control signal to the chip under test through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

[0103] In this embodiment, the trigger mode is specifically a trigger mode in which the digital stimulus response unit, upon receiving a trigger instruction, responds to the trigger instruction, outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit.

[0104] In a specific implementation, the digital stimulus response unit can be configured to output a control signal and a first trigger signal time point in the trigger configuration script segment, and the signal source unit can be configured to work in the time domain so that the signal source unit's work in the time domain is synchronously associated with the chip under test's work in the time domain. When the digital stimulus response unit responds to the trigger instruction and executes the trigger configuration script segment, the corresponding first pulse signal is output to the chip under test through the first group of transmission ports as a control signal, and the corresponding second pulse signal is output to the signal source unit through the second group of transmission ports as the first trigger signal.

[0105] As an embodiment, the trigger configuration script segment includes a first marking signal. The trigger configuration script segment uses the first marking signal as the trigger time point for the digital stimulus response unit to output the control signal to the chip under test, and to output the first trigger signal to the signal source unit. When executing the trigger configuration script segment, the digital stimulus response unit outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit based on the first marking signal. Accordingly, in the above steps: according to the trigger mode, outputting the control signal to the chip under test through the first group of transmission ports, and outputting the first trigger signal to the signal source unit through the second group of transmission ports, includes:

[0106] The digital stimulus response unit responds to the trigger instruction, and based on the first marking signal, outputs the control signal to the chip under test through the first group of transmission ports, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

[0107] In this embodiment, the triggering method is to use the rising edge signal when the trigger signal is converted from a low level to a high level as the triggering time point, or to use the falling edge signal when the trigger signal is converted from a high level to a low level as the triggering time point. When the digital stimulus response unit responds to the trigger instruction and executes the trigger configuration script segment, based on the first mark signal, the control signal is converted from a low level to a high level, and the control signal is output to the chip under test through the first group of transmission ports. Similarly, based on the first mark signal, the first trigger signal is converted from a low level to a high level, and the first trigger signal is output to the signal source unit through the second group of transmission ports.

[0108] It is easy to understand that in specific implementation, different forms of pulse signal pairs can be selected as control signals and first trigger signals according to actual needs. It is only necessary to ensure that the pulse signal pair is correlated and synchronized in the time domain and correlated and synchronized with the working state of the chip under test in the time domain.

[0109] As a possible implementation method of this embodiment, the preset script text also includes a signal source configuration script segment, and the signal source configuration script segment includes a second marking signal. Among them, the signal source configuration script segment includes a response strategy of the signal source unit in response to the first trigger signal. In this embodiment, the response strategy of the signal source unit in response to the first trigger signal is that the signal source unit outputs a control signal to the chip under test and outputs a first trigger signal to the signal source unit based on the second marking signal when executing the trigger configuration script segment. The signal source configuration script segment uses the second marking signal as the trigger time point for outputting the control signal to the chip under test and outputting the first trigger signal to the signal source unit. Accordingly, step S12 includes:

[0110] Based on the second marker signal, the signal source unit outputs a radio frequency input signal to the chip under test and outputs a second trigger signal to the signal analysis unit and the power supply unit when a rising edge or a falling edge of the first trigger signal is detected.

[0111] In this embodiment, the signal source configuration script segment is used to describe a response strategy of the signal source unit in response to the first trigger signal, and the response strategy indicates a response action performed by the signal source unit when receiving the first trigger signal.

[0112] When the signal source unit detects the rising edge or the falling edge of the first trigger signal, it can output the radio frequency input signal to the chip under test, and output the second trigger signal to the signal analysis unit and the power supply unit.

[0113] In this embodiment, the first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.

[0114] It is easy to understand that the "first rising edge signal" and the "first falling edge signal" that appear in the embodiments of the present application are examples of the first trigger signal, and the "second rising edge signal" and the "second falling edge signal" are examples of the second trigger signal, which are only used to distinguish different types of signals output by different units. In actual applications, only one rising edge signal or one falling edge signal can be used as the application of different signals between different units. This should not be understood as a limitation on the type of rising edge signal or falling edge signal.

[0115] exist Figure 4 In the corresponding embodiment, after step S12 is executed, steps S13 to S15 are executed. For the specific implementation of steps S13 to S15, please refer to Figure 3 The corresponding embodiments will not be described in detail here.

[0116] As an embodiment, the synchronization test method further includes the following steps:

[0117] After the power supply unit stops supplying power to the chip under test and waits for a preset period of time, the power supply unit measures and outputs the electrical property data of the chip under test based on the analysis result of the RF output signal and the power supply data of the chip under test.

[0118] In this embodiment, the preset duration is used to describe the waiting time of the power supply unit. The electrical attribute data includes at least one of the working current value of the chip under test, the power value of the chip under test, and the power consumption value of the chip under test. The power supply data is the electrical data when the power supply unit supplies power to the chip under test, for example, the power supply voltage value, the power supply current value, the power supply duration, etc.

[0119] It should be noted that the power supply unit supplies power to the chip under test by responding to the second trigger signal, wherein the second trigger signal triggers the power supply unit to provide working power synchronized with the working state of the chip under test. After the power supply unit stops supplying power to the chip under test, it waits for a preset period of time and then performs electrical property data analysis based on the analysis results of the RF output signal and the power supply data to obtain the electrical property analysis results.

[0120] It is easy to understand that since the power supply data is the electrical data when the power supply unit supplies power to the chip under test, the analysis results of the RF output signal may include: gain data, output power data, signal-to-noise ratio, efficiency and at least one of standing wave ratio.

[0121] In the above scheme, the digital stimulus response unit responds to the trigger instruction, outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit. Since the control signal and the first trigger signal are synchronously associated in the time domain, and the control signal is used to indicate the working state of the chip under test, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting the RF input signal to the chip under test by responding to the first trigger signal, thereby triggering the power supply unit to supply power to the chip under test, so that the chip under test processes the RF input signal and outputs a RF output signal under the working state indicated by the control signal, and at the same time triggers the signal analysis unit to analyze and process the RF output signal output by the chip under test. Without configuring a test case, when testing the chip under test, the work coordination and action synchronization between the digital stimulus response unit, the signal source unit, the signal analysis unit and the power supply unit are realized in a more streamlined manner, thereby simplifying the implementation process of the chip under test test and improving the chip test efficiency.

[0122] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A synchronous testing device, characterized in that: include: A digital stimulus response unit, a signal source unit, a signal analysis unit and a power supply unit; A digital stimulus response unit is configured to output a control signal to the chip under test, and output a first trigger signal to a signal source unit; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working state of the chip under test; The signal source unit is configured to respond to the first trigger signal to output a radio frequency input signal to the chip under test, and output a second trigger signal to the signal analysis unit and the power supply unit, wherein the radio frequency input signal is used to be input into the chip under test for processing and output a radio frequency output signal, and the second trigger signal is used to trigger the signal analysis unit to analyze and process the radio frequency output signal, and trigger the power supply unit to supply power to the chip under test; During the testing of the chip under test, the signal source unit, the signal analysis unit and the power supply unit are controlled by the digital stimulus response unit and synchronized with the working state of the chip under test.

2. The synchronous testing device according to claim 1, characterized in that: The synchronous testing device also includes: a control backplane and multiple groups of test card units arranged on the control backplane, each group of test card units includes at least one test connection card, and the test connection card is used to connect the digital stimulus response unit, the signal source unit and the power supply unit.

3. The synchronous testing device according to claim 2, characterized in that: Different test connection card positions on the same test card position unit are connected to each other to trigger synchronization, and different test connection card positions on different test card position units are triggered synchronously by configuring a trigger bus.

4. The synchronous testing device according to claim 3, characterized in that: The control backplane and all the test connection card positions are connected with a trigger bus whose initial state is a low level, and all the test connection card positions use the trigger bus being pulled up to a high level as a trigger signal, or the control backplane and all the test connection card positions are connected with a trigger bus whose initial state is a high level, and all the test connection card positions use the trigger bus being pulled down to a low level as a trigger signal.

5. A synchronous testing method, characterized in that: The synchronous testing device according to claim 1 comprises: The digital stimulus response unit outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working state of the chip under test; The signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip under test, and outputs a second trigger signal to the signal analysis unit and the power supply unit; The power supply unit supplies power to the chip under test based on the second trigger signal; The chip under test amplifies the radio frequency input signal and outputs a radio frequency output signal; The signal analysis unit analyzes and processes the radio frequency output signal based on the second trigger signal.

6. The synchronous testing method according to claim 5, characterized in that: Before the digital stimulus response unit outputs the control signal to the chip under test and outputs the trigger signal to the signal source unit, it also includes: The control backplane obtains a preset script file, wherein the preset script file includes a backplane configuration script segment; The control backplane sends a trigger instruction to the digital stimulus response unit according to the backplane configuration script segment to trigger the digital stimulus response unit to output a control signal to the chip under test and output a first trigger signal to the signal source unit.

7. The synchronous testing method according to claim 6, characterized in that: The preset script also includes a trigger configuration script segment, and the trigger configuration script segment includes a trigger mode, a first group of transmission ports, and a second group of transmission ports; The digital stimulus response unit responds to the trigger instruction, outputs a control signal to the chip under test, and outputs a first trigger signal to the signal source unit, including: The digital stimulus response unit responds to the trigger instruction, outputs the control signal to the chip under test through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

8. The synchronous testing method according to claim 7, characterized in that: The trigger configuration script segment includes a first marking signal; The digital stimulus response unit responds to the trigger instruction, outputs the control signal to the chip under test through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports, including: The digital stimulus response unit responds to a trigger instruction, outputs a control signal to the chip under test through the first group of transmission ports based on the first marking signal, and outputs a first trigger signal to the signal source unit through the second group of transmission ports.

9. The synchronous testing method according to claim 8, characterized in that: The preset script also includes a signal source configuration script segment, and the signal source configuration script segment includes a second marking signal; The signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip under test, and outputs a second trigger signal to the signal analysis unit and the power supply unit, including: Based on the second marking signal, the signal source unit outputs a radio frequency input signal to the chip under test and outputs a second trigger signal to the signal analysis unit and the power supply unit when the first trigger signal is detected.

10. The synchronous testing method according to claim 9, characterized in that: The first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.

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