FinFET device manufacturing method

Abstract

The present invention provides a method for manufacturing a FinFET device, comprising: providing a substrate, the substrate comprising a device region and a partition region; forming a FinFET structure on the device region and the partition region; forming a mask layer on the FinFET structure, using the mask layer to remove the FinFET structure on the partition region to form a groove exposing the partition region; forming a partition structure in the groove, using the partition structure to isolate the FinFET structure in the device region. In the present invention, the FinFET structure is formed on the device region and the partition region, and then the FinFET structure in the partition region is removed to form the partition structure. The FinFET structure in the device region can be formed in an environment with relatively uniform structure and stress, avoiding the risk of problems such as fin bending caused by the different structures of the device region and the partition region when forming the FinFET structure, thereby improving the yield of manufacturing FinFET devices. Moreover, in the entire manufacturing process of the FinFET device, the process of repeatedly removing the related structures of the partition region is avoided, which is conducive to simplifying the process and improving efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for manufacturing a FinFET device. Background Art

[0002] With the continuous development of semiconductor technology, traditional planar devices can no longer meet people's demand for high-performance devices. Finfield-EffectTransistor (FinFET) is a three-dimensional device, including fins formed vertically on the substrate and high dielectric constant metal gates (HKMG) intersecting the fins. This design can greatly improve circuit control and reduce leakage, and can also greatly shorten the gate length of the transistor.

[0003] Among them, the manufacturing process of FinFET devices can be roughly divided into front-end process, middle-end process and back-end process. The front-end process is used to form a fin structure and a gate structure on a substrate, the middle-end process is used to form a local interconnection structure between the fin structure and the gate structure to form a FinFET structure, and the back-end process is used to form an interconnection structure on the FinFET structure to form a FinFET device.

[0004] Taking the existing front-end process and middle-end process as an example, the substrate includes a device area and a partition area, and the partition structure of the partition area is formed almost simultaneously with the device structure of the device area. For example: first, fins (fin structures) are formed on the device area and the partition area, and then the fins in the partition area are removed; a gate structure is formed on the device area and the partition area, and then the gate structure of the partition area is removed; a local interconnection structure is formed on the device area and the partition area, and then the local interconnection structure of the partition area is removed. In the above-mentioned front-end process and middle-end process, there have always been problems such as fin bending, gate structure and local interconnection structure residues that are difficult to solve, causing great trouble to process debugging. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a FinFET device, so as to solve the problem that the partition structure of the partition region affects the FinFET structure of the device region during the formation process.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a FinFET device, comprising: providing a substrate, the substrate comprising a device region and an isolation region; forming a FinFET structure on the device region and the isolation region, the FinFET structure comprising a fin structure, a gate structure, a local interconnect structure and an interlayer dielectric layer, the gate structure and the local interconnect structure are both located on the fin structure, and the interlayer dielectric layer covers the local interconnect structure and the gate structure; forming a mask layer on the FinFET structure, using the mask layer to remove the FinFET structure on the isolation region to form a trench exposing the isolation region; forming an isolation dielectric layer in the trench to form a isolation structure, and using the isolation structure to isolate the FinFET structure in the device region.

[0007] Optionally, the local interconnect structure includes a source-drain interconnect structure, the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer covers the source-drain interconnect structure, and the second interlayer dielectric layer covers the gate structure.

[0008] Optionally, the local interconnect structure further includes a gate interconnect structure, the gate interconnect structure is located on the gate structure, and the second interlayer dielectric layer covers the gate interconnect structure.

[0009] Optionally, a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer.

[0010] Optionally, the fin structure includes a fin and a source-drain structure formed on the fin, and the source-drain structure is located on both sides of the gate structure.

[0011] Optionally, a sidewall structure is further provided between the source-drain structure and the gate structure, and the sidewall structure of the partition region is retained in the trench.

[0012] Optionally, the step of forming a groove exposing the isolation region includes: forming a mask layer on the FinFET structure, and using the mask layer to remove the interlayer dielectric layer on the isolation region; wet etching to remove the local interconnect structure and gate structure of the isolation region; and removing the fin structure of the isolation region to form a groove exposing the isolation region.

[0013] Optionally, after removing the FinFET structure in the isolation region, etching of a portion of the thickness of the substrate is continued.

[0014] Optionally, the material of the isolation dielectric layer includes silicon oxide.

[0015] Optionally, the isolation dielectric layer is formed by using a FCVD process.

[0016] To sum up, the present invention forms a FinFET structure on the device area and the partition area, and then removes the FinFET structure in the partition area to form a partition structure. The FinFET structure in the device area can be formed in an environment with relatively uniform structure and stress, thereby avoiding the risks of fin bending, gate structure and local interconnection structure residues caused by the different structures of the device area and the partition area when forming the FinFET structure, thereby improving the yield of manufacturing FinFET devices. Moreover, in the entire manufacturing process of the FinFET device, the process of repeatedly removing the related structures of the partition area is avoided, which is conducive to simplifying the process and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0018] Figure 1 Flow chart of the method for manufacturing a FinFET device provided in an embodiment of the present application

[0019] Figure 2a to Figure 2i It is a structural schematic diagram corresponding to the corresponding steps of a method for manufacturing a FinFET device provided in this embodiment.

[0020] In the attached figure:

[0021] 10-substrate; 10a-device area; 10b-isolation area;

[0022] 210 - fin structure; 210a - fin; 210b - source-drain structure; 220 - gate structure; 221 - gate metal layer; 222 - gate dielectric layer;

[0023] 230a-source-drain interconnection structure; 240-interlayer dielectric layer; 240a-first interlayer dielectric layer; 240b-second interlayer dielectric layer; 260-sidewall structure;

[0024] 270-groove; 280-isolation dielectric layer;

[0025] 310 - first mask; 250a - first opening; 320 - second mask; 250b - second opening; 330 - third mask;

[0026] D1-first direction; D2-second direction. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0029] Figure 1 It is a flow chart of a method for manufacturing a FinFET device provided in an embodiment of the present application.

[0030] like Figure 1 As shown, the method for manufacturing a FinFET device provided in this embodiment includes the following steps:

[0031] S01: providing a substrate, wherein the substrate comprises a device region and a partition region;

[0032] S02: forming a FinFET structure on the device region and the isolation region, wherein the FinFET structure includes a fin structure, a gate structure, a local interconnect structure and an interlayer dielectric layer, wherein the gate structure and the local interconnect structure are both located on the fin structure, and the interlayer dielectric layer covers the local interconnect structure and the gate structure;

[0033] S03: forming a mask layer on the FinFET structure, and removing the FinFET structure on the partition region by using the mask layer to form a trench exposing the partition region;

[0034] S04: forming an isolation dielectric layer in the trench to form an isolation structure, and utilizing the isolation structure to isolate the FinFET structure in the device region.

[0035] Figure 2a to Figure 2i is a schematic diagram of the structure corresponding to the corresponding steps of the method for manufacturing a FinFET device provided in an embodiment of the present application. Next, Figure 2a to Figure 2iA method for manufacturing a FinFET device is described in detail.

[0036] First, please refer to Figure 2a , step S01 is performed to provide a substrate 10, wherein the substrate 10 includes a device region 10a and a partition region 10b.

[0037] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In this embodiment, a silicon substrate is used as an example for description.

[0038] The device region 10a is used to form a FinFET device, and the isolation region 10b may be located, for example, between two device regions 10a, and is used to form an isolation structure to isolate the FinFET devices on the two device regions 10a. In practice, the isolation region may be set in any suitable shape and at a suitable position as required, and the shape and position of the isolation region are not limited in this embodiment.

[0039] Next, please refer to Figure 2b and Figure 2c , execute step S02 to form a FinFET structure on the device area 10a and the isolation area 10b, the FinFET structure including a fin structure 210, a gate structure 220, a local interconnect structure and an interlayer dielectric layer 240, the gate structure 220 and the local interconnect structure are both located on the fin structure 210, and the interlayer dielectric layer 240 covers the local interconnect structure 230 and the gate structure 220.

[0040] The specific process may include, first, forming a plurality of fins 210a on the substrate 10 by using, for example, a multi-patterning technique, wherein the plurality of fins 210a extend along a first direction D1 and are arranged at intervals along a second direction D2, wherein the first direction D1 may be orthogonal to the second direction D2. A shallow trench isolation structure (not shown in the figure) is formed between adjacent fins 210a to isolate and define the height of the fins 210a.

[0041] Next, a source-drain structure 210b, a gate structure 220, and a local interconnect structure 230 are formed on the fins 210a of the device region 10a and the partition region 10b. Specifically, for example, a virtual gate extending along the second direction D2 may be first formed, a sidewall structure 260 surrounding the virtual gate along the sidewall of the virtual gate may be formed, and a source-drain structure 210b may be formed in the fins 210a on both sides of the virtual gate using the virtual gate structure and the sidewall structure 260; a first interlayer dielectric layer 240a is formed to fill between the virtual gates and located on the source-drain structure 210b, and then the virtual gate is removed, and a gate structure 220 is formed in the groove formed by removing the virtual gate structure. The gate structure 220 includes a gate dielectric layer 222 filled in the outer wall covering the fin 210a and a gate conductive layer 221 located on the gate dielectric layer 222.

[0042] It should be noted that, in the process of forming the above-mentioned fin structure 210 and gate structure 220, the fin 210a with uniform structure in the device area 10a and the partition area 10b is used to form a source-drain structure 210b and a gate structure 220 with better quality in the device area 10a, especially in the device area 10a around the partition area 10b, so as to reduce the deformation of the fin 210a caused by the inconsistent density of the fin 210a and a series of problems caused by the deformation of the fin 210a. It should be understood that the deformation (bending or tilting) of the fin 210a will lead to large differences in the etching rate, cleaning rate and deposition rate of different regions in subsequent processes such as etching process, cleaning process and thin film deposition process, and thus cause corresponding quality problems.

[0043] Next, a second interlayer dielectric layer 240b and a local interconnect structure are formed in the device region 10a and the isolation region 10b to form a FinFET structure. The FinFET structure in this embodiment may adopt a COAG (Contact Over Active Gate) structure, and a local interconnect structure is directly drawn out on the gate structure and the source-drain structure to make the device arrangement more compact, and the area of ​​a single device can be further compressed.

[0044] Specifically, the local interconnect structure includes a source-drain interconnect structure 230a, which is located in the first interlayer dielectric layer 240a and electrically connected to the source-drain structure 210b to lead the source-drain structure 210b upward. The interlayer dielectric layer 240 includes a first interlayer dielectric layer 240a and a second interlayer dielectric layer 240b, wherein the first interlayer dielectric layer 240a covers the source-drain interconnect structure 230a, and the second interlayer dielectric layer 240b covers the gate structure 220. The top surfaces of the first interlayer dielectric layer 240a, the second interlayer dielectric layer 240b, and the sidewall structure 260 therebetween are flush or substantially flush, so as to facilitate the subsequent yellow light process.

[0045] In other specific embodiments, a gate interconnection structure electrically connected to the gate structure may be formed in the second interlayer dielectric layer 240b to lead the gate structure 220 upward. Of course, it is also feasible to form the gate interconnection structure after forming the partition in the partition region 10b as in the present embodiment.

[0046] Preferably, the material of the first interlayer dielectric layer 240a is different from the material of the second interlayer dielectric layer 240b, so as to utilize the etching selectivity of the first interlayer dielectric layer 240a and the second interlayer dielectric layer 240b, and facilitate the self-alignment of the partition structure while also facilitating the self-alignment when forming the local interconnect structure. In this embodiment, the material of the first interlayer dielectric layer 240a is silicon carbide, the material of the second interlayer dielectric layer 240b is silicon oxycarbide, and the material of the sidewall structure 260 is silicon nitride.

[0047] It should be noted that the above-mentioned method of forming a FinFET structure on the device region 10a and the isolation region 10b of the substrate is only a preferred embodiment. In practice, there may also be other FinFET structure methods, but in these other FinFET structure methods, the structures of the device region 10a and the isolation region 10b maintain integrity or uniformity.

[0048] Next, please refer to Figure 2d , perform step S03, form a first mask 310 partially exposing the partition area 10b on the surface of the substrate 10, the first mask 310 at least exposes the first interlayer dielectric layer 240a of the partition area 10b, and use the first mask 310 to etch and remove the first interlayer dielectric layer 240a of the partition area 10b to form a first opening 250a of the source-drain interconnection structure 230a exposing the partition area 10b.

[0049] Specifically, the opening edge of the first mask 310 is located on the sidewall structure 260 or the second interlayer dielectric layer 240b on both sides of the partition area 10b, so as to increase the size deviation capacity and position deviation capacity of the first mask 310, which is conducive to improving the etching yield. It should be understood that the first interlayer dielectric layer 240a, the sidewall structure 260 and the second interlayer dielectric layer 240b are periodically arranged on the top surface of the device area 10a and the partition area 10b, the width of the first interlayer dielectric layer 240a and the second interlayer dielectric layer 240b is relatively wide, and the width of the sidewall structure 260 is relatively narrow, for example, the thickness is less than 30 angstroms, and it is very difficult to directly position the opening edge of the first mask 310 on the sidewall structure 260. In practice, the first mask 310 may include a multilayer structure, such as a photoresist layer, an anti-reflection layer, etc., to facilitate improving the size and position accuracy of the opening of the first mask 310.

[0050] Then, if Figure 2eAs shown, the first mask 310 and the first opening 250a are used to remove the source-drain interconnection structure 230a in the isolation region 10b by wet etching to expose the source-drain structure 210b.

[0051] Next, please refer to Figure 2f , remove the first mask 310, form a second mask 320 on the surface of the substrate 10 to partially expose the partition area 10b, the second mask 320 at least exposes the second interlayer dielectric layer 240b of the partition area 10b, and use the second mask 320 to remove the second interlayer dielectric layer 240b of the partition area 10b to form a second opening 250b of the gate structure 220 exposing the partition area 10b.

[0052] Among them, the opening edge of the second mask 320 is located on the sidewall structure 260 on both sides of the second interlayer dielectric layer 240b or the source-drain interconnection structure 230a (or the first interlayer dielectric layer 240a) on both sides of the second interlayer dielectric layer 240b, so as to increase the position deviation capacity and size deviation capacity of the second mask 320, which is beneficial to improving the etching yield.

[0053] Then, if Figure 2g As shown, the gate structure 220 in the isolation region 10b is removed by wet etching using the second mask 320 and the second opening 250b to expose the fin 210a.

[0054] It should be noted that, in this embodiment, there is no limitation on the order of removing the first interlayer dielectric layer 240a, the second interlayer dielectric layer 240b, and other structures located thereunder in the partition region 10b. For example, a second mask 320 may be formed first, and the second interlayer dielectric layer 240b and the gate structure 220 may be removed using the second mask 320, and then the first interlayer dielectric layer 240a and the source-drain interconnection structure may be removed using the first mask 310.

[0055] Next, please refer to Figure 2h , remove the second mask 320, form a third mask 330 on the surface of the substrate 10, the opening of the third mask 330 exposes the first opening 250a and the second opening 250b, and use the third mask 330 to etch and remove the source / drain structure 210b and the fin 210a of the partition area 10b to form a groove 270 of the substrate exposing the partition area 10a.

[0056] Specifically, after removing the second mask 320, a wet cleaning process may be performed on the substrate 10 to remove particles and residues, so as to facilitate the subsequent etching process. The opening edge of the third mask 330 may be located on the sidewall structure 260 or the interlayer dielectric layer at the edge of the partition area 10b. After removing the source-drain structure 210b and the fin 210a of the partition area, that is, removing the FinFET structure of the partition area 10a, the substrate may continue to be etched to a certain depth, so as to improve the partition effect and form the groove 270.

[0057] In this embodiment, the original sidewall structure 260 is retained in the trench 270 formed by removing the FinFET structure of the isolation region 10b to save process steps. Of course, in the actual process, the sidewall structure 260 in the trench 270 can also be etched away to facilitate the subsequent filling of the isolation dielectric layer.

[0058] Next, please refer to Figure 2i , executing step S04, forming an isolation dielectric layer 280 in the trench 270 to serve as an isolation structure and isolate the FinFET structure in the device area.

[0059] Specifically, a blocking dielectric material layer may be formed to fill the trench and extend to cover the interlayer dielectric layer 240 of the device region 10a, and then the blocking dielectric material layer is subjected to a grinding process using the interlayer dielectric layer 240 of the device region 10a as a grinding stop layer to form a blocking dielectric layer 280 filling the trench 270. The material of the blocking dielectric layer 280 may be silicon oxide, and the blocking dielectric layer 280 may be formed by, for example, an FCVD method to facilitate the formation of a better filling effect.

[0060] In this embodiment, after forming a FinFET structure with uniform structure and good quality on the device area 10a and the isolation area 10b, the FinFET structure of the isolation area 10b is removed to isolate the FinFET structure of the device area 10a. This not only solves the problems of fin deformation, gate structure and local interconnection structure residue caused by the uneven (different) structures of the device area and the isolation area, but also simplifies the entire manufacturing process accordingly.

[0061] Of course, the manufacturing method of the FinFET device exemplified in this embodiment also includes subsequent back-end process technology, such as interconnection process, and other corresponding process steps are also included in other embodiments of the present application, but the formation of the above steps is formed by methods commonly used in the field and will not be repeated here.

[0062] To sum up, the present invention forms a FinFET structure on the device area and the partition area, and then removes the FinFET structure in the partition area to form a partition structure. The FinFET structure in the device area can be formed in an environment with relatively uniform structure and stress, thereby avoiding the risks of fin bending, gate structure and local interconnection structure residues caused by the different structures of the device area and the partition area when forming the FinFET structure, thereby improving the yield of manufacturing FinFET devices. Moreover, in the entire manufacturing process of the FinFET device, the process of repeatedly removing the related structures of the partition area is avoided, which is conducive to simplifying the process and improving efficiency.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a FinFET device, characterized in that: include: Providing a substrate, the substrate comprising a device region and a partition region; A FinFET structure is formed on the device region and the isolation region, wherein the FinFET structure includes a fin structure, a gate structure, a local interconnect structure and an interlayer dielectric layer, wherein the gate structure and the local interconnect structure are both located on the fin structure, and the interlayer dielectric layer covers the local interconnect structure and the gate structure, wherein the fin structure includes a fin and a source-drain structure formed on the fin, wherein the gate structure is a gate structure re-formed after removing a dummy gate structure, and wherein the local interconnect structure includes a source-drain interconnect structure and a gate interconnect structure; forming a mask layer on the FinFET structure, and removing the FinFET structure on the partition region by using the mask layer to form a trench exposing the partition region; An isolation dielectric layer is formed in the trench to form an isolation structure, and the isolation structure is used to isolate the FinFET structure in the device area.

2. The method for manufacturing a FinFET device according to claim 1, wherein: The interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer covers the source-drain interconnection structure, and the second interlayer dielectric layer covers the gate structure.

3. The method for manufacturing a FinFET device according to claim 2, characterized in that: The gate interconnection structure is located on the gate structure, and the second interlayer dielectric layer covers the gate interconnection structure.

4. The method for manufacturing a FinFET device according to claim 2 or 3, characterized in that: The material of the first interlayer dielectric layer is different from the material of the second interlayer dielectric layer.

5. The method for manufacturing a FinFET device according to claim 1, wherein: The source-drain structure is located at two sides of the gate structure.

6. The method for manufacturing a FinFET device according to claim 5, characterized in that: A sidewall structure is further provided between the source-drain structure and the gate structure, and the sidewall structure of the partition region is retained in the trench.

7. The method for manufacturing a FinFET device according to claim 1, characterized in that: The step of forming a groove exposing the partition region comprises: forming a mask layer on the FinFET structure, and removing the interlayer dielectric layer on the isolation region by using the mask layer; Wet etching to remove the local interconnection structure and gate structure of the isolation area; The fin structure of the isolation region is removed to form a trench exposing the isolation region.

8. The method for manufacturing a FinFET device according to claim 1 or 7, characterized in that: After removing the FinFET structure in the isolation region, etching continues to partially remove the substrate.

9. The method for manufacturing a FinFET device according to claim 1, wherein: The material of the isolation dielectric layer includes silicon oxide.

10. The method for manufacturing a FinFET device according to claim 9, characterized in that: The isolation dielectric layer is formed by using a FCVD process.

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