A low-capacitance unidirectional ESD protection device and a manufacturing method thereof

Abstract

The present invention discloses a low-capacitance unidirectional ESD protection device, wherein a P-type reverse doping region, a P+ diffusion region, and an N+ diffusion region are arranged on the front of a P-type material; a deep energy level impurity doping region is arranged on the N+ diffusion region; and a dielectric layer is arranged between two adjacent P+ diffusion regions and between two adjacent N+ diffusion regions. An anode and a cathode metal layer are arranged on the dielectric layer, respectively. A method for manufacturing a low-capacitance unidirectional ESD protection device comprises the following steps: 1. preparing a P-type material. 2. growing a sacrificial oxide layer, and arranging a P-type reverse doping region on the front. 3. arranging a P+ diffusion region and an N+ diffusion region on the front. 4. photolithography to form a deep energy level doping region on the front. 5. removing the sacrificial oxide layer, depositing a dielectric layer, and photolithography to form contact hole regions of the cathode and the anode on the front. 6. photolithography to form an anode metal layer and a cathode metal layer on the front. The present application realizes low capacitance to meet the requirements of high-speed interfaces, and avoids premature breakdown of surface voltage and premature failure during current discharge.

Description

Technical Field

[0001] The invention belongs to the field of electronic science and technology, and mainly relates to the field of integrated circuit electrostatic discharge (ESD) protection, and specifically is a low-capacitance unidirectional ESD protection device and a manufacturing method thereof. Background Art

[0002] Electrostatic discharge (ESD) is an important cause of damage or even failure of integrated circuit products. Integrated circuit products are extremely susceptible to ESD during their production, manufacturing, assembly and operation, causing internal damage to the product and reduced reliability. Therefore, research on high-performance and high-reliability ESD protection devices plays a key role in improving the yield and reliability of integrated circuits. Usually, the design of ESD protection devices needs to consider three basic parameters: voltage, capacitance, and discharge capacity. In high-speed interface protection, it is necessary to achieve other characteristics such as voltage, discharge current, and high reliability while ensuring low capacitance.

[0003] Devices commonly used for ESD protection include diodes, BJTs (transistors), SCRs (silicon controlled rectifiers), etc. The BJT structure obtains a shallow retrace characteristic due to the introduction of the injection modulation effect. The SCR structure achieves a deep retrace characteristic through the positive feedback mechanism of PNPN. Therefore, in terms of residual voltage parameters, the SCR structure is the lowest, followed by the BJT structure, and the diode structure is the highest. Since the SCR deep retrace voltage is around 2V, which is significantly lower than common power supply voltages such as 3.3V and 5V, the SCR structure will generate latching in some applications and cannot return to the blocking state after the ESD pulse is discharged, which limits the application scenarios of SCR structure devices. Therefore, the BJT structure is a better choice for most application scenarios.

[0004] For unidirectional ESD protection devices with BJT structures used in high-speed interfaces, a lateral NPN structure with a short-circuit area is generally used. This is because NPN has a larger amplification factor and better performance. Its structure is as follows Figure 2 As shown, a P+ diffusion region 103 and an N+ diffusion region 104 are formed on the P-type material 101, and a surface passivation layer 113 plays a role in dielectric isolation. The anode metal layer 107 and the cathode metal layer 108 are the anode and cathode of the ESD protection device respectively.

[0005] Figure 2 The lateral NPN structure with short-circuit region shown is a parallel connection of a diode structure and a BJT structure, and there is a base series resistor between the base and emitter of the NPN. Its IV characteristic curve and equivalent circuit diagram are shown in Figure 3As shown, when the anode metal layer 107 is connected to a high potential and the cathode metal layer 108 is connected to a low potential, the current passes through the P+ diffusion region 103, the P-type material 101, and the N+ diffusion region 104 in the loop, showing the forward conduction characteristics of the diode. When the cathode metal layer 108 is connected to a high potential and the anode metal layer 107 is connected to a low potential, the diode composed of the N+ diffusion region 104 and the P-type material 101 first undergoes avalanche breakdown, and the avalanche current first passes through the P+ diffusion region 103 to the anode. When the voltage drop on the base resistor is greater than 0.7V, the BJT is turned on, thereby showing the shallow retrace breakdown characteristics as shown in the figure. Figure 2 The protection structure of the unidirectional ESD protection device shown is a lateral NPN structure with a short-circuit region, which has lower capacitance and stronger discharge capability than a diode structure. Since the breakdown voltage is determined by the reverse biased diode, the doping concentration of the P-type material 101 corresponding to the low breakdown voltage is very high, and the corresponding junction capacitance is also large. Figure 2 The structure shown cannot meet the requirements of low capacitance and strong discharge capability of high-speed interfaces.

[0006] CN111370408A discloses a low residual voltage and low capacitance unidirectional ESD protection device and a manufacturing method thereof, comprising an N-type single crystal, three isolation dielectric layers are arranged on the top surface of the N-type single crystal, a front metal area is arranged between two adjacent isolation dielectric layers, a P-type diffusion area is arranged on one side of the top of the N-type single crystal, and a connected N-type contact area and a P-type contact area are arranged on the other side, the bottom of the P-type diffusion area is an N-type adjustment area, and a connected N-type contact area and a P-type contact area are arranged on the top, and the N-type contact area and the P-type contact area on the top of the P-type diffusion area and the N-type contact area and the P-type contact area on the other side of the top of the N-type single crystal are respectively arranged under the two front metal areas on the top surface of the N-type single crystal to reduce the residual voltage. However, it is an SCR silicon controlled rectifier, and only the N-type adjustment area is introduced. Due to the large difference between the surface concentration of the N-type single crystal area and the concentration of the N-type adjustment area formed by injection, the IV characteristic presents an abnormal segmented retrace. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a low-capacitance unidirectional ESD protection device and a manufacturing method thereof, which can reduce junction capacitance by 50-90%, achieve low capacitance to meet high-speed interface application requirements, avoid IV characteristic abnormalities, and improve reliability.

[0008] In order to solve the above technical problems, the present invention provides a low-capacitance unidirectional ESD protection device, comprising: a P-type material, a P+ diffusion region, an anode metal layer, and a cathode metal layer; a P-type reverse doping region, a P+ diffusion region, and an N+ diffusion region are arranged on the front of the P-type material; a deep energy level impurity doping region is arranged on the N+ diffusion region by photolithography; a surface dielectric layer is arranged between two adjacent P+ diffusion regions and between two adjacent N+ diffusion regions. An anode metal layer and a cathode metal layer are arranged on the dielectric layer respectively.

[0009] By adopting the above technical solution, when the anode metal layer is connected to a high potential and the cathode metal layer is connected to a low potential, the characteristics are manifested as the forward conduction characteristics of the diode; when the cathode metal layer is connected to a high potential and the anode metal layer is connected to a low potential, the characteristics are manifested as the shallow retrace breakdown characteristics of the transistor.

[0010] Furthermore, the device structure is bilaterally symmetrical and is connected in series to form a bidirectional structure; wherein the spacing between the P+ diffusion regions on both sides is >100um.

[0011] By adopting the above technical solution, the lateral parasitic device is prevented from being turned on.

[0012] Furthermore, the P-type material is replaced with a silicon-on-insulator SOI, which includes an N+ substrate material, an isolation groove, an oxide layer and a P-type material. The N+ substrate material is provided with a P-type material through an oxide layer, and isolation grooves are spaced apart on the N+ substrate material, the oxide layer and the P-type material.

[0013] By adopting the above technical solution, the chip area of ​​the bidirectional structure is reduced by 30~50% on the original basis after replacing the material.

[0014] A method for manufacturing a low-capacitance unidirectional ESD protection device comprises the following steps:

[0015] Step 1: Prepare P-type material.

[0016] Step 2: grow a sacrificial oxide layer, and photolithographically implant boron B on the front side to form a P-type reverse doped region.

[0017] Step 3: Photolithography is used to inject concentrated boron B into the front side, and after diffusion, a P+ diffusion region is formed. Photolithography is used to inject concentrated phosphorus P into the front side, and after diffusion, an N+ diffusion region is formed.

[0018] Step 4: Photolithography is performed on the front side to inject deep energy level impurities such as indium In, thallium TI, cobalt Co, or nickel Ni, and after activation, a deep energy level doping region is formed.

[0019] Step 5: remove the sacrificial oxide layer, deposit the dielectric layer, and form the cathode and anode contact hole areas by front photolithography.

[0020] Step 6: Sputter or evaporate metal on the front side, and after the alloy is completed, photolithography is performed on the front side to form an anode metal layer and a cathode metal layer.

[0021] By adopting the above technical solution, the introduction of the P-type reverse doping region makes the doping concentration of the P-type material only 0.1%~1% of the original, which can reduce the junction capacitance by 50~90%, and achieve low capacitance to meet the needs of high-speed interfaces. The introduction of the P-type reverse doping region can introduce the breakdown voltage and discharge current from the surface into the body. In addition, the introduction of the deep energy level doping region on the surface achieves higher resistance, further avoids the edge effect of the current here, avoids premature breakdown of the surface voltage and premature failure during current discharge. Through the reasonable design of this area, compared with the conventional structure, the flow capacity of the present invention is improved by 10-30%.

[0022] Furthermore, the crystal orientation of the P-type material in step 1 is <100> , resistivity is 50~200Ω.cm.

[0023] By adopting the above technical solution, using 100 crystal orientation, 50-200 ohm resistivity P-type material, compared with <110> Crystal orientation and <111> Crystal orientation, with the least surface defects, can achieve the lowest leakage current and the highest reliability. 50~200Ω.cm can ensure the polar capacitance while avoiding the surface leakage problem caused by high resistivity, improving the stability of the process and reducing the difficulty of stable mass production.

[0024] Furthermore, the thickness of the sacrificial oxide layer in step 2 is 300-1000 Å. The boron implantation dose of the P-type reverse doping region is 1E14-5E14 cm-2, the energy is 150-600 KeV, and the peak concentration is controlled at 0.6-1.5 um.

[0025] By adopting the above technical solution, the thickness of the sacrificial oxide layer is 300-1000Å, the boron implantation dose of the P-type reverse doping area is 1E14-5E14cm-2, the energy is 150-600KeV, and the peak concentration is controlled at 0.6~1.5um, so as to optimize the product performance, thereby reducing the breakdown voltage and improving the discharge capacity.

[0026] Furthermore, the boron implantation dose in step 3 is 1E15-3E15cm-2, and the energy is 40-80KeV. The phosphorus implantation dose in the N+ diffusion region is 3E15-8E15cm-2, and the energy is 80-120KeV. The advancement temperature condition is 950-1050°C, and the time is 30-90min, forming the P+ diffusion region and the N+ diffusion region.

[0027] By adopting the above technical solution, the junction depth can be controlled within a suitable range, and the optimal solution of discharge capacity and capacitance can be obtained, so as to achieve sufficient current discharge capacity and high reliability under low capacitance.

[0028] Furthermore, in step 4, deep energy level impurities such as indium In, thallium TI, cobalt Co, or nickel Ni are implanted by front lithography to form a deep energy level doping region after activation. The implantation dose is 1e14~5e14cm-2, and the junction depth is controlled at 0.2~0.4um.

[0029] By adopting the above technical solution, the junction depth is controlled at the surface, which can prevent the current from flowing through the area that is most likely to cause failure and leave a sufficient circuit path for the current in the body.

[0030] Furthermore, the dielectric layer in step 5 is tetraethoxysilane TEOS with a thickness of 8000-15000 Å. After the contact holes are photolithographically formed, a layer of TI / TIN is deposited.

[0031] By adopting the above technical solution, the failure caused by metal overheating can be effectively avoided while reducing the contact resistance.

[0032] Furthermore, the metal sputtered or evaporated on the front side in step 6 is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 3-5um, an alloy temperature of 320-410°C, and a time of 15-30min.

[0033] By adopting the above technical solution, the low temperature alloy temperature of 320-410℃ can avoid failure problems such as metal puncture caused by high temperature alloys, and improve reliability. The metal thickness of 3-5um can obtain the minimum metal resistance without increasing the process difficulty, improve the discharge capacity and reduce the parasitic resistance.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The present invention can introduce the P-type reverse doping region 102 under the conditions of unchanged chip area and chip processing procedures. The doping concentration of the P-type material 101 is only about 0.1% to 1% of the original, which can reduce the junction capacitance by 50 to 90%, achieving low capacitance to meet the application requirements of high-speed interfaces.

[0036] 2. The introduction of the P-type reverse doping region 102 of the present invention can introduce the breakdown voltage and discharge current from the surface into the body, making the current in the body more uniform and achieving a lower residual voltage. In addition, the introduction of the surface deep energy level doping region 105 achieves a higher resistance in the body, further avoiding the edge effect of the current here, avoiding premature breakdown of the surface voltage and premature failure during current discharge, avoiding abnormal IV characteristics, and improving reliability. Through the reasonable design of this area, the flow capacity of the present invention is increased by 10-30% compared with the conventional structure.

[0037] 3. The dielectric layer of the present invention is tetraethoxysilane TEOS with a thickness of 8000-15000Å. After photolithography of the contact hole, a layer of TI / TIN is deposited, which can effectively avoid metal overheating failure while reducing contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The figure is a cross-sectional structural diagram of a low-capacitance unidirectional ESD protection device of the present invention.

[0039] Figure 2 This is a cross-sectional diagram of a conventional unidirectional ESD protection device.

[0040] Figure 3 It is the IV characteristic curve and equivalent circuit diagram corresponding to the traditional unidirectional ESD protection device.

[0041] Figure 4 This is the IV characteristic curve of the present invention.

[0042] Figure 5 It is a schematic diagram of the process step 1 of the present invention.

[0043] Figure 6 It is a schematic diagram of process step 2 of the present invention.

[0044] Figure 7 It is a schematic diagram of process step three of the present invention.

[0045] Figure 8 Schematic diagram of process step four of the present invention.

[0046] Fig. 9 It is a schematic diagram of process step five of the present invention.

[0047] Fig.10 Schematic diagram of process step six of the present invention.

[0048] Fig.11 It is a bidirectional structure to which the present invention can be applied.

[0049] Fig.12 It is another bidirectional structure to which the present invention can be applied.

[0050] In the figure, 101. P-type material, 102. P-type reverse doped region, 103. P+ diffusion region, 104. N+ diffusion region, 105. deep energy level doped region, 106. surface dielectric layer, 107. anode metal layer, 108. cathode metal layer, 109. sacrificial oxide layer, 110. N+ substrate material, 111. isolation groove, 112. oxide layer, 113. surface passivation layer. DETAILED DESCRIPTION

[0051] The present invention is further described in detail below in conjunction with the accompanying drawings and implementation modes. A detailed description is given by taking a voltage level of 5.0V as an example.

[0052] like Figure 1 As shown, a low capacitance unidirectional ESD protection device includes: P-type material 101, P+ diffusion region 103, anode metal layer 107, cathode metal layer 108; P-type reverse doping region 102, P+ diffusion region 103, N+ diffusion region 104 are arranged on the front of P-type material 101; deep energy level impurity doping region 105 is arranged on N+ diffusion region 104 by photolithography; surface dielectric layer 106 is arranged between two adjacent P+ diffusion regions 103 and between two adjacent N+ diffusion regions 104. Anode metal layer 107 and cathode metal layer 108 are arranged on dielectric layer 106 respectively. Its IV characteristic curve is shown as follows Figure 4 As shown, the solid line is the IV characteristic curve of the present application, and the dotted line is the IV characteristic curve of the conventional structure. As can be seen from the figure, the base voltage of the present application is lower. When the electrostatic pulse comes, the device of the present application can be turned on at a lower voltage and discharge energy, which can protect the internal circuit more timely and effectively. When the anode metal layer 107 is connected to a high potential and the cathode metal layer 108 is connected to a low potential, the characteristic is manifested as the forward conduction characteristic of the diode. When the cathode metal layer 108 is connected to a high potential and the anode metal layer 107 is connected to a low potential, the characteristic is manifested as the shallow retrace breakdown characteristic of the triode.

[0053] The present application can introduce a P-type reverse doping region 102 under the condition that the chip area and chip processing procedures remain unchanged, so that the doping concentration of the P-type material 101 is only 0.1%~1% of the original, which can reduce the junction capacitance by 50~90%, and achieve low capacitance to meet the needs of high-speed interfaces. The introduction of the P-type reverse doping region 102 can introduce the breakdown voltage and the discharge current from the surface into the body. In addition, the introduction of the surface deep energy level doping region 105 achieves higher resistance, further avoids the edge effect of the current here, and avoids premature breakdown of the surface voltage and premature failure during current discharge. Through the reasonable design of this area, compared with the conventional structure, the flow capacity of the present invention is improved by 10-30%.

[0054] A method for manufacturing a low-capacitance unidirectional ESD protection device comprises the following steps:

[0055] Step 1: Figure 5 As shown, firstly, a P-type material 101 is prepared, and the crystal orientation of the P-type material 101 is <100> , resistivity is 50~200Ω.cm.

[0056] Step 2: Figure 6As shown, a sacrificial oxide layer 109 is grown with a thickness of 300-1000Å, and boron B is implanted on the front side by photolithography to form a P-type reverse doping region 102. The boron implantation dose of the P-type reverse doping region 102 is 1E14-5E14cm-2, the energy is 150-600KeV, and the peak concentration is 0.5~1um.

[0057] Step 3: Figure 7 As shown, concentrated boron B is injected by front lithography, and P+ diffusion region 103 is formed after diffusion. Concentrated phosphorus P is injected by front lithography, and N+ diffusion region 104 is formed after diffusion. The boron injection dose of front lithography is 1E15-3E15cm-2, and the energy is 40-80KeV. The phosphorus injection dose of front lithography N+ diffusion region is 3E15-8E15cm-2, and the energy is 80-120KeV. The temperature condition of advancement is 950-1050℃, and the time is 30-90min, forming P+ diffusion region 103 and N+ diffusion region 104.

[0058] Step 4: Figure 8 As shown, deep energy level impurities Indium In, Thallium Ti, Cobalt Co, or Nickel Ni are implanted by front lithography, and the implantation dose is 1e14~5e14cm-2, and the junction depth is controlled at 0.2~0.4um. After activation, a deep energy level doping region 105 is formed.

[0059] Step 5: Fig. 9 As shown, the sacrificial oxide layer is removed, and the dielectric layer 106 is deposited as tetraethoxysilane TEOS with a thickness of 8000-15000 Å. After photolithography of the cathode and anode contact holes, a layer of TI / TIN is deposited. While reducing the contact resistance, it can effectively avoid the failure of metal overheating.

[0060] Step 6: Fig.10 As shown, the metal sputtered or evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 3-5um. The temperature of the alloy is 320-410°C, and the time is 15-30min. After the alloy is completed, the front side is photolithographically formed into an anode metal layer 107 and a cathode metal layer 108.

[0061] like Fig.11 As shown, a bidirectional structure of the present application is obtained by right-side symmetry and series connection. The spacing between the P+ diffusion regions 103 on both sides is >100um to prevent the lateral parasitic device from being turned on.

[0062] like Fig.12 As shown in FIG. , another bidirectional structure of the present invention is shown. Fig.10On the basis of the bidirectional structure, the P-type material 101 is replaced with a silicon-on-insulator SOI, and the silicon-on-insulator includes an N+ substrate material 110, an isolation groove 111, an oxide layer 112 and a P-type material 101. The N+ substrate material 110 is provided with the P-type material 101 through the oxide layer 112, and the isolation grooves 111 are arranged on the N+ substrate material 110, the oxide layer 112, and the P-type material 101. After the material is replaced, the use of this silicon-on-insulator structure can effectively prevent the parasitic SCR from being turned on between the structures on both sides, and its area is reduced by 30-50% compared with similar products without this isolation structure.

[0063] The example of the present invention is a unidirectional structure. By changing the layout, it can realize functions such as multi-way unidirectional, multi-way bidirectional, and one-way bidirectional, all of which are within the scope of the implementation of the present invention.

[0064] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to preferred examples, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A low capacitance unidirectional ESD protection device, comprising: P-type material (101), P-type reverse doping region (102), P+ diffusion region (103), N+ diffusion region (104), deep energy level impurity doping region (105), dielectric layer (106), anode metal layer (107), cathode metal layer (108); characterized in that: the P-type reverse doping region (102), P+ diffusion region (103), and N+ diffusion region (104) are arranged on the front of the P-type material (101); a dielectric layer (106) is arranged on the P-type material (101); anode metal layers (107) are arranged on the dielectric layer (106) in sequence. ), a cathode metal layer (108); below the anode metal layer (107), from left to right, are a P+ diffusion region (103) and an N+ diffusion region (104); below the cathode metal layer (108), is an N+ diffusion region (104); a deep energy level impurity doping region (105) is provided above each of the two N+ diffusion regions (104); the P-type reverse doping region (102) is located between the two N+ diffusion regions (104), and the deep energy level impurity doping region (105) is located at an upper corner of the N+ diffusion region (104) on a side close to the P-type reverse doping region (102); The low-capacitance unidirectional ESD protection device is bilaterally symmetrical and is connected in series to form a bidirectional structure; wherein the spacing between the P+ diffusion regions (103) on both sides is greater than 100 um.

2. A low capacitance unidirectional ESD protection device according to claim 1, characterized in that: The P-type material (101) is replaced with a silicon-on-insulator (SOI), wherein the silicon-on-insulator comprises an N+ substrate material (110), an isolation groove (111), an oxide layer (112) and the P-type material (101); the N+ substrate material (110) is provided with the P-type material (101) through the oxide layer (112), and the isolation grooves (111) are spaced apart on the N+ substrate material (110), the oxide layer (112) and the P-type material (101).

3. A method for manufacturing a low-capacitance unidirectional ESD protection device, characterized in that: The following steps are involved: Step 1: preparing a P-type material (101); Step 2: growing a sacrificial oxide layer (109), and implanting boron B on the front side by photolithography to form a P-type reverse doped region (102); Step 3: Photolithography is performed on the front side to inject concentrated boron B, and after diffusion, a P+ diffusion region (103) is formed; photolithography is performed on the front side to inject concentrated phosphorus P, and after diffusion, an N+ diffusion region (104) is formed; Step 4: Photolithography is performed on the front side to inject deep energy level impurities such as indium In, thallium TI, cobalt Co, or nickel Ni, and after activation, a deep energy level doping region (105) is formed; Step 5: remove the sacrificial oxide layer (109), deposit a dielectric layer (106), and form cathode and anode contact hole regions by front photolithography; Step 6: Sputter or evaporate metal on the front side, and after the alloy is completed, photolithography is performed on the front side to form an anode metal layer (107) and a cathode metal layer (108).

4. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: The crystal orientation of the P-type material (101) in step 1 is <100> , the resistivity is 50~200Ω.cm.

5. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: The thickness of the sacrificial oxide layer (109) in step 2 is 300-1000Å; the boron implantation dose of the P-type reverse doping region (102) is 1E14-5E14cm -2 , energy is 150-600KeV, and peak concentration is controlled at 0.6~1.5um.

6. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: The boron implantation dose in step 3 is 1E15-3E15cm -2 , energy is 40-80KeV; the phosphorus implantation dose in the N+ diffusion region (104) is 3E15-8E15cm -2 , energy is 80-120KeV; the advancement temperature condition is 950-1050℃, the time is 30-90min, and a P+ diffusion region (103) and an N+ diffusion region (104) are formed.

7. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: In step 4, deep energy level impurities such as indium In, thallium TI, cobalt Co, or nickel Ni are implanted on the front side by photolithography to form a deep energy level doping region (105) after activation. The implantation dose is 1e14-5e14cm -2 , the junction depth is controlled at 0.2~0.4um.

8. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: The dielectric layer (106) in step five is tetraethoxysilane TEOS with a thickness of 8000-15000Å. After photolithography of the contact hole, a layer of TI / TIN is deposited. This can effectively avoid metal overheating failure while reducing contact resistance.

9. The method for manufacturing a low-capacitance unidirectional ESD protection device according to claim 3, characterized in that: The metal sputtered or evaporated on the front side in step six is ​​aluminum or aluminum copper or aluminum silicon copper, with a thickness of 3-5um; the temperature of the alloy is 320-410°C, and the time is 15-30min.

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