A HVIC three-phase drive integrated circuit

Abstract

The present invention relates to the field of electronic circuit technology, and specifically discloses an HVIC three-phase driver integrated circuit, comprising a PCB circuit board and a plurality of freewheeling FWD chip tubes, a plurality of IGBT transistors, and a plurality of lead terminals arranged on the PCB circuit board. The PCB circuit board is also provided with a first three-channel HVIC circuit and a second three-channel HVIC circuit, the IGBT transistors being electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit, and the second three-channel HVIC circuit, respectively, and the lead terminals being electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit, and the second three-channel HVIC circuit, respectively. The present invention provides a design of a three-phase driver integrated module by providing a first three-channel HVIC circuit and a second three-channel HVIC circuit, two three-channel HVIC solutions, and effectively solving the complex wiring requirements of a miniaturized main control board, allowing for more flexible design and matching of the output end of the intelligent IPM, thereby improving the reliability and adaptability of the product.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an HVIC three-phase drive integrated circuit. Background Art

[0002] A high-voltage integrated circuit (HVIC) converts MCU signals into signals that drive IGBTs. An HVIC integrates PMOS transistors, NMOS transistors, triodes, diodes, voltage regulators, resistors, and capacitors to form a Schmitt diode, low-voltage level switches, high-voltage level switches, pulse generators, delay circuits, filter circuits, overcurrent protection, thermal protection, undervoltage protection, and bootstrap circuits. The HVIC receives control signals from the MCU to drive the subsequent IGBTs or MOS transistors. It also transmits system status detection signals back to the MCU.

[0003] Traditional HVIC has half-bridge and full-bridge drive types. Compared with the driving solutions in the field of highly integrated IPM intelligent power modules, the design methods of these two solutions are currently limited in universality. With the trend of miniaturization and integration of intelligent power modules, the traditional half-bridge and full-bridge methods cannot fully meet the development direction, such as Figure 1-2 As shown in the figure, the IPM module wiring design is not convenient for routing design, which increases the difficulty of routing. The routing is too long, resulting in poor anti-interference ability and reduced product reliability. If the application design is not reasonable, it is easy to cause false triggering, affecting the user experience. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that, in response to the above-mentioned defects of the prior art, an HVIC three-phase drive integrated circuit is provided. By setting a first three-channel HVIC circuit and a second three-channel HVIC circuit, that is, adopting an HVIC with "1 upper bridge and 2 lower bridges" + an HVIC with "2 upper bridges and 1 lower bridge", the design of a three-phase drive integrated module is composed of two three-channel HVIC solutions, which effectively solves the complex wiring requirements of the miniaturized main control board, allows the output end of the intelligent IPM to be more freely designed and matched, and can improve the reliability and adaptability of the product.

[0005] In order to solve the above technical problems, the technical solution of the present invention is:

[0006] A HVIC three-phase drive integrated circuit includes a PCB circuit board and a plurality of freewheeling FWD chip tubes, a plurality of IGBT transistors and a plurality of lead terminals arranged on the PCB circuit board. The PCB circuit board is also provided with a first three-channel HVIC circuit and a second three-channel HVIC circuit. The IGBT transistors are electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit, respectively. The lead terminals are electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit, respectively.

[0007] Preferably, the first three-channel HVIC circuit includes a dual-channel high-side drive circuit, a single-channel low-side drive circuit and a first interlock circuit 15, and the first interlock circuit 15 is electrically connected to the dual-channel high-side drive circuit and the single-channel low-side drive circuit respectively.

[0008] Preferably, the second three-channel HVIC circuit includes a single-channel high-side driving circuit, a dual-channel low-side driving circuit and a second interlock circuit 16, and the second interlock circuit 16 is electrically connected to the single-channel high-side driving circuit and the dual-channel low-side driving circuit respectively.

[0009] Preferably, the dual-channel high-side drive circuit includes a Schmitt trigger 1, a low-pass filter 2, a VREG generating circuit 3, a low-voltage-high-voltage transition circuit 4, a high-voltage area output circuit 5, a Schmitt trigger 6, a low-pass filter 7, a VREG generating circuit 8, a low-voltage-high-voltage transition circuit 9 and a high-voltage area output circuit 10, the low-pass filter 2 is electrically connected to the Schmitt trigger 1 and the VREG generating circuit 3 respectively, the VREG generating circuit 3 is electrically connected to the low-voltage-high-voltage transition circuit 4 via a pulse generating circuit, and the low-voltage-high-voltage transition circuit 4 is electrically connected to the high-voltage area output circuit 5; the low-pass filter 7 is electrically connected to the Schmitt trigger 6 and the VREG generating circuit 8 respectively, the first interlock circuit 15 is electrically connected to the VREG generating circuit 8 and the low-voltage-high-voltage transition circuit 9 respectively, and the low-voltage-high-voltage transition circuit 9 is electrically connected to the high-voltage area output circuit 10.

[0010] Preferably, the single-channel low-side drive circuit includes a Schmitt trigger 11, a low-pass filter 12, a VREG generating circuit 13 and a low-voltage zone output circuit 14, the low-pass filter 12 is electrically connected to the Schmitt trigger 11 and the VREG generating circuit 13, respectively, and the first interlock circuit 15 is electrically connected to the VREG generating circuit 13 and the low-voltage zone output circuit 14, respectively.

[0011] Preferably, the single-channel high-side drive circuit includes a Schmitt trigger 21, a low-pass filter 22, a VREG generating circuit 23, a low-voltage-high-voltage transition circuit 24 and a high-voltage area output circuit 25, the low-pass filter 22 is electrically connected to the Schmitt trigger 21 and the VREG generating circuit 23, respectively, the second interlock circuit 16 is electrically connected to the VREG generating circuit 23 and the low-voltage-high-voltage transition circuit 24, respectively, and the low-voltage-high-voltage transition circuit 24 is electrically connected to the high-voltage area output circuit 25.

[0012] Preferably, the dual-channel low-side drive circuit includes a Schmitt trigger 26, a low-pass filter 27, a VREG generating circuit 28, a low-voltage area output circuit 29, a Schmitt trigger 31, a low-pass filter 32, a VREG generating circuit 33 and a low-voltage area output circuit 34, the low-pass filter 27 is electrically connected to the Schmitt trigger 26 and the VREG generating circuit 28, respectively, the second interlock circuit 16 is electrically connected to the VREG generating circuit 28 and the low-voltage area output circuit 29, respectively, the low-pass filter 32 is electrically connected to the Schmitt trigger 31 and the VREG generating circuit 33, and the VREG generating circuit 33 is electrically connected to the low-voltage area output circuit 34.

[0013] By adopting the above technical solution, the present invention provides an HVIC three-phase driver integrated circuit, which has the following beneficial effects: a first three-channel HVIC circuit and a second three-channel HVIC circuit are further provided on the PCB circuit board in the HVIC three-phase driver integrated circuit, the IGBT transistors are electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit respectively, and the lead terminals are electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit respectively, and a three-channel HVIC is designed, namely " The HVIC with "one upper bridge and two lower bridges" + the HVIC with "two upper bridges and one lower bridge" adopts the driving mode of two HVICs for integrated module drive design. Compared with the 6-channel HVIC, it effectively solves the complex wiring requirements of miniaturized main control boards under the condition of similar cost and unchanged process. It allows more freedom in the design and matching of the output end of the intelligent IPM, which can improve the reliability and adaptability of the product, avoid the product quality risks caused by the wiring difficulties of the HVIC solution, and provide users with more choices in application solutions, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The basic topology diagram of the existing three-phase full-bridge HVIC is shown below;

[0015] Figure 2 The wiring topology diagram of the existing three-phase full-bridge HVIC is shown below;

[0016] Figure 3 1 is a basic topological structure diagram of the first three-channel HVIC circuit in the present invention;

[0017] Figure 4 1 is a basic topological structure diagram of the second three-channel HVIC circuit in the present invention;

[0018] Figure 5 It is a wiring topology diagram of the present invention;

[0019] Figure 6 is a circuit schematic diagram of the first three-channel HVIC circuit in the present invention;

[0020] Figure 7 is a circuit schematic diagram of the second three-channel HVIC circuit in the present invention;

[0021] In the figure, 01-PCB circuit board, 02-freewheeling FWD chip tube, 03-IGBT transistor, 04-lead terminal, 05-first three-channel HVIC circuit, 06-second three-channel HVIC circuit. DETAILED DESCRIPTION

[0022] The following is a further description of specific embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is intended to facilitate understanding of the present invention and does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0023] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0025] like Figure 3-Figure 7 As shown, the HVIC three-phase drive integrated circuit includes a PCB circuit board 01 and several freewheeling FWD chip tubes 02, several IGBT transistors 03 and several lead terminals 04 arranged on the PCB circuit board 01. The PCB circuit board 01 is also provided with a first three-channel HVIC circuit 05 and a second three-channel HVIC circuit 06. The IGBT transistor 03 is electrically connected to the freewheeling FWD chip tube 02, the first three-channel HVIC circuit 05 and the second three-channel HVIC circuit 06 respectively. The lead terminal 04 is electrically connected to the freewheeling FWD chip tube 02, the first three-channel HVIC circuit 05 and the second three-channel HVIC circuit 06 respectively. It can be understood that the freewheeling FWD chip tube 02 and the IGBT transistor 03 are connected by jumpers to form a group of single-phase upper and lower bridge arms, with a total of six groups; the freewheeling FWD chip tube 02 and the IGBT transistor 03 are directly soldered on the PCB circuit 01 through the tin paste solder welding process to form a circuit loop output; the first three-channel HVIC circuit 05 and the second three-channel HVIC circuit 06 are the driving HVIC chip tubes of the upper and lower bridge arm transistors, and the gates of each bridge arm are connected by jumpers to control the drive; the lead terminals 04 are distributed on the upper and lower sides of the PCB circuit board 01, which are electrically connected to the peripheral applications to realize the solution drive.

[0026] Specifically, the first three-channel HVIC circuit 05 includes a dual-channel high-side drive circuit, a single-channel low-side drive circuit and a first interlock circuit 15, and the first interlock circuit 15 is electrically connected to the dual-channel high-side drive circuit and the single-channel low-side drive circuit respectively; the second three-channel HVIC circuit includes a single-channel high-side drive circuit, a dual-channel low-side drive circuit and a second interlock circuit 16, and the second interlock circuit 16 is electrically connected to the single-channel high-side drive circuit and the dual-channel low-side drive circuit respectively; the dual-channel high-side drive circuit includes a Schmitt trigger 1, a low-pass filter 2, a VREG generating circuit 3, a low-voltage-high-voltage transition circuit 4, a high-voltage area output circuit 5, a Schmitt trigger 6, a low-pass filter 7, a VREG generating circuit EG generating circuit 8, low voltage-high voltage transition circuit 9 and high voltage area output circuit 10, the low-pass filter 2 is electrically connected to the Schmitt trigger 1 and the VREG generating circuit 3 respectively, the VREG generating circuit 3 is electrically connected to the low voltage-high voltage transition circuit 4 via the pulse generating circuit, and the low voltage-high voltage transition circuit 4 is electrically connected to the high voltage area output circuit 5; the low-pass filter 7 is electrically connected to the Schmitt trigger 6 and the VREG generating circuit 8 respectively, the first interlock circuit 15 is electrically connected to the VREG generating circuit 8 and the low voltage-high voltage transition circuit 9 respectively, and the low voltage-high voltage transition circuit 9 is electrically connected to the high voltage area output circuit 10; the single-channel low-side drive circuit includes a Schmitt trigger 11, a low-pass filter The single-channel high-side drive circuit includes a Schmitt trigger 21, a low-pass filter 22, a VREG generating circuit 23, a low-voltage-high-voltage transition circuit 24 and a high-voltage area output circuit 25, the low-pass filter 22 is electrically connected to the Schmitt trigger 21 and the VREG generating circuit 23, the second interlock circuit 16 is electrically connected to the VREG generating circuit 23 and the low-voltage-high-voltage transition circuit 24, the low-pass filter 22 is electrically connected to the Schmitt trigger 21 and the VREG generating circuit 23, the second interlock circuit 16 is electrically connected to the VREG generating circuit 23 and the low-voltage-high-voltage transition circuit 24, the low-voltage-high-voltage transition circuit 24 is electrically connected to the low-voltage-high-voltage transition circuit 24. Circuit 24 is electrically connected to the high-voltage area output circuit 25; the dual-channel low-side drive circuit includes a Schmitt trigger 26, a low-pass filter 27, a VREG generating circuit 28, a low-voltage area output circuit 29, a Schmitt trigger 31, a low-pass filter 32, a VREG generating circuit 33 and a low-voltage area output circuit 34, the low-pass filter 27 is electrically connected to the Schmitt trigger 26 and the VREG generating circuit 28 respectively, the second interlock circuit 16 is electrically connected to the VREG generating circuit 28 and the low-voltage area output circuit 29 respectively, the low-pass filter 32 is electrically connected to the Schmitt trigger 31 and the VREG generating circuit 33 respectively, and the VREG generating circuit 33 is electrically connected to the low-voltage area output circuit 34.

[0027] It can be understood that the first three-channel HVIC circuit 05 is a PMOS tube, an NMOS tube, a triode, a diode, a voltage regulator, a resistor, and a capacitor integrated together to form a power supply circuit, a power supply undervoltage protection circuit, two high-voltage side drive circuits (bootstrap circuit, high-voltage side undervoltage protection circuit), one low-voltage side drive circuit, an enable circuit, an overcurrent protection circuit, an overheating protection circuit and an overvoltage protection circuit, etc.; the second three-channel HVIC circuit 06 is a PMOS tube, an NMOS tube, a triode, a diode, a voltage regulator, a resistor, and a capacitor integrated together to form a power supply circuit, a power supply undervoltage protection circuit, one high-voltage side drive circuit (bootstrap circuit, high-voltage side undervoltage protection circuit), two low-voltage side drive circuits, an enable circuit, an overcurrent protection circuit, an overheating protection circuit and an overvoltage protection circuit, etc., the interlock circuit is connected to the high-side drive circuit and the low-side drive circuit, and the interlock circuit is connected to the high-side drive circuit and the low-side drive circuit.

[0028] It can be understood that both LIN and HIN need to let the input signals pass through the Schmitt trigger first to filter the level noise of the input circuit. The maximum value of logic 0 is 0.8V, and the minimum value of logic 1 is 2.9V. The low-pass filter is used to filter the high-frequency noise of the input circuit. At the same time, in order to give VB enough charging time and avoid the driven back-end circuit working in a state of insufficient VB voltage (which will reduce the efficiency of the back-end circuit), it is necessary to limit the frequency range of the input signal and filter out signals with excessively high frequencies. Generally, signals above 600KHz to 700KHz should be filtered out. VREG generation circuit: The power supply voltage TYPE value of the driver IC is generally 15V. To receive the 5V logic 1 signal of the MCU, etc., a 7V to 8V VREG must be generated to generate a 7.2V VREG signal with good temperature characteristics.

[0029] As you can understand, the interlock circuit is necessary to prevent the HO and LO pins from being simultaneously high when the HIN and LIN inputs of the HVIC are simultaneously high. When HIN and LIN are simultaneously high, the HO and LO pins are simultaneously set to low. (If HO and LO are simultaneously high, subsequent components such as the IGBT will be turned on at the same time, causing a large current to flow and damaging the IGBT and other subsequent components.)

[0030] When both inputs are at logic 1, both outputs are at logic 0. In other cases, the input and output have the same logic:

[0031]

[0032]

[0033] Undervoltage protection circuit: Whether it's VDD or the bootstrap VB, when the voltage drops too low, the HVIC shuts down (keeping the output at logic 0) to protect subsequent circuitry. In the low-voltage range, a UVD filter detects the VDD level. In the high-voltage range, a UVD filter detects the VB level. When VDD (the voltage of VB relative to VS) drops below 10V, the output remains at logic 0. When VDD rises above 10.7V, the output remains at logic 1. This creates a 0.7V difference. This ensures that the output only reaches a high level after confirming that the power supply voltage is sufficiently high. To account for power supply noise, a delay circuit should be added at the end of the circuit to prevent malfunctioning of the output if the power supply voltage drops momentarily due to power supply noise. The fault logic control circuit receives fault signals from various functional circuits and, based on these signals, generates a fault signal from the FO. Depending on the severity of the fault, it disables the corresponding function or shuts down all HVIC functions, protecting the HVIC and the entire application circuit. A fault signal of 1 for each of the undervoltage protection, overvoltage protection, current protection, overtemperature protection, and EN enable functions indicates normal operation. When the signal is 0, the fault logic control circuit outputs a fault signal from the FO, causing the HVIC to enter the corresponding functional protection mode, shutting down the six PWM waveforms and halting operation. The pulse selection circuit consists of logic circuits, including two triple-AND gates, one NOT gate, and two OR gates. The pulse generation circuit (PULSE GEN) includes both a ONESHOT and DOUBLEPLUSE pulse circuits. The AND gate performs a logical multiplication operation and has two or more inputs and one output (typical circuits have only one output, while ECL circuits have two outputs). The output of this circuit is high (logic "1") only when all input terminals are high (logic "1"). Otherwise, the output is low (logic "0"). The mathematical logic expression of the three-input AND gate is: Y = ABC, and the corresponding truth table is as follows:

[0034]

[0035] The present invention can effectively solve the complex wiring requirements of the miniaturized main control board without increasing the cost and keeping the process unchanged, so that the output end of the intelligent IPM can be designed and matched more freely, thereby improving the reliability and adaptability of the product, avoiding some product quality risks caused by wiring difficulties due to the HVIC solution, and providing users with more choices in application solutions, thereby improving the user experience.

[0036] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It is apparent to those skilled in the art that various changes, modifications, substitutions, and variations to these embodiments may be made without departing from the principles and spirit of the present invention, and these changes and modifications still fall within the scope of protection of the present invention.

Claims

1. An HVIC three-phase driver integrated circuit, comprising a PCB circuit board and a plurality of freewheeling FWD chip tubes, a plurality of IGBT transistors and a plurality of lead terminals arranged on the PCB circuit board, characterized in that: The PCB circuit board is also provided with a first three-channel HVIC circuit and a second three-channel HVIC circuit, the IGBT transistor is electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit respectively, and the lead terminal is electrically connected to the freewheeling FWD chip tube, the first three-channel HVIC circuit and the second three-channel HVIC circuit respectively; the first three-channel HVIC circuit includes a dual-channel high-side drive circuit, a single-channel low-side drive circuit and a first interlock circuit (15), and the first interlock circuit (15) is electrically connected to the dual-channel high-side drive circuit and the single-channel low-side drive circuit respectively.

2. The HVIC three-phase driver integrated circuit according to claim 1, wherein: The second three-channel HVIC circuit includes a single-channel high-side driving circuit, a dual-channel low-side driving circuit and a second interlock circuit (16), and the second interlock circuit (16) is electrically connected to the single-channel high-side driving circuit and the dual-channel low-side driving circuit respectively.

3. The HVIC three-phase driver integrated circuit according to claim 1, wherein: The dual-channel high-side driving circuit comprises a first Schmitt trigger (1), a first low-pass filter (2), a first VREG generating circuit (3), a first low-voltage-high-voltage transition circuit (4), a first high-voltage region output circuit (5), a second Schmitt trigger (6), a second low-pass filter (7), a second VREG generating circuit (8), a second low-voltage-high-voltage transition circuit (9) and a second high-voltage region output circuit (10), wherein the first low-pass filter (2) is electrically connected to the first Schmitt trigger (1) and the first VREG generating circuit (3), respectively, and the first VREG generating circuit (8) is electrically connected to the first Schmitt trigger (1) and the first VREG generating circuit (3). The generating circuit (3) is electrically connected to the first low-voltage-high-voltage transition circuit (4) via the pulse generating circuit, and the first low-voltage-high-voltage transition circuit (4) is electrically connected to the first high-voltage area output circuit (5); the second low-pass filter (7) is electrically connected to the second Schmitt trigger (6) and the second VREG generating circuit (8), respectively; the first interlocking circuit (15) is electrically connected to the second VREG generating circuit (8) and the second low-voltage-high-voltage transition circuit (9), respectively; the second low-voltage-high-voltage transition circuit (9) is electrically connected to the second high-voltage area output circuit (10).

4. The HVIC three-phase driver integrated circuit according to claim 1, wherein: The single-channel low-side driving circuit comprises a third Schmitt trigger (11), a third low-pass filter (12), a third VREG generating circuit (13) and a first low-voltage region output circuit (14); the third low-pass filter (12) is electrically connected to the third Schmitt trigger (11) and the third VREG generating circuit (13), respectively; and the first interlocking circuit (15) is electrically connected to the third VREG generating circuit (13) and the first low-voltage region output circuit (14), respectively.

5. The HVIC three-phase driver integrated circuit according to claim 2, wherein: The single-channel high-side drive circuit includes a fourth Schmitt trigger (21), a fourth low-pass filter (22), a fourth VREG generating circuit (23), a third low-voltage-high-voltage transition circuit (24) and a third high-voltage area output circuit (25), wherein the fourth low-pass filter (22) is electrically connected to the fourth Schmitt trigger (21) and the fourth VREG generating circuit (23), respectively; the second interlock circuit (16) is electrically connected to the fourth VREG generating circuit (23) and the third low-voltage-high-voltage transition circuit (24), respectively; and the third low-voltage-high-voltage transition circuit (24) is electrically connected to the third high-voltage area output circuit (25).

6. The HVIC three-phase driver integrated circuit according to claim 2, wherein: The dual-channel low-side driving circuit includes a fifth Schmitt trigger (26), a fifth low-pass filter (27), a fifth VREG generating circuit (28), a second low-voltage zone output circuit (29), a sixth Schmitt trigger (31), a sixth low-pass filter (32), a sixth VREG generating circuit (33) and a third low-voltage zone output circuit (34); the fifth low-pass filter (27) is electrically connected to the fifth Schmitt trigger (26) and the fifth VREG generating circuit (28), respectively; the second interlock circuit (16) is electrically connected to the fifth VREG generating circuit (28) and the second low-voltage zone output circuit (29), respectively; the sixth low-pass filter (32) is electrically connected to the sixth Schmitt trigger (31) and the sixth VREG generating circuit (33), respectively; and the sixth VREG generating circuit (33) is electrically connected to the third low-voltage zone output circuit (34).

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