Circuit board pin defect recognition method based on feature self-learning

Abstract

The present application discloses a circuit board pin defect recognition method based on feature self-learning, including: obtaining a standard circuit board AOI color image and a corresponding configuration file; establishing a solder joint position model and a standard solder feature matrix X of a standard circuit board; obtaining a chip sub-image of a chip in a circuit board to be tested; extracting a corresponding sub-solder joint image from each chip sub-image based on the solder joint position model, calculating the solder height value of each pixel in each sub-solder joint image, and forming a solder feature matrix Y of the corresponding solder joint; calculating the normalized geometric intersection coefficient γ of the solder feature matrix Y and the corresponding standard solder feature matrix X, and judging whether the solder joints are defective one by one according to the geometric intersection coefficient threshold. The present invention can effectively reduce the missed detection rate, improve efficiency and accuracy, and reduce the workload of manual defect detection.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit board detection, and relates to a circuit board pin defect recognition method based on feature self-learning. Background Art

[0002] Circuit boards can make circuits miniaturized and intuitive, and play an important role in the mass production of fixed circuits and in optimizing the layout of electrical appliances.

[0003] Most domestic circuit board manufacturers use manual inspection with a magnifying glass or projector to inspect circuit board defects. Due to the high labor intensity of manual inspection, the eyes are easily fatigued and the missed inspection rate is very high. Moreover, as electronic products develop towards miniaturization and digitalization, circuit boards are also developing towards high density and high precision, which is basically impossible to achieve using manual inspection methods. It is completely impossible to inspect higher density and precision circuit boards (0.12-0.10mm). The backwardness of detection methods has resulted in the current domestic multi-layer board (8-12 layers) product qualification rate of only 50-60%.

[0004] In addition, the circuit board production base also uses AOI equipment to detect circuit board defects, but there are still many defects. The more serious defect is missed detection, that is, there are defects but they are not detected. There is a probability of >60% that AOI equipment cannot detect defects of solder joint type. That is to say, assuming there are 100 defects in the circuit board, 60 of them will not be found by AOI and will be released. Only the abnormalities detected by AOI are manually checked, and such undetectable situations are no longer checked. This defect can only be discovered through electrical measurement in the future, and then fed back to the AOI assembly line. The severity of false alarms is low, but it is also frequent. Most of them are caused by fonts and can be eliminated manually. Summary of the invention

[0005] In order to address the deficiencies in the prior art, the present application provides a circuit board pin defect identification method based on feature self-learning.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] The circuit board pin defect recognition method based on feature self-learning includes the following steps:

[0008] Step 1: Obtain the standard circuit board AOI color image and corresponding configuration file corresponding to the circuit board to be tested for feature self-learning, including the chip model and chip position on the circuit board;

[0009] Step 2: Establish a standard solder joint model of the chip in the AOI color image of the standard circuit board, including the solder joint position model and the standard solder feature matrix X;

[0010] Step 3: Obtain the AOI color image of the circuit board to be tested, and perform SIFT image comparison between it and the AOI color image of the standard circuit board to obtain the chip sub-image of the chip in the circuit board to be tested. Each chip sub-image contains a single chip and all its corresponding solder joints.

[0011] Step 4: Based on the solder joint position model in step 2, extract the corresponding sub-solder joint image from each chip sub-image, each sub-solder joint image includes a single solder joint, calculate the solder height value of each pixel in each sub-solder joint image, and form the solder feature matrix Y of the corresponding solder joint;

[0012] Step 5: Calculate the normalized geometric intersection coefficient γ between the solder feature matrix Y and the corresponding standard solder feature matrix X, and determine whether the solder joints are defective one by one according to the geometric intersection coefficient threshold.

[0013] The present invention further includes the following preferred embodiments:

[0014] Preferably, step 2 specifically includes:

[0015] Step 2.1: Expand the chip area with the center of the chip as the center to obtain the chip matrix of the corresponding phase model;

[0016] Step 2.2: Search for solder joints in the area expanded in step 2.1. When searching for solder joints, obtain the ROI solder joint region of interest based on color information and extract the solder joint matrix, thereby obtaining the solder joint position model of the chip model;

[0017] Step 2.3: Obtain all solder joint matrices in the expanded area, which are all defect-free solder joints, and calculate the solder height value of each pixel in the solder joint matrix;

[0018] Step 2.4: Calculate the average solder height value of each pixel in the same solder joint matrix to form the standard solder feature matrix X of the solder joint.

[0019] Preferably, in step 2.1, the rectangular area where the chip is located is expanded 1.5 times with the center of the chip as the center to obtain a chip matrix.

[0020] Preferably, in step 2.2, the RGB image is converted into an HSV image, the blue part in the HSV image is extracted as the solder point matrix, and then the position of the solder point matrix relative to the chip matrix and the solder point bounding box are obtained, and saved as the solder point position model of the chip of this model; the solder point bounding box is a rectangular frame containing the solder points and the chip.

[0021] Preferably, in step 2.2, the extraction range is: H: (100, 124), S: (43, 255), V: (46, 255).

[0022] Preferably, in step 2.3, the calculation formula for the solder height value is:

[0023] height=BG / 5.-R / 3.0

[0024] Among them, B, G, and R are the B component value, G component value, and R component value of the corresponding pixel RGB respectively.

[0025] Preferably, the SIFT image in step 3 is relatively accurate, specifically including:

[0026] (1) Calculate the SIFT feature points of the image to be tested and the template image respectively;

[0027] (2) Convert SIFT feature points into description matrix for Flann feature matching;

[0028] (3) After feature matching, RANSAC is used to filter and calculate the transfer correction matrix;

[0029] (4) According to the transfer correction matrix, the image to be tested is affine transformed to complete the calibration.

[0030] Preferably, in step 4, the sub-weld point image extraction process is:

[0031] (1) Obtain a chip sub-image containing a single chip and all its corresponding solder joints according to the configuration file;

[0032] (2) Obtain images of each solder joint one by one according to the position of the solder joint relative to the chip in the solder joint position model, namely, the sub-solder joint image.

[0033] Preferably, in step 5, the calculation formula of the normalized geometric intersection coefficient γ is:

[0034]

[0035] Among them, X mn is the element of the standard solder characteristic matrix, Y mn is the element of the solder characteristic matrix to be tested, sbs means taking the absolute value, m and n represent the rows and columns of the matrix.

[0036] Preferably, according to calculation experience, the threshold is 0.7, and when the normalized geometric intersection coefficient γ is less than 0.7, the corresponding solder joint is considered to be defective.

[0037] Beneficial effects achieved by this application:

[0038] The present invention uses self-learning image processing technology to identify defects and has application feasibility. The present invention can effectively reduce the missed detection rate, improve efficiency and accuracy, and reduce the workload of manual defect search; at the same time, it can avoid the problem PCB board being detected until the next process, and can effectively realize earlier problem discovery and solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flow chart of the method of the present invention;

[0040] Figure 2 It is an implementation diagram of the method of the present invention. DETAILED DESCRIPTION

[0041] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0042] like Figure 1 and 2 As shown, the circuit board pin defect recognition method based on feature self-learning of the present invention comprises the following steps:

[0043] Step 1: Obtain the standard circuit board AOI color image and corresponding configuration file corresponding to the circuit board to be tested for feature self-learning, including the chip model and chip position on the circuit board;

[0044] Step 2: Establish a standard solder joint model of the chip in the AOI color image of the standard circuit board, including the solder joint position model and the standard solder feature matrix X, specifically including:

[0045] Step 2.1: Expand the chip area with the center of the chip as the center to obtain a chip matrix;

[0046] In specific implementation, the rectangular area where the chip is located is expanded 1.5 times with the center of the chip as the center to obtain a chip matrix.

[0047] For example, the chip height is 50 and the width is 100, forming a rectangular area where the chip is located. The center of the area is the center of the chip, and the area is expanded 1.5 times to obtain the area containing the solder joints: the height is 75 and the width is 150, and the chip matrix is ​​obtained.

[0048] Step 2.2: Search for solder joints in the area expanded in step 2.1. When searching for solder joints, obtain the ROI solder joint region of interest based on color information and extract the solder joint matrix, thereby obtaining the solder joint position model of the chip model;

[0049] Considering that the blue solder part is an important position to ensure the quality of the solder joint, the blue part is extracted to obtain the ROI region of interest;

[0050] Specifically, the RGB image is converted into an HSV image, the blue part in the HSV image is extracted as the solder point matrix, and then the position of the solder point matrix relative to the chip matrix and the solder point bounding box are obtained, and saved as the solder point position model of the chip model.

[0051] The solder joint bounding box is a rectangular frame including the solder joint and the chip.

[0052] The extraction range is: H: (100, 124), S: (43, 255), V: (46, 255).

[0053] Step 2.3: Obtain all solder joint matrices in the expanded area, which are all defect-free solder joints, and calculate the solder height value of each pixel in the solder joint matrix;

[0054] The calculation formula for solder height is:

[0055] height=BG / 5.-R / 3.0

[0056] Among them, B, G, and R are the B component value, G component value, and R component value of the corresponding pixel RGB respectively.

[0057] Step 2.4: Calculate the average solder height value of each pixel in the same solder joint matrix to form the standard solder feature matrix X of the solder joint.

[0058] The solder joints of the same chip pins are highly similar.

[0059] Step 3: Obtain the AOI color image of the circuit board to be tested, perform SIFT image comparison between it and the AOI color image of the standard circuit board, and obtain the chip sub-image of the chip in the circuit board to be tested. If the circuit board contains multiple chips, then step 3 obtains multiple chip sub-images, each chip sub-image contains a single chip and all its corresponding solder joints;

[0060] The SIFT image is relatively accurate, specifically including:

[0061] (1) Calculate the SIFT feature points of the image to be tested and the template image respectively;

[0062] (2) Convert SIFT feature points into description matrix for Flann feature matching;

[0063] (3) After feature matching, RANSAC is used to filter and calculate the transfer correction matrix;

[0064] (4) According to the transfer correction matrix, the image to be tested is affine transformed to complete the calibration.

[0065] Step 4: Based on the solder joint position model in step 2, extract the corresponding sub-solder joint image from each chip sub-image, each sub-solder joint image includes a single solder joint, calculate the solder height value of each pixel in each sub-solder joint image, and form the solder feature matrix Y of the corresponding solder joint;

[0066] The sub-solder point image extraction process is as follows:

[0067] (1) Obtain a chip sub-image containing a single chip and all its corresponding solder joints according to the configuration file;

[0068] (2) Obtain images of each solder joint one by one according to the position of the solder joint relative to the chip in the solder joint position model, namely, the sub-solder joint image.

[0069] It can be understood that the position of each chip and its corresponding solder joint are included in the solder joint configuration model file.

[0070] Step 5: Calculate the normalized geometric intersection coefficient γ between the solder feature matrix Y and the corresponding standard solder feature matrix X, and determine whether the solder joints are defective one by one according to the geometric intersection coefficient threshold.

[0071] The calculation formula of normalized geometric intersection coefficient γ is:

[0072]

[0073] Among them, X mn is the element of the standard solder characteristic matrix, Y mn is the element of the solder characteristic matrix to be tested, sbs means taking the absolute value, m and n represent the rows and columns of the matrix.

[0074] The closer the coefficient is to 1, the more similar the two solder joints are.

[0075] According to calculation experience, the threshold is set to 0.7. When the normalized geometric intersection coefficient γ is less than 0.7, the corresponding solder joint is considered to be defective.

[0076] Step 6: When you get a new board, repeat steps 1-2 to continue learning and updating the model.

[0077] The present invention uses self-learning image processing technology to identify defects and has application feasibility. The present invention can effectively reduce the missed detection rate, improve efficiency and accuracy, and reduce the workload of manual defect search; at the same time, it can avoid the problem PCB board being detected until the next process, and can effectively realize earlier problem discovery and solution.

[0078] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A circuit board pin defect recognition method based on feature self-learning, characterized by: The method comprises the following steps: Step 1: Obtain the standard circuit board AOI color image and corresponding configuration file corresponding to the circuit board to be tested for feature self-learning, including the chip model and chip position on the circuit board; Step 2: Establish a standard solder joint model of the chip in the AOI color image of the standard circuit board, including the solder joint position model and the standard solder feature matrix X; Step 3: Obtain the AOI color image of the circuit board to be tested, and perform SIFT image comparison between it and the AOI color image of the standard circuit board to obtain the chip sub-image of the chip in the circuit board to be tested. Each chip sub-image contains a single chip and all its corresponding solder joints. Step 4: Based on the solder joint position model in step 2, extract the corresponding sub-solder joint image from each chip sub-image, each sub-solder joint image includes a single solder joint, calculate the solder height value of each pixel in each sub-solder joint image, and form the solder feature matrix Y of the corresponding solder joint; Step 5: Calculate the normalized geometric intersection coefficient γ between the solder feature matrix Y and the corresponding standard solder feature matrix X, and determine whether the solder joints are defective one by one according to the geometric intersection coefficient threshold.

2. The circuit board pin defect recognition method based on feature self-learning according to claim 1 is characterized in that: Step 2 specifically includes: Step 2.1: Expand the chip area with the center of the chip as the center to obtain the chip matrix of the corresponding phase model; Step 2.2: Search for solder joints in the area expanded in step 2.

1. When searching for solder joints, obtain the ROI solder joint region of interest based on color information and extract the solder joint matrix, thereby obtaining the solder joint position model of the chip model; Step 2.3: Obtain all solder point matrices in the expanded area and calculate the solder height value of each pixel in the solder point matrix; Step 2.4: Calculate the average solder height value of each pixel in the same solder joint matrix to form the standard solder feature matrix X of the solder joint.

3. The circuit board pin defect recognition method based on feature self-learning according to claim 2 is characterized in that: In step 2.1, the rectangular area where the chip is located is expanded 1.5 times with the center of the chip as the center to obtain the chip matrix.

4. The circuit board pin defect recognition method based on feature self-learning according to claim 2 is characterized in that: In step 2.2, the RGB image is converted into an HSV image, and the blue part in the HSV image is extracted as the solder point matrix, and then the position of the solder point matrix relative to the chip matrix and the solder point bounding box are obtained, and saved as the solder point position model of the chip of this model; the solder point bounding box is a rectangular frame containing the solder point and the chip.

5. The circuit board pin defect recognition method based on feature self-learning according to claim 2 is characterized in that: In step 2.2, the extraction range is: H: (100, 124), S: (43, 255), V: (46, 255).

6. The circuit board pin defect recognition method based on feature self-learning according to claim 2 is characterized in that: In step 2.3, the calculation formula for solder height is: height=BG / 5.-R / 3.0 Among them, B, G, and R are the B component value, G component value, and R component value of the corresponding pixel RGB respectively.

7. The circuit board pin defect recognition method based on feature self-learning according to claim 1 is characterized in that: The SIFT image described in step 3 is relatively accurate, specifically including: (1) Calculate the SIFT feature points of the image to be tested and the template image respectively; (2) Convert SIFT feature points into description matrix for Flann feature matching; (3) After feature matching, RANSAC is used to filter and calculate the transfer correction matrix; (4) According to the transfer correction matrix, the image to be tested is affine transformed to complete the calibration.

8. The circuit board pin defect recognition method based on feature self-learning according to claim 1 is characterized in that: In step 4, the sub-solder point image extraction process is as follows: (1) Obtain a chip sub-image containing a single chip and all its corresponding solder joints according to the configuration file; (2) Obtain images of each solder joint one by one according to the position of the solder joint relative to the chip in the solder joint position model, namely, the sub-solder joint image.

9. The circuit board pin defect recognition method based on feature self-learning according to claim 1, characterized in that: In step 5, the normalized geometric intersection coefficient γ is calculated as: Among them, X mn is the element of the standard solder characteristic matrix, Y mn is the element of the solder characteristic matrix to be tested, sbs means taking the absolute value, m and n represent the rows and columns of the matrix.

10. The circuit board pin defect recognition method based on feature self-learning according to claim 9, characterized in that: According to calculation experience, the threshold is 0.

7. When the normalized geometric intersection coefficient γ is less than 0.7, the corresponding solder joint is considered to be defective.

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